1 /* $NetBSD: clmpcc.c,v 1.38 2008/04/28 20:23:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.38 2008/04/28 20:23:49 martin Exp $"); 38 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ioctl.h> 44 #include <sys/select.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/conf.h> 49 #include <sys/file.h> 50 #include <sys/uio.h> 51 #include <sys/kernel.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/kauth.h> 56 #include <sys/intr.h> 57 58 #include <sys/bus.h> 59 #include <machine/param.h> 60 61 #include <dev/ic/clmpccreg.h> 62 #include <dev/ic/clmpccvar.h> 63 #include <dev/cons.h> 64 65 66 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 67 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 68 #endif 69 70 71 static int clmpcc_init(struct clmpcc_softc *sc); 72 static void clmpcc_shutdown(struct clmpcc_chan *); 73 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *); 74 static int clmpcc_param(struct tty *, struct termios *); 75 static void clmpcc_set_params(struct clmpcc_chan *); 76 static void clmpcc_start(struct tty *); 77 static int clmpcc_modem_control(struct clmpcc_chan *, int, int); 78 79 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 80 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 81 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 82 83 /* 84 * These should be in a header file somewhere... 85 */ 86 #define ISCLR(v, f) (((v) & (f)) == 0) 87 88 extern struct cfdriver clmpcc_cd; 89 90 dev_type_open(clmpccopen); 91 dev_type_close(clmpccclose); 92 dev_type_read(clmpccread); 93 dev_type_write(clmpccwrite); 94 dev_type_ioctl(clmpccioctl); 95 dev_type_stop(clmpccstop); 96 dev_type_tty(clmpcctty); 97 dev_type_poll(clmpccpoll); 98 99 const struct cdevsw clmpcc_cdevsw = { 100 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl, 101 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY 102 }; 103 104 /* 105 * Make this an option variable one can patch. 106 */ 107 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 108 109 110 /* 111 * Things needed when the device is used as a console 112 */ 113 static struct clmpcc_softc *cons_sc = NULL; 114 static int cons_chan; 115 static int cons_rate; 116 117 static int clmpcc_common_getc(struct clmpcc_softc *, int); 118 static void clmpcc_common_putc(struct clmpcc_softc *, int, int); 119 int clmpcccngetc(dev_t); 120 void clmpcccnputc(dev_t, int); 121 122 123 /* 124 * Convenience functions, inlined for speed 125 */ 126 #define integrate static inline 127 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int); 128 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int); 129 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int); 130 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int); 131 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *, 132 u_int); 133 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int); 134 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int); 135 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *); 136 137 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 138 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 139 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 140 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 141 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 142 143 144 integrate u_int8_t 145 clmpcc_rdreg(sc, offset) 146 struct clmpcc_softc *sc; 147 u_int offset; 148 { 149 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 150 offset ^= sc->sc_byteswap; 151 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 152 offset ^= CLMPCC_BYTESWAP_HIGH; 153 #endif 154 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 155 } 156 157 integrate void 158 clmpcc_wrreg(sc, offset, val) 159 struct clmpcc_softc *sc; 160 u_int offset; 161 u_int val; 162 { 163 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 164 offset ^= sc->sc_byteswap; 165 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 166 offset ^= CLMPCC_BYTESWAP_HIGH; 167 #endif 168 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 169 } 170 171 integrate u_int8_t 172 clmpcc_rdreg_odd(sc, offset) 173 struct clmpcc_softc *sc; 174 u_int offset; 175 { 176 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 177 offset ^= (sc->sc_byteswap & 2); 178 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 179 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 180 #endif 181 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 182 } 183 184 integrate void 185 clmpcc_wrreg_odd(sc, offset, val) 186 struct clmpcc_softc *sc; 187 u_int offset; 188 u_int val; 189 { 190 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 191 offset ^= (sc->sc_byteswap & 2); 192 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 193 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 194 #endif 195 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 196 } 197 198 integrate void 199 clmpcc_wrtx_multi(sc, buff, count) 200 struct clmpcc_softc *sc; 201 u_int8_t *buff; 202 u_int count; 203 { 204 u_int offset = CLMPCC_REG_TDR; 205 206 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 207 offset ^= (sc->sc_byteswap & 2); 208 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 209 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 210 #endif 211 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 212 } 213 214 integrate u_int8_t 215 clmpcc_select_channel(sc, new_chan) 216 struct clmpcc_softc *sc; 217 u_int new_chan; 218 { 219 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 220 221 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 222 223 return old_chan; 224 } 225 226 integrate void 227 clmpcc_channel_cmd(sc, chan, cmd) 228 struct clmpcc_softc *sc; 229 int chan; 230 int cmd; 231 { 232 int i; 233 234 for (i = 5000; i; i--) { 235 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 236 break; 237 delay(1); 238 } 239 240 if ( i == 0 ) 241 printf("%s: channel %d command timeout (idle)\n", 242 device_xname(&sc->sc_dev), chan); 243 244 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 245 } 246 247 integrate void 248 clmpcc_enable_transmitter(ch) 249 struct clmpcc_chan *ch; 250 { 251 u_int old; 252 int s; 253 254 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 255 256 s = splserial(); 257 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 258 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 259 SET(ch->ch_tty->t_state, TS_BUSY); 260 splx(s); 261 262 clmpcc_select_channel(ch->ch_sc, old); 263 } 264 265 static int 266 clmpcc_speed(sc, speed, cor, bpr) 267 struct clmpcc_softc *sc; 268 speed_t speed; 269 int *cor, *bpr; 270 { 271 int c, co, br; 272 273 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 274 br = ((sc->sc_clk / c) / speed) - 1; 275 if ( br < 0x100 ) { 276 *cor = co; 277 *bpr = br; 278 return 0; 279 } 280 } 281 282 return -1; 283 } 284 285 void 286 clmpcc_attach(sc) 287 struct clmpcc_softc *sc; 288 { 289 struct clmpcc_chan *ch; 290 struct tty *tp; 291 int chan; 292 293 if ( cons_sc != NULL && 294 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 295 cons_sc = sc; 296 297 /* Initialise the chip */ 298 clmpcc_init(sc); 299 300 printf(": Cirrus Logic CD240%c Serial Controller\n", 301 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 302 303 sc->sc_softintr_cookie = 304 softint_establish(SOFTINT_SERIAL, clmpcc_softintr, sc); 305 if (sc->sc_softintr_cookie == NULL) 306 panic("clmpcc_attach: softintr_establish"); 307 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 308 309 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 310 ch = &sc->sc_chans[chan]; 311 312 ch->ch_sc = sc; 313 ch->ch_car = chan; 314 315 tp = ttymalloc(); 316 tp->t_oproc = clmpcc_start; 317 tp->t_param = clmpcc_param; 318 319 ch->ch_tty = tp; 320 321 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 322 if ( ch->ch_ibuf == NULL ) { 323 aprint_error_dev(&sc->sc_dev, "(%d): unable to allocate ring buffer\n", 324 chan); 325 return; 326 } 327 328 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 329 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 330 331 tty_attach(tp); 332 } 333 334 aprint_error_dev(&sc->sc_dev, "%d channels available", 335 CLMPCC_NUM_CHANS); 336 if ( cons_sc == sc ) { 337 printf(", console on channel %d.\n", cons_chan); 338 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 339 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 340 } else 341 printf(".\n"); 342 } 343 344 static int 345 clmpcc_init(sc) 346 struct clmpcc_softc *sc; 347 { 348 u_int tcor, tbpr; 349 u_int rcor, rbpr; 350 u_int msvr_rts, msvr_dtr; 351 u_int ccr; 352 int is_console; 353 int i; 354 355 /* 356 * All we're really concerned about here is putting the chip 357 * into a quiescent state so that it won't do anything until 358 * clmpccopen() is called. (Except the console channel.) 359 */ 360 361 /* 362 * If the chip is acting as console, set all channels to the supplied 363 * console baud rate. Otherwise, plump for 9600. 364 */ 365 if ( cons_sc && 366 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 367 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 368 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 369 is_console = 1; 370 } else { 371 clmpcc_speed(sc, 9600, &tcor, &tbpr); 372 clmpcc_speed(sc, 9600, &rcor, &rbpr); 373 is_console = 0; 374 } 375 376 /* Allow any pending output to be sent */ 377 delay(10000); 378 379 /* Send the Reset All command to channel 0 (resets all channels!) */ 380 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 381 382 delay(1000); 383 384 /* 385 * The chip will set it's firmware revision register to a non-zero 386 * value to indicate completion of reset. 387 */ 388 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 389 delay(1); 390 391 if ( i == 0 ) { 392 /* 393 * Watch out... If this chip is console, the message 394 * probably won't be sent since we just reset it! 395 */ 396 aprint_error_dev(&sc->sc_dev, "Failed to reset chip\n"); 397 return -1; 398 } 399 400 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 401 clmpcc_select_channel(sc, i); 402 403 /* All interrupts are disabled to begin with */ 404 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 405 406 /* Make sure the channel interrupts on the correct vectors */ 407 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 408 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 409 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 410 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 411 412 /* Receive timer prescaler set to 1ms */ 413 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 414 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 415 416 /* We support Async mode only */ 417 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 418 419 /* Set the required baud rate */ 420 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 421 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 422 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 423 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 424 425 /* Always default to 8N1 (XXX what about console?) */ 426 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 427 CLMPCC_COR1_NO_PARITY | 428 CLMPCC_COR1_IGNORE_PAR); 429 430 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 431 432 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 433 434 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 435 CLMPCC_COR4_CDzd | 436 CLMPCC_COR4_CTSzd); 437 438 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 439 CLMPCC_COR5_CDod | 440 CLMPCC_COR5_CTSod | 441 CLMPCC_COR5_FLOW_NORM); 442 443 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 444 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 445 446 /* Set the receive FIFO timeout */ 447 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 448 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 449 450 /* At this point, we set up the console differently */ 451 if ( is_console && i == cons_chan ) { 452 msvr_rts = CLMPCC_MSVR_RTS; 453 msvr_dtr = CLMPCC_MSVR_DTR; 454 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 455 } else { 456 msvr_rts = 0; 457 msvr_dtr = 0; 458 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 459 } 460 461 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 462 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 463 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 464 delay(100); 465 } 466 467 return 0; 468 } 469 470 static void 471 clmpcc_shutdown(ch) 472 struct clmpcc_chan *ch; 473 { 474 int oldch; 475 476 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 477 478 /* Turn off interrupts. */ 479 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 480 481 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 482 /* Disable the transmitter and receiver */ 483 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 484 CLMPCC_CCR_T0_TX_DIS); 485 486 /* Drop RTS and DTR */ 487 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 488 } 489 490 clmpcc_select_channel(ch->ch_sc, oldch); 491 } 492 493 int 494 clmpccopen(dev, flag, mode, l) 495 dev_t dev; 496 int flag, mode; 497 struct lwp *l; 498 { 499 struct clmpcc_softc *sc; 500 struct clmpcc_chan *ch; 501 struct tty *tp; 502 int oldch; 503 int error; 504 505 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 506 if (sc == NULL) 507 return (ENXIO); 508 509 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 510 511 tp = ch->ch_tty; 512 513 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 514 return EBUSY; 515 516 /* 517 * Do the following iff this is a first open. 518 */ 519 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 520 521 ttychars(tp); 522 523 tp->t_dev = dev; 524 tp->t_iflag = TTYDEF_IFLAG; 525 tp->t_oflag = TTYDEF_OFLAG; 526 tp->t_lflag = TTYDEF_LFLAG; 527 tp->t_cflag = TTYDEF_CFLAG; 528 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 529 530 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 531 SET(tp->t_cflag, CLOCAL); 532 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 533 SET(tp->t_cflag, CRTSCTS); 534 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 535 SET(tp->t_cflag, MDMBUF); 536 537 /* 538 * Override some settings if the channel is being 539 * used as the console. 540 */ 541 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 542 tp->t_ospeed = tp->t_ispeed = cons_rate; 543 SET(tp->t_cflag, CLOCAL); 544 CLR(tp->t_cflag, CRTSCTS); 545 CLR(tp->t_cflag, HUPCL); 546 } 547 548 ch->ch_control = 0; 549 550 clmpcc_param(tp, &tp->t_termios); 551 ttsetwater(tp); 552 553 /* Clear the input ring */ 554 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 555 556 /* Select the channel */ 557 oldch = clmpcc_select_channel(sc, ch->ch_car); 558 559 /* Reset it */ 560 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 561 CLMPCC_CCR_T0_RX_EN | 562 CLMPCC_CCR_T0_TX_EN); 563 564 /* Enable receiver and modem change interrupts. */ 565 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 566 CLMPCC_IER_RET | 567 CLMPCC_IER_RX_FIFO); 568 569 /* Raise RTS and DTR */ 570 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 571 572 clmpcc_select_channel(sc, oldch); 573 } 574 575 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 576 if (error) 577 goto bad; 578 579 error = (*tp->t_linesw->l_open)(dev, tp); 580 if (error) 581 goto bad; 582 583 return 0; 584 585 bad: 586 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 587 /* 588 * We failed to open the device, and nobody else had it opened. 589 * Clean up the state as appropriate. 590 */ 591 clmpcc_shutdown(ch); 592 } 593 594 return error; 595 } 596 597 int 598 clmpccclose(dev, flag, mode, l) 599 dev_t dev; 600 int flag, mode; 601 struct lwp *l; 602 { 603 struct clmpcc_softc *sc = 604 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 605 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 606 struct tty *tp = ch->ch_tty; 607 int s; 608 609 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 610 return 0; 611 612 (*tp->t_linesw->l_close)(tp, flag); 613 614 s = spltty(); 615 616 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 617 /* 618 * Although we got a last close, the device may still be in 619 * use; e.g. if this was the dialout node, and there are still 620 * processes waiting for carrier on the non-dialout node. 621 */ 622 clmpcc_shutdown(ch); 623 } 624 625 ttyclose(tp); 626 627 splx(s); 628 629 return 0; 630 } 631 632 int 633 clmpccread(dev, uio, flag) 634 dev_t dev; 635 struct uio *uio; 636 int flag; 637 { 638 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 639 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 640 641 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 642 } 643 644 int 645 clmpccwrite(dev, uio, flag) 646 dev_t dev; 647 struct uio *uio; 648 int flag; 649 { 650 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 651 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 652 653 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 654 } 655 656 int 657 clmpccpoll(dev, events, l) 658 dev_t dev; 659 int events; 660 struct lwp *l; 661 { 662 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 663 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 664 665 return ((*tp->t_linesw->l_poll)(tp, events, l)); 666 } 667 668 struct tty * 669 clmpcctty(dev) 670 dev_t dev; 671 { 672 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 673 674 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 675 } 676 677 int 678 clmpccioctl(dev, cmd, data, flag, l) 679 dev_t dev; 680 u_long cmd; 681 void *data; 682 int flag; 683 struct lwp *l; 684 { 685 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 686 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 687 struct tty *tp = ch->ch_tty; 688 int error; 689 690 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 691 if (error != EPASSTHROUGH) 692 return error; 693 694 error = ttioctl(tp, cmd, data, flag, l); 695 if (error != EPASSTHROUGH) 696 return error; 697 698 error = 0; 699 700 switch (cmd) { 701 case TIOCSBRK: 702 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 703 clmpcc_enable_transmitter(ch); 704 break; 705 706 case TIOCCBRK: 707 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 708 clmpcc_enable_transmitter(ch); 709 break; 710 711 case TIOCSDTR: 712 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 713 break; 714 715 case TIOCCDTR: 716 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 717 break; 718 719 case TIOCMSET: 720 clmpcc_modem_control(ch, *((int *)data), DMSET); 721 break; 722 723 case TIOCMBIS: 724 clmpcc_modem_control(ch, *((int *)data), DMBIS); 725 break; 726 727 case TIOCMBIC: 728 clmpcc_modem_control(ch, *((int *)data), DMBIC); 729 break; 730 731 case TIOCMGET: 732 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 733 break; 734 735 case TIOCGFLAGS: 736 *((int *)data) = ch->ch_openflags; 737 break; 738 739 case TIOCSFLAGS: 740 error = kauth_authorize_device_tty(l->l_cred, 741 KAUTH_DEVICE_TTY_PRIVSET, tp); 742 if ( error ) 743 break; 744 ch->ch_openflags = *((int *)data) & 745 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 746 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 747 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 748 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 749 break; 750 751 default: 752 error = EPASSTHROUGH; 753 break; 754 } 755 756 return error; 757 } 758 759 int 760 clmpcc_modem_control(ch, bits, howto) 761 struct clmpcc_chan *ch; 762 int bits; 763 int howto; 764 { 765 struct clmpcc_softc *sc = ch->ch_sc; 766 struct tty *tp = ch->ch_tty; 767 int oldch; 768 int msvr; 769 int rbits = 0; 770 771 oldch = clmpcc_select_channel(sc, ch->ch_car); 772 773 switch ( howto ) { 774 case DMGET: 775 msvr = clmpcc_rd_msvr(sc); 776 777 if ( sc->sc_swaprtsdtr ) { 778 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 779 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 780 } else { 781 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 782 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 783 } 784 785 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 786 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 787 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 788 break; 789 790 case DMSET: 791 if ( sc->sc_swaprtsdtr ) { 792 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 793 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 794 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 795 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 796 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 797 } else { 798 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 799 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 800 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 801 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 802 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 803 } 804 break; 805 806 case DMBIS: 807 if ( sc->sc_swaprtsdtr ) { 808 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 809 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 810 if ( ISSET(bits, TIOCM_DTR) ) 811 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 812 } else { 813 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 814 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 815 if ( ISSET(bits, TIOCM_DTR) ) 816 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 817 } 818 break; 819 820 case DMBIC: 821 if ( sc->sc_swaprtsdtr ) { 822 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 823 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 824 if ( ISCLR(bits, TIOCM_DTR) ) 825 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 826 } else { 827 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 828 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 829 if ( ISCLR(bits, TIOCM_DTR) ) 830 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 831 } 832 break; 833 } 834 835 clmpcc_select_channel(sc, oldch); 836 837 return rbits; 838 } 839 840 static int 841 clmpcc_param(tp, t) 842 struct tty *tp; 843 struct termios *t; 844 { 845 struct clmpcc_softc *sc = 846 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 847 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 848 u_char cor; 849 u_char oldch; 850 int oclk, obpr; 851 int iclk, ibpr; 852 int s; 853 854 /* Check requested parameters. */ 855 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 856 return EINVAL; 857 858 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 859 return EINVAL; 860 861 /* 862 * For the console, always force CLOCAL and !HUPCL, so that the port 863 * is always active. 864 */ 865 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 866 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 867 SET(t->c_cflag, CLOCAL); 868 CLR(t->c_cflag, HUPCL); 869 } 870 871 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 872 873 /* If ospeed it zero, hangup the line */ 874 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 875 876 if ( t->c_ospeed ) { 877 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 878 ch->ch_tbpr = obpr; 879 } else { 880 ch->ch_tcor = 0; 881 ch->ch_tbpr = 0; 882 } 883 884 if ( t->c_ispeed ) { 885 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 886 ch->ch_rbpr = ibpr; 887 } else { 888 ch->ch_rcor = 0; 889 ch->ch_rbpr = 0; 890 } 891 892 /* Work out value to use for COR1 */ 893 cor = 0; 894 if ( ISSET(t->c_cflag, PARENB) ) { 895 cor |= CLMPCC_COR1_NORM_PARITY; 896 if ( ISSET(t->c_cflag, PARODD) ) 897 cor |= CLMPCC_COR1_ODD_PARITY; 898 } 899 900 if ( ISCLR(t->c_cflag, INPCK) ) 901 cor |= CLMPCC_COR1_IGNORE_PAR; 902 903 switch ( t->c_cflag & CSIZE ) { 904 case CS5: 905 cor |= CLMPCC_COR1_CHAR_5BITS; 906 break; 907 908 case CS6: 909 cor |= CLMPCC_COR1_CHAR_6BITS; 910 break; 911 912 case CS7: 913 cor |= CLMPCC_COR1_CHAR_7BITS; 914 break; 915 916 case CS8: 917 cor |= CLMPCC_COR1_CHAR_8BITS; 918 break; 919 } 920 921 ch->ch_cor1 = cor; 922 923 /* 924 * The only interesting bit in COR2 is 'CTS Automatic Enable' 925 * when hardware flow control is in effect. 926 */ 927 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 928 929 /* COR3 needs to be set to the number of stop bits... */ 930 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 931 CLMPCC_COR3_STOP_1; 932 933 /* 934 * COR4 contains the FIFO threshold setting. 935 * We adjust the threshold depending on the input speed... 936 */ 937 if ( t->c_ispeed <= 1200 ) 938 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 939 else if ( t->c_ispeed <= 19200 ) 940 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 941 else 942 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 943 944 /* 945 * If chip is used with CTS and DTR swapped, we can enable 946 * automatic hardware flow control. 947 */ 948 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 949 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 950 else 951 ch->ch_cor5 = 0; 952 953 s = splserial(); 954 oldch = clmpcc_select_channel(sc, ch->ch_car); 955 956 /* 957 * COR2 needs to be set immediately otherwise we might never get 958 * a Tx EMPTY interrupt to change the other parameters. 959 */ 960 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 961 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 962 963 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 964 clmpcc_set_params(ch); 965 else 966 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 967 968 clmpcc_select_channel(sc, oldch); 969 970 splx(s); 971 972 return 0; 973 } 974 975 static void 976 clmpcc_set_params(ch) 977 struct clmpcc_chan *ch; 978 { 979 struct clmpcc_softc *sc = ch->ch_sc; 980 u_char r1; 981 u_char r2; 982 983 if ( ch->ch_tcor || ch->ch_tbpr ) { 984 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 985 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 986 /* Only write Tx rate if it really has changed */ 987 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 988 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 989 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 990 } 991 } 992 993 if ( ch->ch_rcor || ch->ch_rbpr ) { 994 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 995 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 996 /* Only write Rx rate if it really has changed */ 997 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 998 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 999 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1000 } 1001 } 1002 1003 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1004 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1005 /* Any change to COR1 requires an INIT command */ 1006 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1007 } 1008 1009 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1010 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1011 1012 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1013 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1014 /* 1015 * Note: If the FIFO has changed, we always set it to 1016 * zero here and disable the Receive Timeout interrupt. 1017 * It's up to the Rx Interrupt handler to pick the 1018 * appropriate moment to write the new FIFO length. 1019 */ 1020 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1021 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1022 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1023 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1024 } 1025 1026 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1027 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1028 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1029 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1030 } 1031 } 1032 1033 static void 1034 clmpcc_start(tp) 1035 struct tty *tp; 1036 { 1037 struct clmpcc_softc *sc = 1038 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1039 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1040 u_int oldch; 1041 int s; 1042 1043 s = spltty(); 1044 1045 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1046 ttypull(tp); 1047 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1048 CLMPCC_FLG_END_BREAK) || 1049 tp->t_outq.c_cc > 0 ) { 1050 1051 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1052 CLMPCC_FLG_END_BREAK) ) { 1053 ch->ch_obuf_addr = tp->t_outq.c_cf; 1054 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1055 } 1056 1057 /* Enable TX empty interrupts */ 1058 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1059 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1060 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1061 CLMPCC_IER_TX_EMPTY); 1062 clmpcc_select_channel(ch->ch_sc, oldch); 1063 SET(tp->t_state, TS_BUSY); 1064 } 1065 } 1066 1067 splx(s); 1068 } 1069 1070 /* 1071 * Stop output on a line. 1072 */ 1073 void 1074 clmpccstop(tp, flag) 1075 struct tty *tp; 1076 int flag; 1077 { 1078 struct clmpcc_softc *sc = 1079 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1080 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1081 int s; 1082 1083 s = splserial(); 1084 1085 if ( ISSET(tp->t_state, TS_BUSY) ) { 1086 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1087 SET(tp->t_state, TS_FLUSH); 1088 ch->ch_obuf_size = 0; 1089 } 1090 splx(s); 1091 } 1092 1093 /* 1094 * RX interrupt routine 1095 */ 1096 int 1097 clmpcc_rxintr(arg) 1098 void *arg; 1099 { 1100 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1101 struct clmpcc_chan *ch; 1102 u_int8_t *put, *end, rxd; 1103 u_char errstat; 1104 u_char fc, tc; 1105 u_char risr; 1106 u_char rir; 1107 #ifdef DDB 1108 int saw_break = 0; 1109 #endif 1110 1111 /* Receive interrupt active? */ 1112 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1113 1114 /* 1115 * If we're using auto-vectored interrupts, we have to 1116 * verify if the chip is generating the interrupt. 1117 */ 1118 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1119 return 0; 1120 1121 /* Get pointer to interrupting channel's data structure */ 1122 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1123 1124 /* Get the interrupt status register */ 1125 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1126 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1127 u_char reg; 1128 /* 1129 * Set the FIFO threshold to zero, and disable 1130 * further receive timeout interrupts. 1131 */ 1132 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1133 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1134 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1135 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1136 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1137 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1138 return 1; 1139 } 1140 1141 /* How many bytes are waiting in the FIFO? */ 1142 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1143 1144 #ifdef DDB 1145 /* 1146 * Allow BREAK on the console to drop to the debugger. 1147 */ 1148 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1149 risr & CLMPCC_RISR_BREAK ) { 1150 saw_break = 1; 1151 } 1152 #endif 1153 1154 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1155 /* Just get rid of the data */ 1156 while ( fc-- ) 1157 (void) clmpcc_rd_rxdata(sc); 1158 goto rx_done; 1159 } 1160 1161 put = ch->ch_ibuf_wr; 1162 end = ch->ch_ibuf_end; 1163 1164 /* 1165 * Note: The chip is completely hosed WRT these error 1166 * conditions; there seems to be no way to associate 1167 * the error with the correct character in the FIFO. 1168 * We compromise by tagging the first character we read 1169 * with the error. Not perfect, but there's no other way. 1170 */ 1171 errstat = 0; 1172 if ( risr & CLMPCC_RISR_PARITY ) 1173 errstat |= TTY_PE; 1174 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1175 errstat |= TTY_FE; 1176 1177 /* 1178 * As long as there are characters in the FIFO, and we 1179 * have space for them... 1180 */ 1181 while ( fc > 0 ) { 1182 1183 *put++ = rxd = clmpcc_rd_rxdata(sc); 1184 *put++ = errstat; 1185 1186 if ( put >= end ) 1187 put = ch->ch_ibuf; 1188 1189 if ( put == ch->ch_ibuf_rd ) { 1190 put -= 2; 1191 if ( put < ch->ch_ibuf ) 1192 put = end - 2; 1193 } 1194 1195 errstat = 0; 1196 fc--; 1197 } 1198 1199 ch->ch_ibuf_wr = put; 1200 1201 #if 0 1202 if ( sc->sc_swaprtsdtr == 0 && 1203 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1204 /* 1205 * If RTS/DTR are not physically swapped, we have to 1206 * do hardware flow control manually 1207 */ 1208 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1209 } 1210 #endif 1211 1212 rx_done: 1213 if ( fc != tc ) { 1214 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1215 u_char reg; 1216 /* 1217 * Set the FIFO threshold to the preset value, 1218 * and enable receive timeout interrupts. 1219 */ 1220 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1221 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1222 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1223 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1224 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1225 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1226 } 1227 1228 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1229 softint_schedule(sc->sc_softintr_cookie); 1230 } else 1231 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1232 1233 #ifdef DDB 1234 /* 1235 * Only =after= we write REOIR is it safe to drop to the debugger. 1236 */ 1237 if ( saw_break ) 1238 Debugger(); 1239 #endif 1240 1241 return 1; 1242 } 1243 1244 /* 1245 * Tx interrupt routine 1246 */ 1247 int 1248 clmpcc_txintr(arg) 1249 void *arg; 1250 { 1251 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1252 struct clmpcc_chan *ch; 1253 struct tty *tp; 1254 u_char ftc, oftc; 1255 u_char tir, teoir; 1256 int etcmode = 0; 1257 1258 /* Tx interrupt active? */ 1259 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1260 1261 /* 1262 * If we're using auto-vectored interrupts, we have to 1263 * verify if the chip is generating the interrupt. 1264 */ 1265 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1266 return 0; 1267 1268 /* Get pointer to interrupting channel's data structure */ 1269 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1270 tp = ch->ch_tty; 1271 1272 /* Dummy read of the interrupt status register */ 1273 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1274 1275 /* Make sure embedded transmit commands are disabled */ 1276 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1277 1278 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1279 1280 /* Handle a delayed parameter change */ 1281 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1282 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1283 clmpcc_set_params(ch); 1284 } 1285 1286 if ( ch->ch_obuf_size > 0 ) { 1287 u_int n = min(ch->ch_obuf_size, ftc); 1288 1289 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1290 1291 ftc -= n; 1292 ch->ch_obuf_size -= n; 1293 ch->ch_obuf_addr += n; 1294 1295 } else { 1296 /* 1297 * Check if we should start/stop a break 1298 */ 1299 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1300 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1301 /* Enable embedded transmit commands */ 1302 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1303 ch->ch_cor2 | CLMPCC_COR2_ETC); 1304 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1305 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1306 ftc -= 2; 1307 etcmode = 1; 1308 } 1309 1310 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1311 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1312 /* Enable embedded transmit commands */ 1313 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1314 ch->ch_cor2 | CLMPCC_COR2_ETC); 1315 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1316 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1317 ftc -= 2; 1318 etcmode = 1; 1319 } 1320 } 1321 1322 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1323 1324 if ( ftc != oftc ) { 1325 /* 1326 * Enable/disable the Tx FIFO threshold interrupt 1327 * according to how much data is in the FIFO. 1328 * However, always disable the FIFO threshold if 1329 * we've left the channel in 'Embedded Transmit 1330 * Command' mode. 1331 */ 1332 if ( etcmode || ftc >= ch->ch_cor4 ) 1333 tir &= ~CLMPCC_IER_TX_FIFO; 1334 else 1335 tir |= CLMPCC_IER_TX_FIFO; 1336 teoir = 0; 1337 } else { 1338 /* 1339 * No data was sent. 1340 * Disable transmit interrupt. 1341 */ 1342 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1343 teoir = CLMPCC_TEOIR_NO_TRANS; 1344 1345 /* 1346 * Request Tx processing in the soft interrupt handler 1347 */ 1348 ch->ch_tx_done = 1; 1349 softint_schedule(sc->sc_softintr_cookie); 1350 } 1351 1352 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1353 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1354 1355 return 1; 1356 } 1357 1358 /* 1359 * Modem change interrupt routine 1360 */ 1361 int 1362 clmpcc_mdintr(arg) 1363 void *arg; 1364 { 1365 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1366 u_char mir; 1367 1368 /* Modem status interrupt active? */ 1369 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1370 1371 /* 1372 * If we're using auto-vectored interrupts, we have to 1373 * verify if the chip is generating the interrupt. 1374 */ 1375 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1376 return 0; 1377 1378 /* Dummy read of the interrupt status register */ 1379 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1380 1381 /* Retrieve current status of modem lines. */ 1382 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1383 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1384 1385 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1386 softint_schedule(sc->sc_softintr_cookie); 1387 1388 return 1; 1389 } 1390 1391 void 1392 clmpcc_softintr(arg) 1393 void *arg; 1394 { 1395 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1396 struct clmpcc_chan *ch; 1397 struct tty *tp; 1398 int (*rint)(int, struct tty *); 1399 u_char *get; 1400 u_char reg; 1401 u_int c; 1402 int chan; 1403 1404 /* Handle Modem state changes too... */ 1405 1406 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1407 ch = &sc->sc_chans[chan]; 1408 tp = ch->ch_tty; 1409 1410 get = ch->ch_ibuf_rd; 1411 rint = tp->t_linesw->l_rint; 1412 1413 /* Squirt buffered incoming data into the tty layer */ 1414 while ( get != ch->ch_ibuf_wr ) { 1415 c = get[0]; 1416 c |= ((u_int)get[1]) << 8; 1417 if ( (rint)(c, tp) == -1 ) { 1418 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1419 break; 1420 } 1421 1422 get += 2; 1423 if ( get == ch->ch_ibuf_end ) 1424 get = ch->ch_ibuf; 1425 1426 ch->ch_ibuf_rd = get; 1427 } 1428 1429 /* 1430 * Is the transmitter idle and in need of attention? 1431 */ 1432 if ( ch->ch_tx_done ) { 1433 ch->ch_tx_done = 0; 1434 1435 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1436 clmpcc_channel_cmd(sc, ch->ch_car, 1437 CLMPCC_CCR_T0_INIT | 1438 CLMPCC_CCR_T0_RX_EN | 1439 CLMPCC_CCR_T0_TX_EN); 1440 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1441 1442 /* 1443 * Allow time for the channel to initialise. 1444 * (Empirically derived duration; there must 1445 * be another way to determine the command 1446 * has completed without busy-waiting...) 1447 */ 1448 delay(800); 1449 1450 /* 1451 * Update the tty layer's idea of the carrier 1452 * bit, in case we changed CLOCAL or MDMBUF. 1453 * We don't hang up here; we only do that by 1454 * explicit request. 1455 */ 1456 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1457 (*tp->t_linesw->l_modem)(tp, reg != 0); 1458 } 1459 1460 CLR(tp->t_state, TS_BUSY); 1461 if ( ISSET(tp->t_state, TS_FLUSH) ) 1462 CLR(tp->t_state, TS_FLUSH); 1463 else 1464 ndflush(&tp->t_outq, 1465 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1466 1467 (*tp->t_linesw->l_start)(tp); 1468 } 1469 } 1470 } 1471 1472 1473 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1474 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1475 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1476 /* 1477 * Following are all routines needed for a cd240x channel to act as console 1478 */ 1479 int 1480 clmpcc_cnattach(sc, chan, rate) 1481 struct clmpcc_softc *sc; 1482 int chan; 1483 int rate; 1484 { 1485 cons_sc = sc; 1486 cons_chan = chan; 1487 cons_rate = rate; 1488 1489 return (clmpcc_init(sc)); 1490 } 1491 1492 /* 1493 * The following functions are polled getc and putc routines, for console use. 1494 */ 1495 static int 1496 clmpcc_common_getc(sc, chan) 1497 struct clmpcc_softc *sc; 1498 int chan; 1499 { 1500 u_char old_chan; 1501 u_char old_ier; 1502 u_char ch, rir, risr; 1503 int s; 1504 1505 s = splhigh(); 1506 1507 /* Save the currently active channel */ 1508 old_chan = clmpcc_select_channel(sc, chan); 1509 1510 /* 1511 * We have to put the channel into RX interrupt mode before 1512 * trying to read the Rx data register. So save the previous 1513 * interrupt mode. 1514 */ 1515 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1516 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1517 1518 /* Loop until we get a character */ 1519 for (;;) { 1520 /* 1521 * The REN bit will be set in the Receive Interrupt Register 1522 * when the CD240x has a character to process. Remember, 1523 * the RACT bit won't be set until we generate an interrupt 1524 * acknowledge cycle via the MD front-end. 1525 */ 1526 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1527 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1528 continue; 1529 1530 /* Acknowledge the request */ 1531 if ( sc->sc_iackhook ) 1532 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1533 1534 /* 1535 * Determine if the interrupt is for the required channel 1536 * and if valid data is available. 1537 */ 1538 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1539 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1540 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1541 risr != 0 ) { 1542 /* Rx error, or BREAK */ 1543 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1544 CLMPCC_REOIR_NO_TRANS); 1545 } else { 1546 /* Dummy read of the FIFO count register */ 1547 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1548 1549 /* Fetch the received character */ 1550 ch = clmpcc_rd_rxdata(sc); 1551 1552 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1553 break; 1554 } 1555 } 1556 1557 /* Restore the original IER and CAR register contents */ 1558 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1559 clmpcc_select_channel(sc, old_chan); 1560 1561 splx(s); 1562 return ch; 1563 } 1564 1565 1566 static void 1567 clmpcc_common_putc(sc, chan, c) 1568 struct clmpcc_softc *sc; 1569 int chan; 1570 int c; 1571 { 1572 u_char old_chan; 1573 int s = splhigh(); 1574 1575 /* Save the currently active channel */ 1576 old_chan = clmpcc_select_channel(sc, chan); 1577 1578 /* 1579 * Since we can only access the Tx Data register from within 1580 * the interrupt handler, the easiest way to get console data 1581 * onto the wire is using one of the Special Transmit Character 1582 * registers. 1583 */ 1584 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1585 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1586 CLMPCC_STCR_SND_SPC); 1587 1588 /* Wait until the "Send Special Character" command is accepted */ 1589 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1590 ; 1591 1592 /* Restore the previous channel selected */ 1593 clmpcc_select_channel(sc, old_chan); 1594 1595 splx(s); 1596 } 1597 1598 int 1599 clmpcccngetc(dev) 1600 dev_t dev; 1601 { 1602 return clmpcc_common_getc(cons_sc, cons_chan); 1603 } 1604 1605 /* 1606 * Console kernel output character routine. 1607 */ 1608 void 1609 clmpcccnputc(dev, c) 1610 dev_t dev; 1611 int c; 1612 { 1613 if ( c == '\n' ) 1614 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1615 1616 clmpcc_common_putc(cons_sc, cons_chan, c); 1617 } 1618