1 /* $NetBSD: clmpcc.c,v 1.15 2001/01/14 23:50:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include "opt_ddb.h" 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/select.h> 50 #include <sys/tty.h> 51 #include <sys/proc.h> 52 #include <sys/user.h> 53 #include <sys/conf.h> 54 #include <sys/file.h> 55 #include <sys/uio.h> 56 #include <sys/kernel.h> 57 #include <sys/syslog.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 #include <machine/param.h> 64 65 #include <dev/ic/clmpccreg.h> 66 #include <dev/ic/clmpccvar.h> 67 #include <dev/cons.h> 68 69 70 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 71 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 72 #endif 73 74 75 static int clmpcc_init __P((struct clmpcc_softc *sc)); 76 static void clmpcc_shutdown __P((struct clmpcc_chan *)); 77 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t, 78 int *, int *)); 79 static int clmpcc_param __P((struct tty *, struct termios *)); 80 static void clmpcc_set_params __P((struct clmpcc_chan *)); 81 static void clmpcc_start __P((struct tty *)); 82 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int)); 83 84 85 cdev_decl(clmpcc); 86 87 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 88 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 89 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 90 91 /* 92 * These should be in a header file somewhere... 93 */ 94 #define ISSET(v, f) (((v) & (f)) != 0) 95 #define ISCLR(v, f) (((v) & (f)) == 0) 96 #define SET(v, f) (v) |= (f) 97 #define CLR(v, f) (v) &= ~(f) 98 99 100 extern struct cfdriver clmpcc_cd; 101 102 103 /* 104 * Make this an option variable one can patch. 105 */ 106 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 107 108 109 /* 110 * Things needed when the device is used as a console 111 */ 112 static struct clmpcc_softc *cons_sc = NULL; 113 static int cons_chan; 114 static int cons_rate; 115 116 static int clmpcc_common_getc __P((struct clmpcc_softc *, int)); 117 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int)); 118 int clmpcccngetc __P((dev_t)); 119 void clmpcccnputc __P((dev_t, int)); 120 121 122 /* 123 * Convenience functions, inlined for speed 124 */ 125 #define integrate static inline 126 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int)); 127 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int)); 128 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int)); 129 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int)); 130 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *, 131 u_int)); 132 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int)); 133 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int)); 134 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *)); 135 136 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 137 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 138 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 139 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 140 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 141 142 143 integrate u_int8_t 144 clmpcc_rdreg(sc, offset) 145 struct clmpcc_softc *sc; 146 u_int offset; 147 { 148 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 149 offset ^= sc->sc_byteswap; 150 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 151 offset ^= CLMPCC_BYTESWAP_HIGH; 152 #endif 153 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 154 } 155 156 integrate void 157 clmpcc_wrreg(sc, offset, val) 158 struct clmpcc_softc *sc; 159 u_int offset; 160 u_int val; 161 { 162 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 163 offset ^= sc->sc_byteswap; 164 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 165 offset ^= CLMPCC_BYTESWAP_HIGH; 166 #endif 167 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 168 } 169 170 integrate u_int8_t 171 clmpcc_rdreg_odd(sc, offset) 172 struct clmpcc_softc *sc; 173 u_int offset; 174 { 175 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 176 offset ^= (sc->sc_byteswap & 2); 177 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 178 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 179 #endif 180 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 181 } 182 183 integrate void 184 clmpcc_wrreg_odd(sc, offset, val) 185 struct clmpcc_softc *sc; 186 u_int offset; 187 u_int val; 188 { 189 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 190 offset ^= (sc->sc_byteswap & 2); 191 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 192 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 193 #endif 194 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 195 } 196 197 integrate void 198 clmpcc_wrtx_multi(sc, buff, count) 199 struct clmpcc_softc *sc; 200 u_int8_t *buff; 201 u_int count; 202 { 203 u_int offset = CLMPCC_REG_TDR; 204 205 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 206 offset ^= (sc->sc_byteswap & 2); 207 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 208 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 209 #endif 210 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 211 } 212 213 integrate u_int8_t 214 clmpcc_select_channel(sc, new_chan) 215 struct clmpcc_softc *sc; 216 u_int new_chan; 217 { 218 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 219 220 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 221 222 return old_chan; 223 } 224 225 integrate void 226 clmpcc_channel_cmd(sc, chan, cmd) 227 struct clmpcc_softc *sc; 228 int chan; 229 int cmd; 230 { 231 int i; 232 233 for (i = 5000; i; i--) { 234 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 235 break; 236 delay(1); 237 } 238 239 if ( i == 0 ) 240 printf("%s: channel %d command timeout (idle)\n", 241 sc->sc_dev.dv_xname, chan); 242 243 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 244 } 245 246 integrate void 247 clmpcc_enable_transmitter(ch) 248 struct clmpcc_chan *ch; 249 { 250 u_int old; 251 int s; 252 253 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 254 255 s = splserial(); 256 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 257 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 258 SET(ch->ch_tty->t_state, TS_BUSY); 259 splx(s); 260 261 clmpcc_select_channel(ch->ch_sc, old); 262 } 263 264 static int 265 clmpcc_speed(sc, speed, cor, bpr) 266 struct clmpcc_softc *sc; 267 speed_t speed; 268 int *cor, *bpr; 269 { 270 int c, co, br; 271 272 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 273 br = ((sc->sc_clk / c) / speed) - 1; 274 if ( br < 0x100 ) { 275 *cor = co; 276 *bpr = br; 277 return 0; 278 } 279 } 280 281 return -1; 282 } 283 284 void 285 clmpcc_attach(sc) 286 struct clmpcc_softc *sc; 287 { 288 struct clmpcc_chan *ch; 289 struct tty *tp; 290 int chan; 291 292 if ( cons_sc != NULL && 293 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 294 cons_sc = sc; 295 296 /* Initialise the chip */ 297 clmpcc_init(sc); 298 299 printf(": Cirrus Logic CD240%c Serial Controller\n", 300 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 301 302 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 303 sc->sc_soft_running = 0; 304 #else 305 sc->sc_softintr_cookie = 306 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc); 307 #ifdef DEBUG 308 if (sc->sc_softintr_cookie == NULL) 309 panic("clmpcc_attach: softintr_establish"); 310 #endif 311 #endif 312 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 313 314 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 315 ch = &sc->sc_chans[chan]; 316 317 ch->ch_sc = sc; 318 ch->ch_car = chan; 319 320 tp = ttymalloc(); 321 tp->t_oproc = clmpcc_start; 322 tp->t_param = clmpcc_param; 323 324 ch->ch_tty = tp; 325 326 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 327 if ( ch->ch_ibuf == NULL ) { 328 printf("%s(%d): unable to allocate ring buffer\n", 329 sc->sc_dev.dv_xname, chan); 330 return; 331 } 332 333 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 334 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 335 336 tty_attach(tp); 337 } 338 339 printf("%s: %d channels available", sc->sc_dev.dv_xname, 340 CLMPCC_NUM_CHANS); 341 if ( cons_sc == sc ) { 342 printf(", console on channel %d.\n", cons_chan); 343 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 344 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 345 } else 346 printf(".\n"); 347 } 348 349 static int 350 clmpcc_init(sc) 351 struct clmpcc_softc *sc; 352 { 353 u_int tcor, tbpr; 354 u_int rcor, rbpr; 355 u_int msvr_rts, msvr_dtr; 356 u_int ccr; 357 int is_console; 358 int i; 359 360 /* 361 * All we're really concerned about here is putting the chip 362 * into a quiescent state so that it won't do anything until 363 * clmpccopen() is called. (Except the console channel.) 364 */ 365 366 /* 367 * If the chip is acting as console, set all channels to the supplied 368 * console baud rate. Otherwise, plump for 9600. 369 */ 370 if ( cons_sc && 371 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 372 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 373 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 374 is_console = 1; 375 } else { 376 clmpcc_speed(sc, 9600, &tcor, &tbpr); 377 clmpcc_speed(sc, 9600, &rcor, &rbpr); 378 is_console = 0; 379 } 380 381 /* Allow any pending output to be sent */ 382 delay(10000); 383 384 /* Send the Reset All command to channel 0 (resets all channels!) */ 385 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 386 387 delay(1000); 388 389 /* 390 * The chip will set it's firmware revision register to a non-zero 391 * value to indicate completion of reset. 392 */ 393 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 394 delay(1); 395 396 if ( i == 0 ) { 397 /* 398 * Watch out... If this chip is console, the message 399 * probably won't be sent since we just reset it! 400 */ 401 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 402 return -1; 403 } 404 405 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 406 clmpcc_select_channel(sc, i); 407 408 /* All interrupts are disabled to begin with */ 409 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 410 411 /* Make sure the channel interrupts on the correct vectors */ 412 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 413 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 414 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 415 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 416 417 /* Receive timer prescaler set to 1ms */ 418 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 419 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 420 421 /* We support Async mode only */ 422 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 423 424 /* Set the required baud rate */ 425 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 426 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 427 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 428 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 429 430 /* Always default to 8N1 (XXX what about console?) */ 431 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 432 CLMPCC_COR1_NO_PARITY | 433 CLMPCC_COR1_IGNORE_PAR); 434 435 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 436 437 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 438 439 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 440 CLMPCC_COR4_CDzd | 441 CLMPCC_COR4_CTSzd); 442 443 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 444 CLMPCC_COR5_CDod | 445 CLMPCC_COR5_CTSod | 446 CLMPCC_COR5_FLOW_NORM); 447 448 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 449 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 450 451 /* Set the receive FIFO timeout */ 452 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 453 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 454 455 /* At this point, we set up the console differently */ 456 if ( is_console && i == cons_chan ) { 457 msvr_rts = CLMPCC_MSVR_RTS; 458 msvr_dtr = CLMPCC_MSVR_DTR; 459 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 460 } else { 461 msvr_rts = 0; 462 msvr_dtr = 0; 463 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 464 } 465 466 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 467 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 468 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 469 delay(100); 470 } 471 472 return 0; 473 } 474 475 static void 476 clmpcc_shutdown(ch) 477 struct clmpcc_chan *ch; 478 { 479 int oldch; 480 481 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 482 483 /* Turn off interrupts. */ 484 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 485 486 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 487 /* Disable the transmitter and receiver */ 488 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 489 CLMPCC_CCR_T0_TX_DIS); 490 491 /* Drop RTS and DTR */ 492 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 493 } 494 495 clmpcc_select_channel(ch->ch_sc, oldch); 496 } 497 498 int 499 clmpccopen(dev, flag, mode, p) 500 dev_t dev; 501 int flag, mode; 502 struct proc *p; 503 { 504 struct clmpcc_softc *sc; 505 struct clmpcc_chan *ch; 506 struct tty *tp; 507 int oldch; 508 int error; 509 510 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 511 if (sc == NULL) 512 return (ENXIO); 513 514 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 515 516 tp = ch->ch_tty; 517 518 if ( ISSET(tp->t_state, TS_ISOPEN) && 519 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 520 return EBUSY; 521 522 /* 523 * Do the following iff this is a first open. 524 */ 525 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 526 527 ttychars(tp); 528 529 tp->t_dev = dev; 530 tp->t_iflag = TTYDEF_IFLAG; 531 tp->t_oflag = TTYDEF_OFLAG; 532 tp->t_lflag = TTYDEF_LFLAG; 533 tp->t_cflag = TTYDEF_CFLAG; 534 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 535 536 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 537 SET(tp->t_cflag, CLOCAL); 538 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 539 SET(tp->t_cflag, CRTSCTS); 540 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 541 SET(tp->t_cflag, MDMBUF); 542 543 /* 544 * Override some settings if the channel is being 545 * used as the console. 546 */ 547 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 548 tp->t_ospeed = tp->t_ispeed = cons_rate; 549 SET(tp->t_cflag, CLOCAL); 550 CLR(tp->t_cflag, CRTSCTS); 551 CLR(tp->t_cflag, HUPCL); 552 } 553 554 ch->ch_control = 0; 555 556 clmpcc_param(tp, &tp->t_termios); 557 ttsetwater(tp); 558 559 /* Clear the input ring */ 560 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 561 562 /* Select the channel */ 563 oldch = clmpcc_select_channel(sc, ch->ch_car); 564 565 /* Reset it */ 566 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 567 CLMPCC_CCR_T0_RX_EN | 568 CLMPCC_CCR_T0_TX_EN); 569 570 /* Enable receiver and modem change interrupts. */ 571 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 572 CLMPCC_IER_RET | 573 CLMPCC_IER_RX_FIFO); 574 575 /* Raise RTS and DTR */ 576 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 577 578 clmpcc_select_channel(sc, oldch); 579 } else 580 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 581 return EBUSY; 582 583 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 584 if (error) 585 goto bad; 586 587 error = (*tp->t_linesw->l_open)(dev, tp); 588 if (error) 589 goto bad; 590 591 return 0; 592 593 bad: 594 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 595 /* 596 * We failed to open the device, and nobody else had it opened. 597 * Clean up the state as appropriate. 598 */ 599 clmpcc_shutdown(ch); 600 } 601 602 return error; 603 } 604 605 int 606 clmpccclose(dev, flag, mode, p) 607 dev_t dev; 608 int flag, mode; 609 struct proc *p; 610 { 611 struct clmpcc_softc *sc = 612 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 613 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 614 struct tty *tp = ch->ch_tty; 615 int s; 616 617 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 618 return 0; 619 620 (*tp->t_linesw->l_close)(tp, flag); 621 622 s = spltty(); 623 624 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 625 /* 626 * Although we got a last close, the device may still be in 627 * use; e.g. if this was the dialout node, and there are still 628 * processes waiting for carrier on the non-dialout node. 629 */ 630 clmpcc_shutdown(ch); 631 } 632 633 ttyclose(tp); 634 635 splx(s); 636 637 return 0; 638 } 639 640 int 641 clmpccread(dev, uio, flag) 642 dev_t dev; 643 struct uio *uio; 644 int flag; 645 { 646 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 647 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 648 649 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 650 } 651 652 int 653 clmpccwrite(dev, uio, flag) 654 dev_t dev; 655 struct uio *uio; 656 int flag; 657 { 658 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 659 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 660 661 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 662 } 663 664 struct tty * 665 clmpcctty(dev) 666 dev_t dev; 667 { 668 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 669 670 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 671 } 672 673 int 674 clmpccioctl(dev, cmd, data, flag, p) 675 dev_t dev; 676 u_long cmd; 677 caddr_t data; 678 int flag; 679 struct proc *p; 680 { 681 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 682 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 683 struct tty *tp = ch->ch_tty; 684 int error; 685 686 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 687 if (error >= 0) 688 return error; 689 690 error = ttioctl(tp, cmd, data, flag, p); 691 if (error >= 0) 692 return error; 693 694 error = 0; 695 696 switch (cmd) { 697 case TIOCSBRK: 698 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 699 clmpcc_enable_transmitter(ch); 700 break; 701 702 case TIOCCBRK: 703 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 704 clmpcc_enable_transmitter(ch); 705 break; 706 707 case TIOCSDTR: 708 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 709 break; 710 711 case TIOCCDTR: 712 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 713 break; 714 715 case TIOCMSET: 716 clmpcc_modem_control(ch, *((int *)data), DMSET); 717 break; 718 719 case TIOCMBIS: 720 clmpcc_modem_control(ch, *((int *)data), DMBIS); 721 break; 722 723 case TIOCMBIC: 724 clmpcc_modem_control(ch, *((int *)data), DMBIC); 725 break; 726 727 case TIOCMGET: 728 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 729 break; 730 731 case TIOCGFLAGS: 732 *((int *)data) = ch->ch_openflags; 733 break; 734 735 case TIOCSFLAGS: 736 error = suser(p->p_ucred, &p->p_acflag); 737 if ( error ) 738 break; 739 ch->ch_openflags = *((int *)data) & 740 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 741 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 742 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 743 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 744 break; 745 746 default: 747 error = ENOTTY; 748 break; 749 } 750 751 return error; 752 } 753 754 int 755 clmpcc_modem_control(ch, bits, howto) 756 struct clmpcc_chan *ch; 757 int bits; 758 int howto; 759 { 760 struct clmpcc_softc *sc = ch->ch_sc; 761 struct tty *tp = ch->ch_tty; 762 int oldch; 763 int msvr; 764 int rbits = 0; 765 766 oldch = clmpcc_select_channel(sc, ch->ch_car); 767 768 switch ( howto ) { 769 case DMGET: 770 msvr = clmpcc_rd_msvr(sc); 771 772 if ( sc->sc_swaprtsdtr ) { 773 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 774 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 775 } else { 776 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 777 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 778 } 779 780 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 781 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 782 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 783 break; 784 785 case DMSET: 786 if ( sc->sc_swaprtsdtr ) { 787 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 788 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 789 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 790 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 791 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 792 } else { 793 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 794 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 795 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 796 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 797 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 798 } 799 break; 800 801 case DMBIS: 802 if ( sc->sc_swaprtsdtr ) { 803 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 804 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 805 if ( ISSET(bits, TIOCM_DTR) ) 806 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 807 } else { 808 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 809 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 810 if ( ISSET(bits, TIOCM_DTR) ) 811 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 812 } 813 break; 814 815 case DMBIC: 816 if ( sc->sc_swaprtsdtr ) { 817 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 818 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 819 if ( ISCLR(bits, TIOCM_DTR) ) 820 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 821 } else { 822 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 823 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 824 if ( ISCLR(bits, TIOCM_DTR) ) 825 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 826 } 827 break; 828 } 829 830 clmpcc_select_channel(sc, oldch); 831 832 return rbits; 833 } 834 835 static int 836 clmpcc_param(tp, t) 837 struct tty *tp; 838 struct termios *t; 839 { 840 struct clmpcc_softc *sc = 841 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 842 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 843 u_char cor; 844 u_char oldch; 845 int oclk, obpr; 846 int iclk, ibpr; 847 int s; 848 849 /* Check requested parameters. */ 850 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 851 return EINVAL; 852 853 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 854 return EINVAL; 855 856 /* 857 * For the console, always force CLOCAL and !HUPCL, so that the port 858 * is always active. 859 */ 860 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 861 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 862 SET(t->c_cflag, CLOCAL); 863 CLR(t->c_cflag, HUPCL); 864 } 865 866 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 867 868 /* If ospeed it zero, hangup the line */ 869 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 870 871 if ( t->c_ospeed ) { 872 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 873 ch->ch_tbpr = obpr; 874 } else { 875 ch->ch_tcor = 0; 876 ch->ch_tbpr = 0; 877 } 878 879 if ( t->c_ispeed ) { 880 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 881 ch->ch_rbpr = ibpr; 882 } else { 883 ch->ch_rcor = 0; 884 ch->ch_rbpr = 0; 885 } 886 887 /* Work out value to use for COR1 */ 888 cor = 0; 889 if ( ISSET(t->c_cflag, PARENB) ) { 890 cor |= CLMPCC_COR1_NORM_PARITY; 891 if ( ISSET(t->c_cflag, PARODD) ) 892 cor |= CLMPCC_COR1_ODD_PARITY; 893 } 894 895 if ( ISCLR(t->c_cflag, INPCK) ) 896 cor |= CLMPCC_COR1_IGNORE_PAR; 897 898 switch ( t->c_cflag & CSIZE ) { 899 case CS5: 900 cor |= CLMPCC_COR1_CHAR_5BITS; 901 break; 902 903 case CS6: 904 cor |= CLMPCC_COR1_CHAR_6BITS; 905 break; 906 907 case CS7: 908 cor |= CLMPCC_COR1_CHAR_7BITS; 909 break; 910 911 case CS8: 912 cor |= CLMPCC_COR1_CHAR_8BITS; 913 break; 914 } 915 916 ch->ch_cor1 = cor; 917 918 /* 919 * The only interesting bit in COR2 is 'CTS Automatic Enable' 920 * when hardware flow control is in effect. 921 */ 922 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 923 924 /* COR3 needs to be set to the number of stop bits... */ 925 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 926 CLMPCC_COR3_STOP_1; 927 928 /* 929 * COR4 contains the FIFO threshold setting. 930 * We adjust the threshold depending on the input speed... 931 */ 932 if ( t->c_ispeed <= 1200 ) 933 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 934 else if ( t->c_ispeed <= 19200 ) 935 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 936 else 937 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 938 939 /* 940 * If chip is used with CTS and DTR swapped, we can enable 941 * automatic hardware flow control. 942 */ 943 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 944 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 945 else 946 ch->ch_cor5 = 0; 947 948 s = splserial(); 949 oldch = clmpcc_select_channel(sc, ch->ch_car); 950 951 /* 952 * COR2 needs to be set immediately otherwise we might never get 953 * a Tx EMPTY interrupt to change the other parameters. 954 */ 955 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 956 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 957 958 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 959 clmpcc_set_params(ch); 960 else 961 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 962 963 clmpcc_select_channel(sc, oldch); 964 965 splx(s); 966 967 return 0; 968 } 969 970 static void 971 clmpcc_set_params(ch) 972 struct clmpcc_chan *ch; 973 { 974 struct clmpcc_softc *sc = ch->ch_sc; 975 u_char r1; 976 u_char r2; 977 978 if ( ch->ch_tcor || ch->ch_tbpr ) { 979 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 980 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 981 /* Only write Tx rate if it really has changed */ 982 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 983 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 984 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 985 } 986 } 987 988 if ( ch->ch_rcor || ch->ch_rbpr ) { 989 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 990 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 991 /* Only write Rx rate if it really has changed */ 992 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 993 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 994 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 995 } 996 } 997 998 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 999 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1000 /* Any change to COR1 requires an INIT command */ 1001 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1002 } 1003 1004 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1005 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1006 1007 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1008 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1009 /* 1010 * Note: If the FIFO has changed, we always set it to 1011 * zero here and disable the Receive Timeout interrupt. 1012 * It's up to the Rx Interrupt handler to pick the 1013 * appropriate moment to write the new FIFO length. 1014 */ 1015 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1016 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1017 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1018 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1019 } 1020 1021 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1022 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1023 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1024 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1025 } 1026 } 1027 1028 static void 1029 clmpcc_start(tp) 1030 struct tty *tp; 1031 { 1032 struct clmpcc_softc *sc = 1033 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1034 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1035 u_int oldch; 1036 int s; 1037 1038 s = spltty(); 1039 1040 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1041 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1042 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1043 CLR(tp->t_state, TS_ASLEEP); 1044 wakeup(&tp->t_outq); 1045 } 1046 selwakeup(&tp->t_wsel); 1047 } 1048 1049 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1050 CLMPCC_FLG_END_BREAK) || 1051 tp->t_outq.c_cc > 0 ) { 1052 1053 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1054 CLMPCC_FLG_END_BREAK) ) { 1055 ch->ch_obuf_addr = tp->t_outq.c_cf; 1056 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1057 } 1058 1059 /* Enable TX empty interrupts */ 1060 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1061 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1062 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1063 CLMPCC_IER_TX_EMPTY); 1064 clmpcc_select_channel(ch->ch_sc, oldch); 1065 SET(tp->t_state, TS_BUSY); 1066 } 1067 } 1068 1069 splx(s); 1070 } 1071 1072 /* 1073 * Stop output on a line. 1074 */ 1075 void 1076 clmpccstop(tp, flag) 1077 struct tty *tp; 1078 int flag; 1079 { 1080 struct clmpcc_softc *sc = 1081 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1082 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1083 int s; 1084 1085 s = splserial(); 1086 1087 if ( ISSET(tp->t_state, TS_BUSY) ) { 1088 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1089 SET(tp->t_state, TS_FLUSH); 1090 ch->ch_obuf_size = 0; 1091 } 1092 splx(s); 1093 } 1094 1095 /* 1096 * RX interrupt routine 1097 */ 1098 int 1099 clmpcc_rxintr(arg) 1100 void *arg; 1101 { 1102 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1103 struct clmpcc_chan *ch; 1104 u_int8_t *put, *end, rxd; 1105 u_char errstat; 1106 u_char fc, tc; 1107 u_char risr; 1108 u_char rir; 1109 #ifdef DDB 1110 int saw_break = 0; 1111 #endif 1112 1113 /* Receive interrupt active? */ 1114 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1115 1116 /* 1117 * If we're using auto-vectored interrupts, we have to 1118 * verify if the chip is generating the interrupt. 1119 */ 1120 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1121 return 0; 1122 1123 /* Get pointer to interrupting channel's data structure */ 1124 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1125 1126 /* Get the interrupt status register */ 1127 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1128 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1129 u_char reg; 1130 /* 1131 * Set the FIFO threshold to zero, and disable 1132 * further receive timeout interrupts. 1133 */ 1134 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1135 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1136 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1137 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1138 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1139 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1140 return 1; 1141 } 1142 1143 /* How many bytes are waiting in the FIFO? */ 1144 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1145 1146 #ifdef DDB 1147 /* 1148 * Allow BREAK on the console to drop to the debugger. 1149 */ 1150 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1151 risr & CLMPCC_RISR_BREAK ) { 1152 saw_break = 1; 1153 } 1154 #endif 1155 1156 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1157 /* Just get rid of the data */ 1158 while ( fc-- ) 1159 (void) clmpcc_rd_rxdata(sc); 1160 goto rx_done; 1161 } 1162 1163 put = ch->ch_ibuf_wr; 1164 end = ch->ch_ibuf_end; 1165 1166 /* 1167 * Note: The chip is completely hosed WRT these error 1168 * conditions; there seems to be no way to associate 1169 * the error with the correct character in the FIFO. 1170 * We compromise by tagging the first character we read 1171 * with the error. Not perfect, but there's no other way. 1172 */ 1173 errstat = 0; 1174 if ( risr & CLMPCC_RISR_PARITY ) 1175 errstat |= TTY_PE; 1176 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1177 errstat |= TTY_FE; 1178 1179 /* 1180 * As long as there are characters in the FIFO, and we 1181 * have space for them... 1182 */ 1183 while ( fc > 0 ) { 1184 1185 *put++ = rxd = clmpcc_rd_rxdata(sc); 1186 *put++ = errstat; 1187 1188 if ( put >= end ) 1189 put = ch->ch_ibuf; 1190 1191 if ( put == ch->ch_ibuf_rd ) { 1192 put -= 2; 1193 if ( put < ch->ch_ibuf ) 1194 put = end - 2; 1195 } 1196 1197 errstat = 0; 1198 fc--; 1199 } 1200 1201 ch->ch_ibuf_wr = put; 1202 1203 #if 0 1204 if ( sc->sc_swaprtsdtr == 0 && 1205 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1206 /* 1207 * If RTS/DTR are not physically swapped, we have to 1208 * do hardware flow control manually 1209 */ 1210 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1211 } 1212 #endif 1213 1214 rx_done: 1215 if ( fc != tc ) { 1216 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1217 u_char reg; 1218 /* 1219 * Set the FIFO threshold to the preset value, 1220 * and enable receive timeout interrupts. 1221 */ 1222 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1223 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1224 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1225 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1226 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1227 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1228 } 1229 1230 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1231 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1232 if ( sc->sc_soft_running == 0 ) { 1233 sc->sc_soft_running = 1; 1234 (sc->sc_softhook)(sc); 1235 } 1236 #else 1237 softintr_schedule(sc->sc_softintr_cookie); 1238 #endif 1239 } else 1240 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1241 1242 #ifdef DDB 1243 /* 1244 * Only =after= we write REOIR is it safe to drop to the debugger. 1245 */ 1246 if ( saw_break ) 1247 Debugger(); 1248 #endif 1249 1250 return 1; 1251 } 1252 1253 /* 1254 * Tx interrupt routine 1255 */ 1256 int 1257 clmpcc_txintr(arg) 1258 void *arg; 1259 { 1260 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1261 struct clmpcc_chan *ch; 1262 struct tty *tp; 1263 u_char ftc, oftc; 1264 u_char tir, teoir; 1265 int etcmode = 0; 1266 1267 /* Tx interrupt active? */ 1268 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1269 1270 /* 1271 * If we're using auto-vectored interrupts, we have to 1272 * verify if the chip is generating the interrupt. 1273 */ 1274 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1275 return 0; 1276 1277 /* Get pointer to interrupting channel's data structure */ 1278 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1279 tp = ch->ch_tty; 1280 1281 /* Dummy read of the interrupt status register */ 1282 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1283 1284 /* Make sure embedded transmit commands are disabled */ 1285 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1286 1287 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1288 1289 /* Handle a delayed parameter change */ 1290 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1291 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1292 clmpcc_set_params(ch); 1293 } 1294 1295 if ( ch->ch_obuf_size > 0 ) { 1296 u_int n = min(ch->ch_obuf_size, ftc); 1297 1298 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1299 1300 ftc -= n; 1301 ch->ch_obuf_size -= n; 1302 ch->ch_obuf_addr += n; 1303 1304 } else { 1305 /* 1306 * Check if we should start/stop a break 1307 */ 1308 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1309 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1310 /* Enable embedded transmit commands */ 1311 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1312 ch->ch_cor2 | CLMPCC_COR2_ETC); 1313 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1314 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1315 ftc -= 2; 1316 etcmode = 1; 1317 } 1318 1319 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1320 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1321 /* Enable embedded transmit commands */ 1322 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1323 ch->ch_cor2 | CLMPCC_COR2_ETC); 1324 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1325 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1326 ftc -= 2; 1327 etcmode = 1; 1328 } 1329 } 1330 1331 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1332 1333 if ( ftc != oftc ) { 1334 /* 1335 * Enable/disable the Tx FIFO threshold interrupt 1336 * according to how much data is in the FIFO. 1337 * However, always disable the FIFO threshold if 1338 * we've left the channel in 'Embedded Transmit 1339 * Command' mode. 1340 */ 1341 if ( etcmode || ftc >= ch->ch_cor4 ) 1342 tir &= ~CLMPCC_IER_TX_FIFO; 1343 else 1344 tir |= CLMPCC_IER_TX_FIFO; 1345 teoir = 0; 1346 } else { 1347 /* 1348 * No data was sent. 1349 * Disable transmit interrupt. 1350 */ 1351 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1352 teoir = CLMPCC_TEOIR_NO_TRANS; 1353 1354 /* 1355 * Request Tx processing in the soft interrupt handler 1356 */ 1357 ch->ch_tx_done = 1; 1358 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1359 if ( sc->sc_soft_running == 0 ) { 1360 sc->sc_soft_running = 1; 1361 (sc->sc_softhook)(sc); 1362 } 1363 #else 1364 softintr_schedule(sc->sc_softintr_cookie); 1365 #endif 1366 } 1367 1368 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1369 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1370 1371 return 1; 1372 } 1373 1374 /* 1375 * Modem change interrupt routine 1376 */ 1377 int 1378 clmpcc_mdintr(arg) 1379 void *arg; 1380 { 1381 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1382 u_char mir; 1383 1384 /* Modem status interrupt active? */ 1385 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1386 1387 /* 1388 * If we're using auto-vectored interrupts, we have to 1389 * verify if the chip is generating the interrupt. 1390 */ 1391 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1392 return 0; 1393 1394 /* Dummy read of the interrupt status register */ 1395 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1396 1397 /* Retrieve current status of modem lines. */ 1398 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1399 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1400 1401 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1402 1403 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1404 if ( sc->sc_soft_running == 0 ) { 1405 sc->sc_soft_running = 1; 1406 (sc->sc_softhook)(sc); 1407 } 1408 #else 1409 softintr_schedule(sc->sc_softintr_cookie); 1410 #endif 1411 1412 return 1; 1413 } 1414 1415 void 1416 clmpcc_softintr(arg) 1417 void *arg; 1418 { 1419 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1420 struct clmpcc_chan *ch; 1421 struct tty *tp; 1422 int (*rint) __P((int, struct tty *)); 1423 u_char *get; 1424 u_char reg; 1425 u_int c; 1426 int chan; 1427 1428 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1429 sc->sc_soft_running = 0; 1430 #endif 1431 1432 /* Handle Modem state changes too... */ 1433 1434 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1435 ch = &sc->sc_chans[chan]; 1436 tp = ch->ch_tty; 1437 1438 get = ch->ch_ibuf_rd; 1439 rint = tp->t_linesw->l_rint; 1440 1441 /* Squirt buffered incoming data into the tty layer */ 1442 while ( get != ch->ch_ibuf_wr ) { 1443 c = get[0]; 1444 c |= ((u_int)get[1]) << 8; 1445 if ( (rint)(c, tp) == -1 ) { 1446 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1447 break; 1448 } 1449 1450 get += 2; 1451 if ( get == ch->ch_ibuf_end ) 1452 get = ch->ch_ibuf; 1453 1454 ch->ch_ibuf_rd = get; 1455 } 1456 1457 /* 1458 * Is the transmitter idle and in need of attention? 1459 */ 1460 if ( ch->ch_tx_done ) { 1461 ch->ch_tx_done = 0; 1462 1463 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1464 clmpcc_channel_cmd(sc, ch->ch_car, 1465 CLMPCC_CCR_T0_INIT | 1466 CLMPCC_CCR_T0_RX_EN | 1467 CLMPCC_CCR_T0_TX_EN); 1468 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1469 1470 /* 1471 * Allow time for the channel to initialise. 1472 * (Empirically derived duration; there must 1473 * be another way to determine the command 1474 * has completed without busy-waiting...) 1475 */ 1476 delay(800); 1477 1478 /* 1479 * Update the tty layer's idea of the carrier 1480 * bit, in case we changed CLOCAL or MDMBUF. 1481 * We don't hang up here; we only do that by 1482 * explicit request. 1483 */ 1484 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1485 (*tp->t_linesw->l_modem)(tp, reg != 0); 1486 } 1487 1488 CLR(tp->t_state, TS_BUSY); 1489 if ( ISSET(tp->t_state, TS_FLUSH) ) 1490 CLR(tp->t_state, TS_FLUSH); 1491 else 1492 ndflush(&tp->t_outq, 1493 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1494 1495 (*tp->t_linesw->l_start)(tp); 1496 } 1497 } 1498 } 1499 1500 1501 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1502 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1503 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1504 /* 1505 * Following are all routines needed for a cd240x channel to act as console 1506 */ 1507 int 1508 clmpcc_cnattach(sc, chan, rate) 1509 struct clmpcc_softc *sc; 1510 int chan; 1511 int rate; 1512 { 1513 cons_sc = sc; 1514 cons_chan = chan; 1515 cons_rate = rate; 1516 1517 return 0; 1518 } 1519 1520 /* 1521 * The following functions are polled getc and putc routines, for console use. 1522 */ 1523 static int 1524 clmpcc_common_getc(sc, chan) 1525 struct clmpcc_softc *sc; 1526 int chan; 1527 { 1528 u_char old_chan; 1529 u_char old_ier; 1530 u_char ch, rir, risr; 1531 int s; 1532 1533 s = splhigh(); 1534 1535 /* Save the currently active channel */ 1536 old_chan = clmpcc_select_channel(sc, chan); 1537 1538 /* 1539 * We have to put the channel into RX interrupt mode before 1540 * trying to read the Rx data register. So save the previous 1541 * interrupt mode. 1542 */ 1543 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1544 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1545 1546 /* Loop until we get a character */ 1547 for (;;) { 1548 /* 1549 * The REN bit will be set in the Receive Interrupt Register 1550 * when the CD240x has a character to process. Remember, 1551 * the RACT bit won't be set until we generate an interrupt 1552 * acknowledge cycle via the MD front-end. 1553 */ 1554 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1555 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1556 continue; 1557 1558 /* Acknowledge the request */ 1559 if ( sc->sc_iackhook ) 1560 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1561 1562 /* 1563 * Determine if the interrupt is for the required channel 1564 * and if valid data is available. 1565 */ 1566 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1567 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1568 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1569 risr != 0 ) { 1570 /* Rx error, or BREAK */ 1571 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1572 CLMPCC_REOIR_NO_TRANS); 1573 } else { 1574 /* Dummy read of the FIFO count register */ 1575 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1576 1577 /* Fetch the received character */ 1578 ch = clmpcc_rd_rxdata(sc); 1579 1580 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1581 break; 1582 } 1583 } 1584 1585 /* Restore the original IER and CAR register contents */ 1586 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1587 clmpcc_select_channel(sc, old_chan); 1588 1589 splx(s); 1590 return ch; 1591 } 1592 1593 1594 static void 1595 clmpcc_common_putc(sc, chan, c) 1596 struct clmpcc_softc *sc; 1597 int chan; 1598 int c; 1599 { 1600 u_char old_chan; 1601 int s = splhigh(); 1602 1603 /* Save the currently active channel */ 1604 old_chan = clmpcc_select_channel(sc, chan); 1605 1606 /* 1607 * Since we can only access the Tx Data register from within 1608 * the interrupt handler, the easiest way to get console data 1609 * onto the wire is using one of the Special Transmit Character 1610 * registers. 1611 */ 1612 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1613 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1614 CLMPCC_STCR_SND_SPC); 1615 1616 /* Wait until the "Send Special Character" command is accepted */ 1617 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1618 ; 1619 1620 /* Restore the previous channel selected */ 1621 clmpcc_select_channel(sc, old_chan); 1622 1623 splx(s); 1624 } 1625 1626 int 1627 clmpcccngetc(dev) 1628 dev_t dev; 1629 { 1630 return clmpcc_common_getc(cons_sc, cons_chan); 1631 } 1632 1633 /* 1634 * Console kernel output character routine. 1635 */ 1636 void 1637 clmpcccnputc(dev, c) 1638 dev_t dev; 1639 int c; 1640 { 1641 if ( c == '\n' ) 1642 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1643 1644 clmpcc_common_putc(cons_sc, cons_chan, c); 1645 } 1646