1 /* $NetBSD: clmpcc.c,v 1.26 2005/12/11 12:21:26 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.26 2005/12/11 12:21:26 christos Exp $"); 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/ioctl.h> 51 #include <sys/select.h> 52 #include <sys/tty.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/conf.h> 56 #include <sys/file.h> 57 #include <sys/uio.h> 58 #include <sys/kernel.h> 59 #include <sys/syslog.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 #include <machine/param.h> 66 67 #include <dev/ic/clmpccreg.h> 68 #include <dev/ic/clmpccvar.h> 69 #include <dev/cons.h> 70 71 72 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 73 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 74 #endif 75 76 77 static int clmpcc_init(struct clmpcc_softc *sc); 78 static void clmpcc_shutdown(struct clmpcc_chan *); 79 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *); 80 static int clmpcc_param(struct tty *, struct termios *); 81 static void clmpcc_set_params(struct clmpcc_chan *); 82 static void clmpcc_start(struct tty *); 83 static int clmpcc_modem_control(struct clmpcc_chan *, int, int); 84 85 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 86 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 87 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 88 89 /* 90 * These should be in a header file somewhere... 91 */ 92 #define ISSET(v, f) (((v) & (f)) != 0) 93 #define ISCLR(v, f) (((v) & (f)) == 0) 94 #define SET(v, f) (v) |= (f) 95 #define CLR(v, f) (v) &= ~(f) 96 97 98 extern struct cfdriver clmpcc_cd; 99 100 dev_type_open(clmpccopen); 101 dev_type_close(clmpccclose); 102 dev_type_read(clmpccread); 103 dev_type_write(clmpccwrite); 104 dev_type_ioctl(clmpccioctl); 105 dev_type_stop(clmpccstop); 106 dev_type_tty(clmpcctty); 107 dev_type_poll(clmpccpoll); 108 109 const struct cdevsw clmpcc_cdevsw = { 110 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl, 111 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY 112 }; 113 114 /* 115 * Make this an option variable one can patch. 116 */ 117 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 118 119 120 /* 121 * Things needed when the device is used as a console 122 */ 123 static struct clmpcc_softc *cons_sc = NULL; 124 static int cons_chan; 125 static int cons_rate; 126 127 static int clmpcc_common_getc(struct clmpcc_softc *, int); 128 static void clmpcc_common_putc(struct clmpcc_softc *, int, int); 129 int clmpcccngetc(dev_t); 130 void clmpcccnputc(dev_t, int); 131 132 133 /* 134 * Convenience functions, inlined for speed 135 */ 136 #define integrate static inline 137 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int); 138 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int); 139 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int); 140 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int); 141 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *, 142 u_int); 143 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int); 144 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int); 145 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *); 146 147 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 148 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 149 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 150 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 151 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 152 153 154 integrate u_int8_t 155 clmpcc_rdreg(sc, offset) 156 struct clmpcc_softc *sc; 157 u_int offset; 158 { 159 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 160 offset ^= sc->sc_byteswap; 161 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 162 offset ^= CLMPCC_BYTESWAP_HIGH; 163 #endif 164 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 165 } 166 167 integrate void 168 clmpcc_wrreg(sc, offset, val) 169 struct clmpcc_softc *sc; 170 u_int offset; 171 u_int val; 172 { 173 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 174 offset ^= sc->sc_byteswap; 175 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 176 offset ^= CLMPCC_BYTESWAP_HIGH; 177 #endif 178 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 179 } 180 181 integrate u_int8_t 182 clmpcc_rdreg_odd(sc, offset) 183 struct clmpcc_softc *sc; 184 u_int offset; 185 { 186 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 187 offset ^= (sc->sc_byteswap & 2); 188 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 189 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 190 #endif 191 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 192 } 193 194 integrate void 195 clmpcc_wrreg_odd(sc, offset, val) 196 struct clmpcc_softc *sc; 197 u_int offset; 198 u_int val; 199 { 200 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 201 offset ^= (sc->sc_byteswap & 2); 202 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 203 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 204 #endif 205 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 206 } 207 208 integrate void 209 clmpcc_wrtx_multi(sc, buff, count) 210 struct clmpcc_softc *sc; 211 u_int8_t *buff; 212 u_int count; 213 { 214 u_int offset = CLMPCC_REG_TDR; 215 216 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 217 offset ^= (sc->sc_byteswap & 2); 218 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 219 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 220 #endif 221 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 222 } 223 224 integrate u_int8_t 225 clmpcc_select_channel(sc, new_chan) 226 struct clmpcc_softc *sc; 227 u_int new_chan; 228 { 229 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 230 231 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 232 233 return old_chan; 234 } 235 236 integrate void 237 clmpcc_channel_cmd(sc, chan, cmd) 238 struct clmpcc_softc *sc; 239 int chan; 240 int cmd; 241 { 242 int i; 243 244 for (i = 5000; i; i--) { 245 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 246 break; 247 delay(1); 248 } 249 250 if ( i == 0 ) 251 printf("%s: channel %d command timeout (idle)\n", 252 sc->sc_dev.dv_xname, chan); 253 254 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 255 } 256 257 integrate void 258 clmpcc_enable_transmitter(ch) 259 struct clmpcc_chan *ch; 260 { 261 u_int old; 262 int s; 263 264 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 265 266 s = splserial(); 267 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 268 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 269 SET(ch->ch_tty->t_state, TS_BUSY); 270 splx(s); 271 272 clmpcc_select_channel(ch->ch_sc, old); 273 } 274 275 static int 276 clmpcc_speed(sc, speed, cor, bpr) 277 struct clmpcc_softc *sc; 278 speed_t speed; 279 int *cor, *bpr; 280 { 281 int c, co, br; 282 283 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 284 br = ((sc->sc_clk / c) / speed) - 1; 285 if ( br < 0x100 ) { 286 *cor = co; 287 *bpr = br; 288 return 0; 289 } 290 } 291 292 return -1; 293 } 294 295 void 296 clmpcc_attach(sc) 297 struct clmpcc_softc *sc; 298 { 299 struct clmpcc_chan *ch; 300 struct tty *tp; 301 int chan; 302 303 if ( cons_sc != NULL && 304 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 305 cons_sc = sc; 306 307 /* Initialise the chip */ 308 clmpcc_init(sc); 309 310 printf(": Cirrus Logic CD240%c Serial Controller\n", 311 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 312 313 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 314 sc->sc_soft_running = 0; 315 #else 316 sc->sc_softintr_cookie = 317 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc); 318 #ifdef DEBUG 319 if (sc->sc_softintr_cookie == NULL) 320 panic("clmpcc_attach: softintr_establish"); 321 #endif 322 #endif 323 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 324 325 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 326 ch = &sc->sc_chans[chan]; 327 328 ch->ch_sc = sc; 329 ch->ch_car = chan; 330 331 tp = ttymalloc(); 332 tp->t_oproc = clmpcc_start; 333 tp->t_param = clmpcc_param; 334 335 ch->ch_tty = tp; 336 337 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 338 if ( ch->ch_ibuf == NULL ) { 339 printf("%s(%d): unable to allocate ring buffer\n", 340 sc->sc_dev.dv_xname, chan); 341 return; 342 } 343 344 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 345 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 346 347 tty_attach(tp); 348 } 349 350 printf("%s: %d channels available", sc->sc_dev.dv_xname, 351 CLMPCC_NUM_CHANS); 352 if ( cons_sc == sc ) { 353 printf(", console on channel %d.\n", cons_chan); 354 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 355 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 356 } else 357 printf(".\n"); 358 } 359 360 static int 361 clmpcc_init(sc) 362 struct clmpcc_softc *sc; 363 { 364 u_int tcor, tbpr; 365 u_int rcor, rbpr; 366 u_int msvr_rts, msvr_dtr; 367 u_int ccr; 368 int is_console; 369 int i; 370 371 /* 372 * All we're really concerned about here is putting the chip 373 * into a quiescent state so that it won't do anything until 374 * clmpccopen() is called. (Except the console channel.) 375 */ 376 377 /* 378 * If the chip is acting as console, set all channels to the supplied 379 * console baud rate. Otherwise, plump for 9600. 380 */ 381 if ( cons_sc && 382 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 383 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 384 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 385 is_console = 1; 386 } else { 387 clmpcc_speed(sc, 9600, &tcor, &tbpr); 388 clmpcc_speed(sc, 9600, &rcor, &rbpr); 389 is_console = 0; 390 } 391 392 /* Allow any pending output to be sent */ 393 delay(10000); 394 395 /* Send the Reset All command to channel 0 (resets all channels!) */ 396 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 397 398 delay(1000); 399 400 /* 401 * The chip will set it's firmware revision register to a non-zero 402 * value to indicate completion of reset. 403 */ 404 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 405 delay(1); 406 407 if ( i == 0 ) { 408 /* 409 * Watch out... If this chip is console, the message 410 * probably won't be sent since we just reset it! 411 */ 412 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 413 return -1; 414 } 415 416 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 417 clmpcc_select_channel(sc, i); 418 419 /* All interrupts are disabled to begin with */ 420 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 421 422 /* Make sure the channel interrupts on the correct vectors */ 423 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 424 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 425 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 426 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 427 428 /* Receive timer prescaler set to 1ms */ 429 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 430 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 431 432 /* We support Async mode only */ 433 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 434 435 /* Set the required baud rate */ 436 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 437 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 438 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 439 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 440 441 /* Always default to 8N1 (XXX what about console?) */ 442 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 443 CLMPCC_COR1_NO_PARITY | 444 CLMPCC_COR1_IGNORE_PAR); 445 446 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 447 448 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 449 450 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 451 CLMPCC_COR4_CDzd | 452 CLMPCC_COR4_CTSzd); 453 454 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 455 CLMPCC_COR5_CDod | 456 CLMPCC_COR5_CTSod | 457 CLMPCC_COR5_FLOW_NORM); 458 459 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 460 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 461 462 /* Set the receive FIFO timeout */ 463 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 464 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 465 466 /* At this point, we set up the console differently */ 467 if ( is_console && i == cons_chan ) { 468 msvr_rts = CLMPCC_MSVR_RTS; 469 msvr_dtr = CLMPCC_MSVR_DTR; 470 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 471 } else { 472 msvr_rts = 0; 473 msvr_dtr = 0; 474 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 475 } 476 477 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 478 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 479 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 480 delay(100); 481 } 482 483 return 0; 484 } 485 486 static void 487 clmpcc_shutdown(ch) 488 struct clmpcc_chan *ch; 489 { 490 int oldch; 491 492 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 493 494 /* Turn off interrupts. */ 495 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 496 497 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 498 /* Disable the transmitter and receiver */ 499 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 500 CLMPCC_CCR_T0_TX_DIS); 501 502 /* Drop RTS and DTR */ 503 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 504 } 505 506 clmpcc_select_channel(ch->ch_sc, oldch); 507 } 508 509 int 510 clmpccopen(dev, flag, mode, l) 511 dev_t dev; 512 int flag, mode; 513 struct lwp *l; 514 { 515 struct clmpcc_softc *sc; 516 struct clmpcc_chan *ch; 517 struct tty *tp; 518 int oldch; 519 int error; 520 521 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 522 if (sc == NULL) 523 return (ENXIO); 524 525 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 526 527 tp = ch->ch_tty; 528 529 if ( ISSET(tp->t_state, TS_ISOPEN) && 530 ISSET(tp->t_state, TS_XCLUDE) && 531 suser(l->l_proc->p_ucred, &l->l_proc->p_acflag) != 0 ) 532 return EBUSY; 533 534 /* 535 * Do the following iff this is a first open. 536 */ 537 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 538 539 ttychars(tp); 540 541 tp->t_dev = dev; 542 tp->t_iflag = TTYDEF_IFLAG; 543 tp->t_oflag = TTYDEF_OFLAG; 544 tp->t_lflag = TTYDEF_LFLAG; 545 tp->t_cflag = TTYDEF_CFLAG; 546 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 547 548 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 549 SET(tp->t_cflag, CLOCAL); 550 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 551 SET(tp->t_cflag, CRTSCTS); 552 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 553 SET(tp->t_cflag, MDMBUF); 554 555 /* 556 * Override some settings if the channel is being 557 * used as the console. 558 */ 559 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 560 tp->t_ospeed = tp->t_ispeed = cons_rate; 561 SET(tp->t_cflag, CLOCAL); 562 CLR(tp->t_cflag, CRTSCTS); 563 CLR(tp->t_cflag, HUPCL); 564 } 565 566 ch->ch_control = 0; 567 568 clmpcc_param(tp, &tp->t_termios); 569 ttsetwater(tp); 570 571 /* Clear the input ring */ 572 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 573 574 /* Select the channel */ 575 oldch = clmpcc_select_channel(sc, ch->ch_car); 576 577 /* Reset it */ 578 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 579 CLMPCC_CCR_T0_RX_EN | 580 CLMPCC_CCR_T0_TX_EN); 581 582 /* Enable receiver and modem change interrupts. */ 583 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 584 CLMPCC_IER_RET | 585 CLMPCC_IER_RX_FIFO); 586 587 /* Raise RTS and DTR */ 588 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 589 590 clmpcc_select_channel(sc, oldch); 591 } 592 593 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 594 if (error) 595 goto bad; 596 597 error = (*tp->t_linesw->l_open)(dev, tp); 598 if (error) 599 goto bad; 600 601 return 0; 602 603 bad: 604 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 605 /* 606 * We failed to open the device, and nobody else had it opened. 607 * Clean up the state as appropriate. 608 */ 609 clmpcc_shutdown(ch); 610 } 611 612 return error; 613 } 614 615 int 616 clmpccclose(dev, flag, mode, l) 617 dev_t dev; 618 int flag, mode; 619 struct lwp *l; 620 { 621 struct clmpcc_softc *sc = 622 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 623 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 624 struct tty *tp = ch->ch_tty; 625 int s; 626 627 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 628 return 0; 629 630 (*tp->t_linesw->l_close)(tp, flag); 631 632 s = spltty(); 633 634 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 635 /* 636 * Although we got a last close, the device may still be in 637 * use; e.g. if this was the dialout node, and there are still 638 * processes waiting for carrier on the non-dialout node. 639 */ 640 clmpcc_shutdown(ch); 641 } 642 643 ttyclose(tp); 644 645 splx(s); 646 647 return 0; 648 } 649 650 int 651 clmpccread(dev, uio, flag) 652 dev_t dev; 653 struct uio *uio; 654 int flag; 655 { 656 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 657 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 658 659 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 660 } 661 662 int 663 clmpccwrite(dev, uio, flag) 664 dev_t dev; 665 struct uio *uio; 666 int flag; 667 { 668 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 669 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 670 671 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 672 } 673 674 int 675 clmpccpoll(dev, events, l) 676 dev_t dev; 677 int events; 678 struct lwp *l; 679 { 680 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 681 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 682 683 return ((*tp->t_linesw->l_poll)(tp, events, l)); 684 } 685 686 struct tty * 687 clmpcctty(dev) 688 dev_t dev; 689 { 690 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 691 692 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 693 } 694 695 int 696 clmpccioctl(dev, cmd, data, flag, l) 697 dev_t dev; 698 u_long cmd; 699 caddr_t data; 700 int flag; 701 struct lwp *l; 702 { 703 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 704 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 705 struct tty *tp = ch->ch_tty; 706 int error; 707 708 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 709 if (error != EPASSTHROUGH) 710 return error; 711 712 error = ttioctl(tp, cmd, data, flag, l); 713 if (error != EPASSTHROUGH) 714 return error; 715 716 error = 0; 717 718 switch (cmd) { 719 case TIOCSBRK: 720 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 721 clmpcc_enable_transmitter(ch); 722 break; 723 724 case TIOCCBRK: 725 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 726 clmpcc_enable_transmitter(ch); 727 break; 728 729 case TIOCSDTR: 730 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 731 break; 732 733 case TIOCCDTR: 734 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 735 break; 736 737 case TIOCMSET: 738 clmpcc_modem_control(ch, *((int *)data), DMSET); 739 break; 740 741 case TIOCMBIS: 742 clmpcc_modem_control(ch, *((int *)data), DMBIS); 743 break; 744 745 case TIOCMBIC: 746 clmpcc_modem_control(ch, *((int *)data), DMBIC); 747 break; 748 749 case TIOCMGET: 750 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 751 break; 752 753 case TIOCGFLAGS: 754 *((int *)data) = ch->ch_openflags; 755 break; 756 757 case TIOCSFLAGS: 758 error = suser(l->l_proc->p_ucred, &l->l_proc->p_acflag); 759 if ( error ) 760 break; 761 ch->ch_openflags = *((int *)data) & 762 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 763 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 764 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 765 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 766 break; 767 768 default: 769 error = EPASSTHROUGH; 770 break; 771 } 772 773 return error; 774 } 775 776 int 777 clmpcc_modem_control(ch, bits, howto) 778 struct clmpcc_chan *ch; 779 int bits; 780 int howto; 781 { 782 struct clmpcc_softc *sc = ch->ch_sc; 783 struct tty *tp = ch->ch_tty; 784 int oldch; 785 int msvr; 786 int rbits = 0; 787 788 oldch = clmpcc_select_channel(sc, ch->ch_car); 789 790 switch ( howto ) { 791 case DMGET: 792 msvr = clmpcc_rd_msvr(sc); 793 794 if ( sc->sc_swaprtsdtr ) { 795 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 796 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 797 } else { 798 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 799 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 800 } 801 802 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 803 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 804 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 805 break; 806 807 case DMSET: 808 if ( sc->sc_swaprtsdtr ) { 809 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 810 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 811 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 812 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 813 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 814 } else { 815 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 816 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 817 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 818 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 819 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 820 } 821 break; 822 823 case DMBIS: 824 if ( sc->sc_swaprtsdtr ) { 825 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 826 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 827 if ( ISSET(bits, TIOCM_DTR) ) 828 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 829 } else { 830 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 831 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 832 if ( ISSET(bits, TIOCM_DTR) ) 833 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 834 } 835 break; 836 837 case DMBIC: 838 if ( sc->sc_swaprtsdtr ) { 839 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 840 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 841 if ( ISCLR(bits, TIOCM_DTR) ) 842 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 843 } else { 844 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 845 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 846 if ( ISCLR(bits, TIOCM_DTR) ) 847 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 848 } 849 break; 850 } 851 852 clmpcc_select_channel(sc, oldch); 853 854 return rbits; 855 } 856 857 static int 858 clmpcc_param(tp, t) 859 struct tty *tp; 860 struct termios *t; 861 { 862 struct clmpcc_softc *sc = 863 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 864 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 865 u_char cor; 866 u_char oldch; 867 int oclk, obpr; 868 int iclk, ibpr; 869 int s; 870 871 /* Check requested parameters. */ 872 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 873 return EINVAL; 874 875 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 876 return EINVAL; 877 878 /* 879 * For the console, always force CLOCAL and !HUPCL, so that the port 880 * is always active. 881 */ 882 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 883 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 884 SET(t->c_cflag, CLOCAL); 885 CLR(t->c_cflag, HUPCL); 886 } 887 888 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 889 890 /* If ospeed it zero, hangup the line */ 891 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 892 893 if ( t->c_ospeed ) { 894 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 895 ch->ch_tbpr = obpr; 896 } else { 897 ch->ch_tcor = 0; 898 ch->ch_tbpr = 0; 899 } 900 901 if ( t->c_ispeed ) { 902 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 903 ch->ch_rbpr = ibpr; 904 } else { 905 ch->ch_rcor = 0; 906 ch->ch_rbpr = 0; 907 } 908 909 /* Work out value to use for COR1 */ 910 cor = 0; 911 if ( ISSET(t->c_cflag, PARENB) ) { 912 cor |= CLMPCC_COR1_NORM_PARITY; 913 if ( ISSET(t->c_cflag, PARODD) ) 914 cor |= CLMPCC_COR1_ODD_PARITY; 915 } 916 917 if ( ISCLR(t->c_cflag, INPCK) ) 918 cor |= CLMPCC_COR1_IGNORE_PAR; 919 920 switch ( t->c_cflag & CSIZE ) { 921 case CS5: 922 cor |= CLMPCC_COR1_CHAR_5BITS; 923 break; 924 925 case CS6: 926 cor |= CLMPCC_COR1_CHAR_6BITS; 927 break; 928 929 case CS7: 930 cor |= CLMPCC_COR1_CHAR_7BITS; 931 break; 932 933 case CS8: 934 cor |= CLMPCC_COR1_CHAR_8BITS; 935 break; 936 } 937 938 ch->ch_cor1 = cor; 939 940 /* 941 * The only interesting bit in COR2 is 'CTS Automatic Enable' 942 * when hardware flow control is in effect. 943 */ 944 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 945 946 /* COR3 needs to be set to the number of stop bits... */ 947 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 948 CLMPCC_COR3_STOP_1; 949 950 /* 951 * COR4 contains the FIFO threshold setting. 952 * We adjust the threshold depending on the input speed... 953 */ 954 if ( t->c_ispeed <= 1200 ) 955 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 956 else if ( t->c_ispeed <= 19200 ) 957 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 958 else 959 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 960 961 /* 962 * If chip is used with CTS and DTR swapped, we can enable 963 * automatic hardware flow control. 964 */ 965 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 966 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 967 else 968 ch->ch_cor5 = 0; 969 970 s = splserial(); 971 oldch = clmpcc_select_channel(sc, ch->ch_car); 972 973 /* 974 * COR2 needs to be set immediately otherwise we might never get 975 * a Tx EMPTY interrupt to change the other parameters. 976 */ 977 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 978 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 979 980 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 981 clmpcc_set_params(ch); 982 else 983 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 984 985 clmpcc_select_channel(sc, oldch); 986 987 splx(s); 988 989 return 0; 990 } 991 992 static void 993 clmpcc_set_params(ch) 994 struct clmpcc_chan *ch; 995 { 996 struct clmpcc_softc *sc = ch->ch_sc; 997 u_char r1; 998 u_char r2; 999 1000 if ( ch->ch_tcor || ch->ch_tbpr ) { 1001 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 1002 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 1003 /* Only write Tx rate if it really has changed */ 1004 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 1005 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 1006 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 1007 } 1008 } 1009 1010 if ( ch->ch_rcor || ch->ch_rbpr ) { 1011 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 1012 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 1013 /* Only write Rx rate if it really has changed */ 1014 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 1015 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 1016 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1017 } 1018 } 1019 1020 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1021 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1022 /* Any change to COR1 requires an INIT command */ 1023 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1024 } 1025 1026 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1027 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1028 1029 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1030 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1031 /* 1032 * Note: If the FIFO has changed, we always set it to 1033 * zero here and disable the Receive Timeout interrupt. 1034 * It's up to the Rx Interrupt handler to pick the 1035 * appropriate moment to write the new FIFO length. 1036 */ 1037 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1038 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1039 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1040 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1041 } 1042 1043 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1044 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1045 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1046 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1047 } 1048 } 1049 1050 static void 1051 clmpcc_start(tp) 1052 struct tty *tp; 1053 { 1054 struct clmpcc_softc *sc = 1055 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1056 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1057 u_int oldch; 1058 int s; 1059 1060 s = spltty(); 1061 1062 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1063 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1064 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1065 CLR(tp->t_state, TS_ASLEEP); 1066 wakeup(&tp->t_outq); 1067 } 1068 selwakeup(&tp->t_wsel); 1069 } 1070 1071 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1072 CLMPCC_FLG_END_BREAK) || 1073 tp->t_outq.c_cc > 0 ) { 1074 1075 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1076 CLMPCC_FLG_END_BREAK) ) { 1077 ch->ch_obuf_addr = tp->t_outq.c_cf; 1078 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1079 } 1080 1081 /* Enable TX empty interrupts */ 1082 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1083 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1084 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1085 CLMPCC_IER_TX_EMPTY); 1086 clmpcc_select_channel(ch->ch_sc, oldch); 1087 SET(tp->t_state, TS_BUSY); 1088 } 1089 } 1090 1091 splx(s); 1092 } 1093 1094 /* 1095 * Stop output on a line. 1096 */ 1097 void 1098 clmpccstop(tp, flag) 1099 struct tty *tp; 1100 int flag; 1101 { 1102 struct clmpcc_softc *sc = 1103 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1104 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1105 int s; 1106 1107 s = splserial(); 1108 1109 if ( ISSET(tp->t_state, TS_BUSY) ) { 1110 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1111 SET(tp->t_state, TS_FLUSH); 1112 ch->ch_obuf_size = 0; 1113 } 1114 splx(s); 1115 } 1116 1117 /* 1118 * RX interrupt routine 1119 */ 1120 int 1121 clmpcc_rxintr(arg) 1122 void *arg; 1123 { 1124 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1125 struct clmpcc_chan *ch; 1126 u_int8_t *put, *end, rxd; 1127 u_char errstat; 1128 u_char fc, tc; 1129 u_char risr; 1130 u_char rir; 1131 #ifdef DDB 1132 int saw_break = 0; 1133 #endif 1134 1135 /* Receive interrupt active? */ 1136 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1137 1138 /* 1139 * If we're using auto-vectored interrupts, we have to 1140 * verify if the chip is generating the interrupt. 1141 */ 1142 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1143 return 0; 1144 1145 /* Get pointer to interrupting channel's data structure */ 1146 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1147 1148 /* Get the interrupt status register */ 1149 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1150 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1151 u_char reg; 1152 /* 1153 * Set the FIFO threshold to zero, and disable 1154 * further receive timeout interrupts. 1155 */ 1156 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1157 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1158 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1159 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1160 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1161 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1162 return 1; 1163 } 1164 1165 /* How many bytes are waiting in the FIFO? */ 1166 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1167 1168 #ifdef DDB 1169 /* 1170 * Allow BREAK on the console to drop to the debugger. 1171 */ 1172 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1173 risr & CLMPCC_RISR_BREAK ) { 1174 saw_break = 1; 1175 } 1176 #endif 1177 1178 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1179 /* Just get rid of the data */ 1180 while ( fc-- ) 1181 (void) clmpcc_rd_rxdata(sc); 1182 goto rx_done; 1183 } 1184 1185 put = ch->ch_ibuf_wr; 1186 end = ch->ch_ibuf_end; 1187 1188 /* 1189 * Note: The chip is completely hosed WRT these error 1190 * conditions; there seems to be no way to associate 1191 * the error with the correct character in the FIFO. 1192 * We compromise by tagging the first character we read 1193 * with the error. Not perfect, but there's no other way. 1194 */ 1195 errstat = 0; 1196 if ( risr & CLMPCC_RISR_PARITY ) 1197 errstat |= TTY_PE; 1198 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1199 errstat |= TTY_FE; 1200 1201 /* 1202 * As long as there are characters in the FIFO, and we 1203 * have space for them... 1204 */ 1205 while ( fc > 0 ) { 1206 1207 *put++ = rxd = clmpcc_rd_rxdata(sc); 1208 *put++ = errstat; 1209 1210 if ( put >= end ) 1211 put = ch->ch_ibuf; 1212 1213 if ( put == ch->ch_ibuf_rd ) { 1214 put -= 2; 1215 if ( put < ch->ch_ibuf ) 1216 put = end - 2; 1217 } 1218 1219 errstat = 0; 1220 fc--; 1221 } 1222 1223 ch->ch_ibuf_wr = put; 1224 1225 #if 0 1226 if ( sc->sc_swaprtsdtr == 0 && 1227 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1228 /* 1229 * If RTS/DTR are not physically swapped, we have to 1230 * do hardware flow control manually 1231 */ 1232 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1233 } 1234 #endif 1235 1236 rx_done: 1237 if ( fc != tc ) { 1238 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1239 u_char reg; 1240 /* 1241 * Set the FIFO threshold to the preset value, 1242 * and enable receive timeout interrupts. 1243 */ 1244 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1245 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1246 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1247 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1248 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1249 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1250 } 1251 1252 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1253 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1254 if ( sc->sc_soft_running == 0 ) { 1255 sc->sc_soft_running = 1; 1256 (sc->sc_softhook)(sc); 1257 } 1258 #else 1259 softintr_schedule(sc->sc_softintr_cookie); 1260 #endif 1261 } else 1262 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1263 1264 #ifdef DDB 1265 /* 1266 * Only =after= we write REOIR is it safe to drop to the debugger. 1267 */ 1268 if ( saw_break ) 1269 Debugger(); 1270 #endif 1271 1272 return 1; 1273 } 1274 1275 /* 1276 * Tx interrupt routine 1277 */ 1278 int 1279 clmpcc_txintr(arg) 1280 void *arg; 1281 { 1282 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1283 struct clmpcc_chan *ch; 1284 struct tty *tp; 1285 u_char ftc, oftc; 1286 u_char tir, teoir; 1287 int etcmode = 0; 1288 1289 /* Tx interrupt active? */ 1290 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1291 1292 /* 1293 * If we're using auto-vectored interrupts, we have to 1294 * verify if the chip is generating the interrupt. 1295 */ 1296 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1297 return 0; 1298 1299 /* Get pointer to interrupting channel's data structure */ 1300 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1301 tp = ch->ch_tty; 1302 1303 /* Dummy read of the interrupt status register */ 1304 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1305 1306 /* Make sure embedded transmit commands are disabled */ 1307 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1308 1309 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1310 1311 /* Handle a delayed parameter change */ 1312 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1313 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1314 clmpcc_set_params(ch); 1315 } 1316 1317 if ( ch->ch_obuf_size > 0 ) { 1318 u_int n = min(ch->ch_obuf_size, ftc); 1319 1320 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1321 1322 ftc -= n; 1323 ch->ch_obuf_size -= n; 1324 ch->ch_obuf_addr += n; 1325 1326 } else { 1327 /* 1328 * Check if we should start/stop a break 1329 */ 1330 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1331 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1332 /* Enable embedded transmit commands */ 1333 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1334 ch->ch_cor2 | CLMPCC_COR2_ETC); 1335 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1336 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1337 ftc -= 2; 1338 etcmode = 1; 1339 } 1340 1341 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1342 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1343 /* Enable embedded transmit commands */ 1344 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1345 ch->ch_cor2 | CLMPCC_COR2_ETC); 1346 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1347 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1348 ftc -= 2; 1349 etcmode = 1; 1350 } 1351 } 1352 1353 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1354 1355 if ( ftc != oftc ) { 1356 /* 1357 * Enable/disable the Tx FIFO threshold interrupt 1358 * according to how much data is in the FIFO. 1359 * However, always disable the FIFO threshold if 1360 * we've left the channel in 'Embedded Transmit 1361 * Command' mode. 1362 */ 1363 if ( etcmode || ftc >= ch->ch_cor4 ) 1364 tir &= ~CLMPCC_IER_TX_FIFO; 1365 else 1366 tir |= CLMPCC_IER_TX_FIFO; 1367 teoir = 0; 1368 } else { 1369 /* 1370 * No data was sent. 1371 * Disable transmit interrupt. 1372 */ 1373 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1374 teoir = CLMPCC_TEOIR_NO_TRANS; 1375 1376 /* 1377 * Request Tx processing in the soft interrupt handler 1378 */ 1379 ch->ch_tx_done = 1; 1380 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1381 if ( sc->sc_soft_running == 0 ) { 1382 sc->sc_soft_running = 1; 1383 (sc->sc_softhook)(sc); 1384 } 1385 #else 1386 softintr_schedule(sc->sc_softintr_cookie); 1387 #endif 1388 } 1389 1390 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1391 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1392 1393 return 1; 1394 } 1395 1396 /* 1397 * Modem change interrupt routine 1398 */ 1399 int 1400 clmpcc_mdintr(arg) 1401 void *arg; 1402 { 1403 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1404 u_char mir; 1405 1406 /* Modem status interrupt active? */ 1407 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1408 1409 /* 1410 * If we're using auto-vectored interrupts, we have to 1411 * verify if the chip is generating the interrupt. 1412 */ 1413 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1414 return 0; 1415 1416 /* Dummy read of the interrupt status register */ 1417 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1418 1419 /* Retrieve current status of modem lines. */ 1420 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1421 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1422 1423 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1424 1425 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1426 if ( sc->sc_soft_running == 0 ) { 1427 sc->sc_soft_running = 1; 1428 (sc->sc_softhook)(sc); 1429 } 1430 #else 1431 softintr_schedule(sc->sc_softintr_cookie); 1432 #endif 1433 1434 return 1; 1435 } 1436 1437 void 1438 clmpcc_softintr(arg) 1439 void *arg; 1440 { 1441 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1442 struct clmpcc_chan *ch; 1443 struct tty *tp; 1444 int (*rint)(int, struct tty *); 1445 u_char *get; 1446 u_char reg; 1447 u_int c; 1448 int chan; 1449 1450 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1451 sc->sc_soft_running = 0; 1452 #endif 1453 1454 /* Handle Modem state changes too... */ 1455 1456 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1457 ch = &sc->sc_chans[chan]; 1458 tp = ch->ch_tty; 1459 1460 get = ch->ch_ibuf_rd; 1461 rint = tp->t_linesw->l_rint; 1462 1463 /* Squirt buffered incoming data into the tty layer */ 1464 while ( get != ch->ch_ibuf_wr ) { 1465 c = get[0]; 1466 c |= ((u_int)get[1]) << 8; 1467 if ( (rint)(c, tp) == -1 ) { 1468 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1469 break; 1470 } 1471 1472 get += 2; 1473 if ( get == ch->ch_ibuf_end ) 1474 get = ch->ch_ibuf; 1475 1476 ch->ch_ibuf_rd = get; 1477 } 1478 1479 /* 1480 * Is the transmitter idle and in need of attention? 1481 */ 1482 if ( ch->ch_tx_done ) { 1483 ch->ch_tx_done = 0; 1484 1485 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1486 clmpcc_channel_cmd(sc, ch->ch_car, 1487 CLMPCC_CCR_T0_INIT | 1488 CLMPCC_CCR_T0_RX_EN | 1489 CLMPCC_CCR_T0_TX_EN); 1490 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1491 1492 /* 1493 * Allow time for the channel to initialise. 1494 * (Empirically derived duration; there must 1495 * be another way to determine the command 1496 * has completed without busy-waiting...) 1497 */ 1498 delay(800); 1499 1500 /* 1501 * Update the tty layer's idea of the carrier 1502 * bit, in case we changed CLOCAL or MDMBUF. 1503 * We don't hang up here; we only do that by 1504 * explicit request. 1505 */ 1506 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1507 (*tp->t_linesw->l_modem)(tp, reg != 0); 1508 } 1509 1510 CLR(tp->t_state, TS_BUSY); 1511 if ( ISSET(tp->t_state, TS_FLUSH) ) 1512 CLR(tp->t_state, TS_FLUSH); 1513 else 1514 ndflush(&tp->t_outq, 1515 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1516 1517 (*tp->t_linesw->l_start)(tp); 1518 } 1519 } 1520 } 1521 1522 1523 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1524 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1525 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1526 /* 1527 * Following are all routines needed for a cd240x channel to act as console 1528 */ 1529 int 1530 clmpcc_cnattach(sc, chan, rate) 1531 struct clmpcc_softc *sc; 1532 int chan; 1533 int rate; 1534 { 1535 cons_sc = sc; 1536 cons_chan = chan; 1537 cons_rate = rate; 1538 1539 return (clmpcc_init(sc)); 1540 } 1541 1542 /* 1543 * The following functions are polled getc and putc routines, for console use. 1544 */ 1545 static int 1546 clmpcc_common_getc(sc, chan) 1547 struct clmpcc_softc *sc; 1548 int chan; 1549 { 1550 u_char old_chan; 1551 u_char old_ier; 1552 u_char ch, rir, risr; 1553 int s; 1554 1555 s = splhigh(); 1556 1557 /* Save the currently active channel */ 1558 old_chan = clmpcc_select_channel(sc, chan); 1559 1560 /* 1561 * We have to put the channel into RX interrupt mode before 1562 * trying to read the Rx data register. So save the previous 1563 * interrupt mode. 1564 */ 1565 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1566 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1567 1568 /* Loop until we get a character */ 1569 for (;;) { 1570 /* 1571 * The REN bit will be set in the Receive Interrupt Register 1572 * when the CD240x has a character to process. Remember, 1573 * the RACT bit won't be set until we generate an interrupt 1574 * acknowledge cycle via the MD front-end. 1575 */ 1576 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1577 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1578 continue; 1579 1580 /* Acknowledge the request */ 1581 if ( sc->sc_iackhook ) 1582 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1583 1584 /* 1585 * Determine if the interrupt is for the required channel 1586 * and if valid data is available. 1587 */ 1588 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1589 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1590 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1591 risr != 0 ) { 1592 /* Rx error, or BREAK */ 1593 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1594 CLMPCC_REOIR_NO_TRANS); 1595 } else { 1596 /* Dummy read of the FIFO count register */ 1597 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1598 1599 /* Fetch the received character */ 1600 ch = clmpcc_rd_rxdata(sc); 1601 1602 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1603 break; 1604 } 1605 } 1606 1607 /* Restore the original IER and CAR register contents */ 1608 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1609 clmpcc_select_channel(sc, old_chan); 1610 1611 splx(s); 1612 return ch; 1613 } 1614 1615 1616 static void 1617 clmpcc_common_putc(sc, chan, c) 1618 struct clmpcc_softc *sc; 1619 int chan; 1620 int c; 1621 { 1622 u_char old_chan; 1623 int s = splhigh(); 1624 1625 /* Save the currently active channel */ 1626 old_chan = clmpcc_select_channel(sc, chan); 1627 1628 /* 1629 * Since we can only access the Tx Data register from within 1630 * the interrupt handler, the easiest way to get console data 1631 * onto the wire is using one of the Special Transmit Character 1632 * registers. 1633 */ 1634 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1635 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1636 CLMPCC_STCR_SND_SPC); 1637 1638 /* Wait until the "Send Special Character" command is accepted */ 1639 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1640 ; 1641 1642 /* Restore the previous channel selected */ 1643 clmpcc_select_channel(sc, old_chan); 1644 1645 splx(s); 1646 } 1647 1648 int 1649 clmpcccngetc(dev) 1650 dev_t dev; 1651 { 1652 return clmpcc_common_getc(cons_sc, cons_chan); 1653 } 1654 1655 /* 1656 * Console kernel output character routine. 1657 */ 1658 void 1659 clmpcccnputc(dev, c) 1660 dev_t dev; 1661 int c; 1662 { 1663 if ( c == '\n' ) 1664 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1665 1666 clmpcc_common_putc(cons_sc, cons_chan, c); 1667 } 1668