1 /* $NetBSD: clmpcc.c,v 1.51 2014/11/15 19:18:18 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.51 2014/11/15 19:18:18 christos Exp $"); 38 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ioctl.h> 44 #include <sys/select.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/conf.h> 48 #include <sys/file.h> 49 #include <sys/uio.h> 50 #include <sys/kernel.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 #include <sys/kauth.h> 55 #include <sys/intr.h> 56 57 #include <sys/bus.h> 58 #include <machine/param.h> 59 60 #include <dev/ic/clmpccreg.h> 61 #include <dev/ic/clmpccvar.h> 62 #include <dev/cons.h> 63 64 65 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 66 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 67 #endif 68 69 70 static int clmpcc_init(struct clmpcc_softc *sc); 71 static void clmpcc_shutdown(struct clmpcc_chan *); 72 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *); 73 static int clmpcc_param(struct tty *, struct termios *); 74 static void clmpcc_set_params(struct clmpcc_chan *); 75 static void clmpcc_start(struct tty *); 76 static int clmpcc_modem_control(struct clmpcc_chan *, int, int); 77 78 #define CLMPCCUNIT(x) (TTUNIT(x) & ~0x3) // XXX >> 2? 79 #define CLMPCCCHAN(x) (TTUNIT(x) & 0x3) 80 #define CLMPCCDIALOUT(x) TTDIALOUT(x) 81 82 /* 83 * These should be in a header file somewhere... 84 */ 85 #define ISCLR(v, f) (((v) & (f)) == 0) 86 87 extern struct cfdriver clmpcc_cd; 88 89 dev_type_open(clmpccopen); 90 dev_type_close(clmpccclose); 91 dev_type_read(clmpccread); 92 dev_type_write(clmpccwrite); 93 dev_type_ioctl(clmpccioctl); 94 dev_type_stop(clmpccstop); 95 dev_type_tty(clmpcctty); 96 dev_type_poll(clmpccpoll); 97 98 const struct cdevsw clmpcc_cdevsw = { 99 .d_open = clmpccopen, 100 .d_close = clmpccclose, 101 .d_read = clmpccread, 102 .d_write = clmpccwrite, 103 .d_ioctl = clmpccioctl, 104 .d_stop = clmpccstop, 105 .d_tty = clmpcctty, 106 .d_poll = clmpccpoll, 107 .d_mmap = nommap, 108 .d_kqfilter = ttykqfilter, 109 .d_discard = nodiscard, 110 .d_flag = D_TTY 111 }; 112 113 /* 114 * Make this an option variable one can patch. 115 */ 116 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 117 118 119 /* 120 * Things needed when the device is used as a console 121 */ 122 static struct clmpcc_softc *cons_sc = NULL; 123 static int cons_chan; 124 static int cons_rate; 125 126 static int clmpcc_common_getc(struct clmpcc_softc *, int); 127 static void clmpcc_common_putc(struct clmpcc_softc *, int, int); 128 int clmpcccngetc(dev_t); 129 void clmpcccnputc(dev_t, int); 130 131 132 /* 133 * Convenience functions, inlined for speed 134 */ 135 #define integrate static inline 136 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int); 137 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int); 138 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int); 139 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int); 140 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *, 141 u_int); 142 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int); 143 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int); 144 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *); 145 146 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 147 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 148 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 149 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 150 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 151 152 153 integrate u_int8_t 154 clmpcc_rdreg(struct clmpcc_softc *sc, u_int offset) 155 { 156 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 157 offset ^= sc->sc_byteswap; 158 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 159 offset ^= CLMPCC_BYTESWAP_HIGH; 160 #endif 161 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 162 } 163 164 integrate void 165 clmpcc_wrreg(struct clmpcc_softc *sc, u_int offset, u_int val) 166 { 167 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 168 offset ^= sc->sc_byteswap; 169 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 170 offset ^= CLMPCC_BYTESWAP_HIGH; 171 #endif 172 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 173 } 174 175 integrate u_int8_t 176 clmpcc_rdreg_odd(struct clmpcc_softc *sc, u_int offset) 177 { 178 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 179 offset ^= (sc->sc_byteswap & 2); 180 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 181 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 182 #endif 183 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 184 } 185 186 integrate void 187 clmpcc_wrreg_odd(struct clmpcc_softc *sc, u_int offset, u_int val) 188 { 189 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 190 offset ^= (sc->sc_byteswap & 2); 191 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 192 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 193 #endif 194 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 195 } 196 197 integrate void 198 clmpcc_wrtx_multi(struct clmpcc_softc *sc, u_int8_t *buff, u_int count) 199 { 200 u_int offset = CLMPCC_REG_TDR; 201 202 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 203 offset ^= (sc->sc_byteswap & 2); 204 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 205 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 206 #endif 207 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 208 } 209 210 integrate u_int8_t 211 clmpcc_select_channel(struct clmpcc_softc *sc, u_int new_chan) 212 { 213 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 214 215 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 216 217 return old_chan; 218 } 219 220 integrate void 221 clmpcc_channel_cmd(struct clmpcc_softc *sc, int chan, int cmd) 222 { 223 int i; 224 225 for (i = 5000; i; i--) { 226 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 227 break; 228 delay(1); 229 } 230 231 if ( i == 0 ) 232 printf("%s: channel %d command timeout (idle)\n", 233 device_xname(sc->sc_dev), chan); 234 235 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 236 } 237 238 integrate void 239 clmpcc_enable_transmitter(struct clmpcc_chan *ch) 240 { 241 u_int old; 242 int s; 243 244 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 245 246 s = splserial(); 247 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 248 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 249 SET(ch->ch_tty->t_state, TS_BUSY); 250 splx(s); 251 252 clmpcc_select_channel(ch->ch_sc, old); 253 } 254 255 static int 256 clmpcc_speed(struct clmpcc_softc *sc, speed_t speed, int *cor, int *bpr) 257 { 258 int c, co, br; 259 260 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 261 br = ((sc->sc_clk / c) / speed) - 1; 262 if ( br < 0x100 ) { 263 *cor = co; 264 *bpr = br; 265 return 0; 266 } 267 } 268 269 return -1; 270 } 271 272 void 273 clmpcc_attach(struct clmpcc_softc *sc) 274 { 275 struct clmpcc_chan *ch; 276 struct tty *tp; 277 int chan; 278 279 if ( cons_sc != NULL && 280 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 281 cons_sc = sc; 282 283 /* Initialise the chip */ 284 clmpcc_init(sc); 285 286 printf(": Cirrus Logic CD240%c Serial Controller\n", 287 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 288 289 sc->sc_softintr_cookie = 290 softint_establish(SOFTINT_SERIAL, clmpcc_softintr, sc); 291 if (sc->sc_softintr_cookie == NULL) 292 panic("clmpcc_attach: softintr_establish"); 293 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 294 295 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 296 ch = &sc->sc_chans[chan]; 297 298 ch->ch_sc = sc; 299 ch->ch_car = chan; 300 301 tp = tty_alloc(); 302 tp->t_oproc = clmpcc_start; 303 tp->t_param = clmpcc_param; 304 305 ch->ch_tty = tp; 306 307 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 308 if ( ch->ch_ibuf == NULL ) { 309 aprint_error_dev(sc->sc_dev, "(%d): unable to allocate ring buffer\n", 310 chan); 311 return; 312 } 313 314 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 315 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 316 317 tty_attach(tp); 318 } 319 320 aprint_error_dev(sc->sc_dev, "%d channels available", 321 CLMPCC_NUM_CHANS); 322 if ( cons_sc == sc ) { 323 printf(", console on channel %d.\n", cons_chan); 324 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 325 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 326 } else 327 printf(".\n"); 328 } 329 330 static int 331 clmpcc_init(struct clmpcc_softc *sc) 332 { 333 u_int tcor = 0, tbpr = 0; 334 u_int rcor = 0, rbpr = 0; 335 u_int msvr_rts, msvr_dtr; 336 u_int ccr; 337 int is_console; 338 int i; 339 340 /* 341 * All we're really concerned about here is putting the chip 342 * into a quiescent state so that it won't do anything until 343 * clmpccopen() is called. (Except the console channel.) 344 */ 345 346 /* 347 * If the chip is acting as console, set all channels to the supplied 348 * console baud rate. Otherwise, plump for 9600. 349 */ 350 if ( cons_sc && 351 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 352 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 353 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 354 is_console = 1; 355 } else { 356 clmpcc_speed(sc, 9600, &tcor, &tbpr); 357 clmpcc_speed(sc, 9600, &rcor, &rbpr); 358 is_console = 0; 359 } 360 361 /* Allow any pending output to be sent */ 362 delay(10000); 363 364 /* Send the Reset All command to channel 0 (resets all channels!) */ 365 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 366 367 delay(1000); 368 369 /* 370 * The chip will set its firmware revision register to a non-zero 371 * value to indicate completion of reset. 372 */ 373 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 374 delay(1); 375 376 if ( i == 0 ) { 377 /* 378 * Watch out... If this chip is console, the message 379 * probably won't be sent since we just reset it! 380 */ 381 aprint_error_dev(sc->sc_dev, "Failed to reset chip\n"); 382 return -1; 383 } 384 385 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 386 clmpcc_select_channel(sc, i); 387 388 /* All interrupts are disabled to begin with */ 389 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 390 391 /* Make sure the channel interrupts on the correct vectors */ 392 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 393 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 394 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 395 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 396 397 /* Receive timer prescaler set to 1ms */ 398 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 399 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 400 401 /* We support Async mode only */ 402 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 403 404 /* Set the required baud rate */ 405 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 406 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 407 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 408 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 409 410 /* Always default to 8N1 (XXX what about console?) */ 411 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 412 CLMPCC_COR1_NO_PARITY | 413 CLMPCC_COR1_IGNORE_PAR); 414 415 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 416 417 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 418 419 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 420 CLMPCC_COR4_CDzd | 421 CLMPCC_COR4_CTSzd); 422 423 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 424 CLMPCC_COR5_CDod | 425 CLMPCC_COR5_CTSod | 426 CLMPCC_COR5_FLOW_NORM); 427 428 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 429 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 430 431 /* Set the receive FIFO timeout */ 432 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 433 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 434 435 /* At this point, we set up the console differently */ 436 if ( is_console && i == cons_chan ) { 437 msvr_rts = CLMPCC_MSVR_RTS; 438 msvr_dtr = CLMPCC_MSVR_DTR; 439 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 440 } else { 441 msvr_rts = 0; 442 msvr_dtr = 0; 443 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 444 } 445 446 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 447 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 448 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 449 delay(100); 450 } 451 452 return 0; 453 } 454 455 static void 456 clmpcc_shutdown(struct clmpcc_chan *ch) 457 { 458 int oldch; 459 460 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 461 462 /* Turn off interrupts. */ 463 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 464 465 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 466 /* Disable the transmitter and receiver */ 467 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 468 CLMPCC_CCR_T0_TX_DIS); 469 470 /* Drop RTS and DTR */ 471 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 472 } 473 474 clmpcc_select_channel(ch->ch_sc, oldch); 475 } 476 477 int 478 clmpccopen(dev_t dev, int flag, int mode, struct lwp *l) 479 { 480 struct clmpcc_softc *sc; 481 struct clmpcc_chan *ch; 482 struct tty *tp; 483 int oldch; 484 int error; 485 486 sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 487 if (sc == NULL) 488 return (ENXIO); 489 490 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 491 492 tp = ch->ch_tty; 493 494 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 495 return EBUSY; 496 497 /* 498 * Do the following iff this is a first open. 499 */ 500 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 501 502 ttychars(tp); 503 504 tp->t_dev = dev; 505 tp->t_iflag = TTYDEF_IFLAG; 506 tp->t_oflag = TTYDEF_OFLAG; 507 tp->t_lflag = TTYDEF_LFLAG; 508 tp->t_cflag = TTYDEF_CFLAG; 509 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 510 511 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 512 SET(tp->t_cflag, CLOCAL); 513 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 514 SET(tp->t_cflag, CRTSCTS); 515 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 516 SET(tp->t_cflag, MDMBUF); 517 518 /* 519 * Override some settings if the channel is being 520 * used as the console. 521 */ 522 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 523 tp->t_ospeed = tp->t_ispeed = cons_rate; 524 SET(tp->t_cflag, CLOCAL); 525 CLR(tp->t_cflag, CRTSCTS); 526 CLR(tp->t_cflag, HUPCL); 527 } 528 529 ch->ch_control = 0; 530 531 clmpcc_param(tp, &tp->t_termios); 532 ttsetwater(tp); 533 534 /* Clear the input ring */ 535 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 536 537 /* Select the channel */ 538 oldch = clmpcc_select_channel(sc, ch->ch_car); 539 540 /* Reset it */ 541 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 542 CLMPCC_CCR_T0_RX_EN | 543 CLMPCC_CCR_T0_TX_EN); 544 545 /* Enable receiver and modem change interrupts. */ 546 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 547 CLMPCC_IER_RET | 548 CLMPCC_IER_RX_FIFO); 549 550 /* Raise RTS and DTR */ 551 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 552 553 clmpcc_select_channel(sc, oldch); 554 } 555 556 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 557 if (error) 558 goto bad; 559 560 error = (*tp->t_linesw->l_open)(dev, tp); 561 if (error) 562 goto bad; 563 564 return 0; 565 566 bad: 567 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 568 /* 569 * We failed to open the device, and nobody else had it opened. 570 * Clean up the state as appropriate. 571 */ 572 clmpcc_shutdown(ch); 573 } 574 575 return error; 576 } 577 578 int 579 clmpccclose(dev_t dev, int flag, int mode, struct lwp *l) 580 { 581 struct clmpcc_softc *sc = 582 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 583 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 584 struct tty *tp = ch->ch_tty; 585 int s; 586 587 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 588 return 0; 589 590 (*tp->t_linesw->l_close)(tp, flag); 591 592 s = spltty(); 593 594 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 595 /* 596 * Although we got a last close, the device may still be in 597 * use; e.g. if this was the dialout node, and there are still 598 * processes waiting for carrier on the non-dialout node. 599 */ 600 clmpcc_shutdown(ch); 601 } 602 603 ttyclose(tp); 604 605 splx(s); 606 607 return 0; 608 } 609 610 int 611 clmpccread(dev_t dev, struct uio *uio, int flag) 612 { 613 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 614 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 615 616 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 617 } 618 619 int 620 clmpccwrite(dev_t dev, struct uio *uio, int flag) 621 { 622 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 623 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 624 625 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 626 } 627 628 int 629 clmpccpoll(dev_t dev, int events, struct lwp *l) 630 { 631 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 632 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 633 634 return ((*tp->t_linesw->l_poll)(tp, events, l)); 635 } 636 637 struct tty * 638 clmpcctty(dev_t dev) 639 { 640 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 641 642 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 643 } 644 645 int 646 clmpccioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 647 { 648 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 649 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 650 struct tty *tp = ch->ch_tty; 651 int error; 652 653 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 654 if (error != EPASSTHROUGH) 655 return error; 656 657 error = ttioctl(tp, cmd, data, flag, l); 658 if (error != EPASSTHROUGH) 659 return error; 660 661 error = 0; 662 663 switch (cmd) { 664 case TIOCSBRK: 665 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 666 clmpcc_enable_transmitter(ch); 667 break; 668 669 case TIOCCBRK: 670 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 671 clmpcc_enable_transmitter(ch); 672 break; 673 674 case TIOCSDTR: 675 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 676 break; 677 678 case TIOCCDTR: 679 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 680 break; 681 682 case TIOCMSET: 683 clmpcc_modem_control(ch, *((int *)data), DMSET); 684 break; 685 686 case TIOCMBIS: 687 clmpcc_modem_control(ch, *((int *)data), DMBIS); 688 break; 689 690 case TIOCMBIC: 691 clmpcc_modem_control(ch, *((int *)data), DMBIC); 692 break; 693 694 case TIOCMGET: 695 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 696 break; 697 698 case TIOCGFLAGS: 699 *((int *)data) = ch->ch_openflags; 700 break; 701 702 case TIOCSFLAGS: 703 error = kauth_authorize_device_tty(l->l_cred, 704 KAUTH_DEVICE_TTY_PRIVSET, tp); 705 if ( error ) 706 break; 707 ch->ch_openflags = *((int *)data) & 708 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 709 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 710 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 711 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 712 break; 713 714 default: 715 error = EPASSTHROUGH; 716 break; 717 } 718 719 return error; 720 } 721 722 int 723 clmpcc_modem_control(struct clmpcc_chan *ch, int bits, int howto) 724 { 725 struct clmpcc_softc *sc = ch->ch_sc; 726 struct tty *tp = ch->ch_tty; 727 int oldch; 728 int msvr; 729 int rbits = 0; 730 731 oldch = clmpcc_select_channel(sc, ch->ch_car); 732 733 switch ( howto ) { 734 case DMGET: 735 msvr = clmpcc_rd_msvr(sc); 736 737 if ( sc->sc_swaprtsdtr ) { 738 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 739 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 740 } else { 741 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 742 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 743 } 744 745 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 746 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 747 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 748 break; 749 750 case DMSET: 751 if ( sc->sc_swaprtsdtr ) { 752 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 753 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 754 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 755 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 756 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 757 } else { 758 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 759 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 760 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 761 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 762 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 763 } 764 break; 765 766 case DMBIS: 767 if ( sc->sc_swaprtsdtr ) { 768 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 769 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 770 if ( ISSET(bits, TIOCM_DTR) ) 771 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 772 } else { 773 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 774 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 775 if ( ISSET(bits, TIOCM_DTR) ) 776 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 777 } 778 break; 779 780 case DMBIC: 781 if ( sc->sc_swaprtsdtr ) { 782 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 783 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 784 if ( ISCLR(bits, TIOCM_DTR) ) 785 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 786 } else { 787 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 788 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 789 if ( ISCLR(bits, TIOCM_DTR) ) 790 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 791 } 792 break; 793 } 794 795 clmpcc_select_channel(sc, oldch); 796 797 return rbits; 798 } 799 800 static int 801 clmpcc_param(struct tty *tp, struct termios *t) 802 { 803 struct clmpcc_softc *sc = 804 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 805 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 806 u_char cor; 807 u_char oldch; 808 int oclk = 0, obpr = 0; 809 int iclk = 0, ibpr = 0; 810 int s; 811 812 /* Check requested parameters. */ 813 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 814 return EINVAL; 815 816 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 817 return EINVAL; 818 819 /* 820 * For the console, always force CLOCAL and !HUPCL, so that the port 821 * is always active. 822 */ 823 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 824 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 825 SET(t->c_cflag, CLOCAL); 826 CLR(t->c_cflag, HUPCL); 827 } 828 829 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 830 831 /* If ospeed it zero, hangup the line */ 832 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 833 834 if ( t->c_ospeed ) { 835 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 836 ch->ch_tbpr = obpr; 837 } else { 838 ch->ch_tcor = 0; 839 ch->ch_tbpr = 0; 840 } 841 842 if ( t->c_ispeed ) { 843 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 844 ch->ch_rbpr = ibpr; 845 } else { 846 ch->ch_rcor = 0; 847 ch->ch_rbpr = 0; 848 } 849 850 /* Work out value to use for COR1 */ 851 cor = 0; 852 if ( ISSET(t->c_cflag, PARENB) ) { 853 cor |= CLMPCC_COR1_NORM_PARITY; 854 if ( ISSET(t->c_cflag, PARODD) ) 855 cor |= CLMPCC_COR1_ODD_PARITY; 856 } 857 858 if ( ISCLR(t->c_cflag, INPCK) ) 859 cor |= CLMPCC_COR1_IGNORE_PAR; 860 861 switch ( t->c_cflag & CSIZE ) { 862 case CS5: 863 cor |= CLMPCC_COR1_CHAR_5BITS; 864 break; 865 866 case CS6: 867 cor |= CLMPCC_COR1_CHAR_6BITS; 868 break; 869 870 case CS7: 871 cor |= CLMPCC_COR1_CHAR_7BITS; 872 break; 873 874 case CS8: 875 cor |= CLMPCC_COR1_CHAR_8BITS; 876 break; 877 } 878 879 ch->ch_cor1 = cor; 880 881 /* 882 * The only interesting bit in COR2 is 'CTS Automatic Enable' 883 * when hardware flow control is in effect. 884 */ 885 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 886 887 /* COR3 needs to be set to the number of stop bits... */ 888 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 889 CLMPCC_COR3_STOP_1; 890 891 /* 892 * COR4 contains the FIFO threshold setting. 893 * We adjust the threshold depending on the input speed... 894 */ 895 if ( t->c_ispeed <= 1200 ) 896 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 897 else if ( t->c_ispeed <= 19200 ) 898 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 899 else 900 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 901 902 /* 903 * If chip is used with CTS and DTR swapped, we can enable 904 * automatic hardware flow control. 905 */ 906 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 907 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 908 else 909 ch->ch_cor5 = 0; 910 911 s = splserial(); 912 oldch = clmpcc_select_channel(sc, ch->ch_car); 913 914 /* 915 * COR2 needs to be set immediately otherwise we might never get 916 * a Tx EMPTY interrupt to change the other parameters. 917 */ 918 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 919 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 920 921 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 922 clmpcc_set_params(ch); 923 else 924 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 925 926 clmpcc_select_channel(sc, oldch); 927 928 splx(s); 929 930 return 0; 931 } 932 933 static void 934 clmpcc_set_params(struct clmpcc_chan *ch) 935 { 936 struct clmpcc_softc *sc = ch->ch_sc; 937 u_char r1; 938 u_char r2; 939 940 if ( ch->ch_tcor || ch->ch_tbpr ) { 941 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 942 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 943 /* Only write Tx rate if it really has changed */ 944 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 945 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 946 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 947 } 948 } 949 950 if ( ch->ch_rcor || ch->ch_rbpr ) { 951 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 952 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 953 /* Only write Rx rate if it really has changed */ 954 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 955 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 956 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 957 } 958 } 959 960 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 961 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 962 /* Any change to COR1 requires an INIT command */ 963 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 964 } 965 966 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 967 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 968 969 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 970 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 971 /* 972 * Note: If the FIFO has changed, we always set it to 973 * zero here and disable the Receive Timeout interrupt. 974 * It's up to the Rx Interrupt handler to pick the 975 * appropriate moment to write the new FIFO length. 976 */ 977 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 978 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 979 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 980 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 981 } 982 983 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 984 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 985 r1 &= ~CLMPCC_COR5_FLOW_MASK; 986 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 987 } 988 } 989 990 static void 991 clmpcc_start(struct tty *tp) 992 { 993 struct clmpcc_softc *sc = 994 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 995 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 996 u_int oldch; 997 int s; 998 999 s = spltty(); 1000 1001 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1002 ttypull(tp); 1003 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1004 CLMPCC_FLG_END_BREAK) || 1005 tp->t_outq.c_cc > 0 ) { 1006 1007 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1008 CLMPCC_FLG_END_BREAK) ) { 1009 ch->ch_obuf_addr = tp->t_outq.c_cf; 1010 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1011 } 1012 1013 /* Enable TX empty interrupts */ 1014 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1015 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1016 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1017 CLMPCC_IER_TX_EMPTY); 1018 clmpcc_select_channel(ch->ch_sc, oldch); 1019 SET(tp->t_state, TS_BUSY); 1020 } 1021 } 1022 1023 splx(s); 1024 } 1025 1026 /* 1027 * Stop output on a line. 1028 */ 1029 void 1030 clmpccstop(struct tty *tp, int flag) 1031 { 1032 struct clmpcc_softc *sc = 1033 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1034 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1035 int s; 1036 1037 s = splserial(); 1038 1039 if ( ISSET(tp->t_state, TS_BUSY) ) { 1040 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1041 SET(tp->t_state, TS_FLUSH); 1042 ch->ch_obuf_size = 0; 1043 } 1044 splx(s); 1045 } 1046 1047 /* 1048 * RX interrupt routine 1049 */ 1050 int 1051 clmpcc_rxintr(void *arg) 1052 { 1053 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1054 struct clmpcc_chan *ch; 1055 u_int8_t *put, *end, rxd; 1056 u_char errstat; 1057 u_char fc, tc; 1058 u_char risr; 1059 u_char rir; 1060 #ifdef DDB 1061 int saw_break = 0; 1062 #endif 1063 1064 /* Receive interrupt active? */ 1065 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1066 1067 /* 1068 * If we're using auto-vectored interrupts, we have to 1069 * verify if the chip is generating the interrupt. 1070 */ 1071 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1072 return 0; 1073 1074 /* Get pointer to interrupting channel's data structure */ 1075 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1076 1077 /* Get the interrupt status register */ 1078 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1079 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1080 u_char reg; 1081 /* 1082 * Set the FIFO threshold to zero, and disable 1083 * further receive timeout interrupts. 1084 */ 1085 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1086 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1087 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1088 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1089 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1090 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1091 return 1; 1092 } 1093 1094 /* How many bytes are waiting in the FIFO? */ 1095 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1096 1097 #ifdef DDB 1098 /* 1099 * Allow BREAK on the console to drop to the debugger. 1100 */ 1101 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1102 risr & CLMPCC_RISR_BREAK ) { 1103 saw_break = 1; 1104 } 1105 #endif 1106 1107 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1108 /* Just get rid of the data */ 1109 while ( fc-- ) 1110 (void) clmpcc_rd_rxdata(sc); 1111 goto rx_done; 1112 } 1113 1114 put = ch->ch_ibuf_wr; 1115 end = ch->ch_ibuf_end; 1116 1117 /* 1118 * Note: The chip is completely hosed WRT these error 1119 * conditions; there seems to be no way to associate 1120 * the error with the correct character in the FIFO. 1121 * We compromise by tagging the first character we read 1122 * with the error. Not perfect, but there's no other way. 1123 */ 1124 errstat = 0; 1125 if ( risr & CLMPCC_RISR_PARITY ) 1126 errstat |= TTY_PE; 1127 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1128 errstat |= TTY_FE; 1129 1130 /* 1131 * As long as there are characters in the FIFO, and we 1132 * have space for them... 1133 */ 1134 while ( fc > 0 ) { 1135 1136 *put++ = rxd = clmpcc_rd_rxdata(sc); 1137 *put++ = errstat; 1138 1139 if ( put >= end ) 1140 put = ch->ch_ibuf; 1141 1142 if ( put == ch->ch_ibuf_rd ) { 1143 put -= 2; 1144 if ( put < ch->ch_ibuf ) 1145 put = end - 2; 1146 } 1147 1148 errstat = 0; 1149 fc--; 1150 } 1151 1152 ch->ch_ibuf_wr = put; 1153 1154 #if 0 1155 if ( sc->sc_swaprtsdtr == 0 && 1156 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1157 /* 1158 * If RTS/DTR are not physically swapped, we have to 1159 * do hardware flow control manually 1160 */ 1161 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1162 } 1163 #endif 1164 1165 rx_done: 1166 if ( fc != tc ) { 1167 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1168 u_char reg; 1169 /* 1170 * Set the FIFO threshold to the preset value, 1171 * and enable receive timeout interrupts. 1172 */ 1173 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1174 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1175 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1176 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1177 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1178 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1179 } 1180 1181 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1182 softint_schedule(sc->sc_softintr_cookie); 1183 } else 1184 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1185 1186 #ifdef DDB 1187 /* 1188 * Only =after= we write REOIR is it safe to drop to the debugger. 1189 */ 1190 if ( saw_break ) 1191 Debugger(); 1192 #endif 1193 1194 return 1; 1195 } 1196 1197 /* 1198 * Tx interrupt routine 1199 */ 1200 int 1201 clmpcc_txintr(void *arg) 1202 { 1203 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1204 struct clmpcc_chan *ch; 1205 u_char ftc, oftc; 1206 u_char tir, teoir; 1207 int etcmode = 0; 1208 1209 /* Tx interrupt active? */ 1210 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1211 1212 /* 1213 * If we're using auto-vectored interrupts, we have to 1214 * verify if the chip is generating the interrupt. 1215 */ 1216 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1217 return 0; 1218 1219 /* Get pointer to interrupting channel's data structure */ 1220 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1221 1222 /* Dummy read of the interrupt status register */ 1223 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1224 1225 /* Make sure embedded transmit commands are disabled */ 1226 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1227 1228 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1229 1230 /* Handle a delayed parameter change */ 1231 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1232 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1233 clmpcc_set_params(ch); 1234 } 1235 1236 if ( ch->ch_obuf_size > 0 ) { 1237 u_int n = min(ch->ch_obuf_size, ftc); 1238 1239 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1240 1241 ftc -= n; 1242 ch->ch_obuf_size -= n; 1243 ch->ch_obuf_addr += n; 1244 1245 } else { 1246 /* 1247 * Check if we should start/stop a break 1248 */ 1249 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1250 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1251 /* Enable embedded transmit commands */ 1252 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1253 ch->ch_cor2 | CLMPCC_COR2_ETC); 1254 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1255 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1256 ftc -= 2; 1257 etcmode = 1; 1258 } 1259 1260 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1261 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1262 /* Enable embedded transmit commands */ 1263 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1264 ch->ch_cor2 | CLMPCC_COR2_ETC); 1265 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1266 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1267 ftc -= 2; 1268 etcmode = 1; 1269 } 1270 } 1271 1272 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1273 1274 if ( ftc != oftc ) { 1275 /* 1276 * Enable/disable the Tx FIFO threshold interrupt 1277 * according to how much data is in the FIFO. 1278 * However, always disable the FIFO threshold if 1279 * we've left the channel in 'Embedded Transmit 1280 * Command' mode. 1281 */ 1282 if ( etcmode || ftc >= ch->ch_cor4 ) 1283 tir &= ~CLMPCC_IER_TX_FIFO; 1284 else 1285 tir |= CLMPCC_IER_TX_FIFO; 1286 teoir = 0; 1287 } else { 1288 /* 1289 * No data was sent. 1290 * Disable transmit interrupt. 1291 */ 1292 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1293 teoir = CLMPCC_TEOIR_NO_TRANS; 1294 1295 /* 1296 * Request Tx processing in the soft interrupt handler 1297 */ 1298 ch->ch_tx_done = 1; 1299 softint_schedule(sc->sc_softintr_cookie); 1300 } 1301 1302 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1303 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1304 1305 return 1; 1306 } 1307 1308 /* 1309 * Modem change interrupt routine 1310 */ 1311 int 1312 clmpcc_mdintr(void *arg) 1313 { 1314 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1315 u_char mir; 1316 1317 /* Modem status interrupt active? */ 1318 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1319 1320 /* 1321 * If we're using auto-vectored interrupts, we have to 1322 * verify if the chip is generating the interrupt. 1323 */ 1324 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1325 return 0; 1326 1327 /* Dummy read of the interrupt status register */ 1328 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1329 1330 /* Retrieve current status of modem lines. */ 1331 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1332 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1333 1334 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1335 softint_schedule(sc->sc_softintr_cookie); 1336 1337 return 1; 1338 } 1339 1340 void 1341 clmpcc_softintr(void *arg) 1342 { 1343 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1344 struct clmpcc_chan *ch; 1345 struct tty *tp; 1346 int (*rint)(int, struct tty *); 1347 u_char *get; 1348 u_char reg; 1349 u_int c; 1350 int chan; 1351 1352 /* Handle Modem state changes too... */ 1353 1354 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1355 ch = &sc->sc_chans[chan]; 1356 tp = ch->ch_tty; 1357 1358 get = ch->ch_ibuf_rd; 1359 rint = tp->t_linesw->l_rint; 1360 1361 /* Squirt buffered incoming data into the tty layer */ 1362 while ( get != ch->ch_ibuf_wr ) { 1363 c = get[0]; 1364 c |= ((u_int)get[1]) << 8; 1365 if ( (rint)(c, tp) == -1 ) { 1366 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1367 break; 1368 } 1369 1370 get += 2; 1371 if ( get == ch->ch_ibuf_end ) 1372 get = ch->ch_ibuf; 1373 1374 ch->ch_ibuf_rd = get; 1375 } 1376 1377 /* 1378 * Is the transmitter idle and in need of attention? 1379 */ 1380 if ( ch->ch_tx_done ) { 1381 ch->ch_tx_done = 0; 1382 1383 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1384 clmpcc_channel_cmd(sc, ch->ch_car, 1385 CLMPCC_CCR_T0_INIT | 1386 CLMPCC_CCR_T0_RX_EN | 1387 CLMPCC_CCR_T0_TX_EN); 1388 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1389 1390 /* 1391 * Allow time for the channel to initialise. 1392 * (Empirically derived duration; there must 1393 * be another way to determine the command 1394 * has completed without busy-waiting...) 1395 */ 1396 delay(800); 1397 1398 /* 1399 * Update the tty layer's idea of the carrier 1400 * bit, in case we changed CLOCAL or MDMBUF. 1401 * We don't hang up here; we only do that by 1402 * explicit request. 1403 */ 1404 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1405 (*tp->t_linesw->l_modem)(tp, reg != 0); 1406 } 1407 1408 CLR(tp->t_state, TS_BUSY); 1409 if ( ISSET(tp->t_state, TS_FLUSH) ) 1410 CLR(tp->t_state, TS_FLUSH); 1411 else 1412 ndflush(&tp->t_outq, 1413 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1414 1415 (*tp->t_linesw->l_start)(tp); 1416 } 1417 } 1418 } 1419 1420 1421 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1422 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1423 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1424 /* 1425 * Following are all routines needed for a cd240x channel to act as console 1426 */ 1427 int 1428 clmpcc_cnattach(struct clmpcc_softc *sc, int chan, int rate) 1429 { 1430 cons_sc = sc; 1431 cons_chan = chan; 1432 cons_rate = rate; 1433 1434 return (clmpcc_init(sc)); 1435 } 1436 1437 /* 1438 * The following functions are polled getc and putc routines, for console use. 1439 */ 1440 static int 1441 clmpcc_common_getc(struct clmpcc_softc *sc, int chan) 1442 { 1443 u_char old_chan; 1444 u_char old_ier; 1445 u_char ch, rir, risr; 1446 int s; 1447 1448 s = splhigh(); 1449 1450 /* Save the currently active channel */ 1451 old_chan = clmpcc_select_channel(sc, chan); 1452 1453 /* 1454 * We have to put the channel into RX interrupt mode before 1455 * trying to read the Rx data register. So save the previous 1456 * interrupt mode. 1457 */ 1458 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1459 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1460 1461 /* Loop until we get a character */ 1462 for (;;) { 1463 /* 1464 * The REN bit will be set in the Receive Interrupt Register 1465 * when the CD240x has a character to process. Remember, 1466 * the RACT bit won't be set until we generate an interrupt 1467 * acknowledge cycle via the MD front-end. 1468 */ 1469 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1470 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1471 continue; 1472 1473 /* Acknowledge the request */ 1474 if ( sc->sc_iackhook ) 1475 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1476 1477 /* 1478 * Determine if the interrupt is for the required channel 1479 * and if valid data is available. 1480 */ 1481 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1482 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1483 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1484 risr != 0 ) { 1485 /* Rx error, or BREAK */ 1486 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1487 CLMPCC_REOIR_NO_TRANS); 1488 } else { 1489 /* Dummy read of the FIFO count register */ 1490 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1491 1492 /* Fetch the received character */ 1493 ch = clmpcc_rd_rxdata(sc); 1494 1495 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1496 break; 1497 } 1498 } 1499 1500 /* Restore the original IER and CAR register contents */ 1501 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1502 clmpcc_select_channel(sc, old_chan); 1503 1504 splx(s); 1505 return ch; 1506 } 1507 1508 1509 static void 1510 clmpcc_common_putc(struct clmpcc_softc *sc, int chan, int c) 1511 { 1512 u_char old_chan; 1513 int s = splhigh(); 1514 1515 /* Save the currently active channel */ 1516 old_chan = clmpcc_select_channel(sc, chan); 1517 1518 /* 1519 * Since we can only access the Tx Data register from within 1520 * the interrupt handler, the easiest way to get console data 1521 * onto the wire is using one of the Special Transmit Character 1522 * registers. 1523 */ 1524 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1525 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1526 CLMPCC_STCR_SND_SPC); 1527 1528 /* Wait until the "Send Special Character" command is accepted */ 1529 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1530 ; 1531 1532 /* Restore the previous channel selected */ 1533 clmpcc_select_channel(sc, old_chan); 1534 1535 splx(s); 1536 } 1537 1538 int 1539 clmpcccngetc(dev_t dev) 1540 { 1541 return clmpcc_common_getc(cons_sc, cons_chan); 1542 } 1543 1544 /* 1545 * Console kernel output character routine. 1546 */ 1547 void 1548 clmpcccnputc(dev_t dev, int c) 1549 { 1550 if ( c == '\n' ) 1551 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1552 1553 clmpcc_common_putc(cons_sc, cons_chan, c); 1554 } 1555