1 /* $NetBSD: clmpcc.c,v 1.36 2007/11/19 18:51:47 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.36 2007/11/19 18:51:47 ad Exp $"); 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/ioctl.h> 51 #include <sys/select.h> 52 #include <sys/tty.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/conf.h> 56 #include <sys/file.h> 57 #include <sys/uio.h> 58 #include <sys/kernel.h> 59 #include <sys/syslog.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/kauth.h> 63 #include <sys/intr.h> 64 65 #include <sys/bus.h> 66 #include <machine/param.h> 67 68 #include <dev/ic/clmpccreg.h> 69 #include <dev/ic/clmpccvar.h> 70 #include <dev/cons.h> 71 72 73 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 74 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 75 #endif 76 77 78 static int clmpcc_init(struct clmpcc_softc *sc); 79 static void clmpcc_shutdown(struct clmpcc_chan *); 80 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *); 81 static int clmpcc_param(struct tty *, struct termios *); 82 static void clmpcc_set_params(struct clmpcc_chan *); 83 static void clmpcc_start(struct tty *); 84 static int clmpcc_modem_control(struct clmpcc_chan *, int, int); 85 86 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 87 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 88 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 89 90 /* 91 * These should be in a header file somewhere... 92 */ 93 #define ISCLR(v, f) (((v) & (f)) == 0) 94 95 extern struct cfdriver clmpcc_cd; 96 97 dev_type_open(clmpccopen); 98 dev_type_close(clmpccclose); 99 dev_type_read(clmpccread); 100 dev_type_write(clmpccwrite); 101 dev_type_ioctl(clmpccioctl); 102 dev_type_stop(clmpccstop); 103 dev_type_tty(clmpcctty); 104 dev_type_poll(clmpccpoll); 105 106 const struct cdevsw clmpcc_cdevsw = { 107 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl, 108 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY 109 }; 110 111 /* 112 * Make this an option variable one can patch. 113 */ 114 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 115 116 117 /* 118 * Things needed when the device is used as a console 119 */ 120 static struct clmpcc_softc *cons_sc = NULL; 121 static int cons_chan; 122 static int cons_rate; 123 124 static int clmpcc_common_getc(struct clmpcc_softc *, int); 125 static void clmpcc_common_putc(struct clmpcc_softc *, int, int); 126 int clmpcccngetc(dev_t); 127 void clmpcccnputc(dev_t, int); 128 129 130 /* 131 * Convenience functions, inlined for speed 132 */ 133 #define integrate static inline 134 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int); 135 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int); 136 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int); 137 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int); 138 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *, 139 u_int); 140 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int); 141 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int); 142 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *); 143 144 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 145 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 146 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 147 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 148 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 149 150 151 integrate u_int8_t 152 clmpcc_rdreg(sc, offset) 153 struct clmpcc_softc *sc; 154 u_int offset; 155 { 156 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 157 offset ^= sc->sc_byteswap; 158 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 159 offset ^= CLMPCC_BYTESWAP_HIGH; 160 #endif 161 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 162 } 163 164 integrate void 165 clmpcc_wrreg(sc, offset, val) 166 struct clmpcc_softc *sc; 167 u_int offset; 168 u_int val; 169 { 170 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 171 offset ^= sc->sc_byteswap; 172 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 173 offset ^= CLMPCC_BYTESWAP_HIGH; 174 #endif 175 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 176 } 177 178 integrate u_int8_t 179 clmpcc_rdreg_odd(sc, offset) 180 struct clmpcc_softc *sc; 181 u_int offset; 182 { 183 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 184 offset ^= (sc->sc_byteswap & 2); 185 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 186 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 187 #endif 188 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 189 } 190 191 integrate void 192 clmpcc_wrreg_odd(sc, offset, val) 193 struct clmpcc_softc *sc; 194 u_int offset; 195 u_int val; 196 { 197 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 198 offset ^= (sc->sc_byteswap & 2); 199 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 200 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 201 #endif 202 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 203 } 204 205 integrate void 206 clmpcc_wrtx_multi(sc, buff, count) 207 struct clmpcc_softc *sc; 208 u_int8_t *buff; 209 u_int count; 210 { 211 u_int offset = CLMPCC_REG_TDR; 212 213 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 214 offset ^= (sc->sc_byteswap & 2); 215 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 216 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 217 #endif 218 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 219 } 220 221 integrate u_int8_t 222 clmpcc_select_channel(sc, new_chan) 223 struct clmpcc_softc *sc; 224 u_int new_chan; 225 { 226 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 227 228 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 229 230 return old_chan; 231 } 232 233 integrate void 234 clmpcc_channel_cmd(sc, chan, cmd) 235 struct clmpcc_softc *sc; 236 int chan; 237 int cmd; 238 { 239 int i; 240 241 for (i = 5000; i; i--) { 242 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 243 break; 244 delay(1); 245 } 246 247 if ( i == 0 ) 248 printf("%s: channel %d command timeout (idle)\n", 249 sc->sc_dev.dv_xname, chan); 250 251 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 252 } 253 254 integrate void 255 clmpcc_enable_transmitter(ch) 256 struct clmpcc_chan *ch; 257 { 258 u_int old; 259 int s; 260 261 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 262 263 s = splserial(); 264 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 265 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 266 SET(ch->ch_tty->t_state, TS_BUSY); 267 splx(s); 268 269 clmpcc_select_channel(ch->ch_sc, old); 270 } 271 272 static int 273 clmpcc_speed(sc, speed, cor, bpr) 274 struct clmpcc_softc *sc; 275 speed_t speed; 276 int *cor, *bpr; 277 { 278 int c, co, br; 279 280 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 281 br = ((sc->sc_clk / c) / speed) - 1; 282 if ( br < 0x100 ) { 283 *cor = co; 284 *bpr = br; 285 return 0; 286 } 287 } 288 289 return -1; 290 } 291 292 void 293 clmpcc_attach(sc) 294 struct clmpcc_softc *sc; 295 { 296 struct clmpcc_chan *ch; 297 struct tty *tp; 298 int chan; 299 300 if ( cons_sc != NULL && 301 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 302 cons_sc = sc; 303 304 /* Initialise the chip */ 305 clmpcc_init(sc); 306 307 printf(": Cirrus Logic CD240%c Serial Controller\n", 308 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 309 310 sc->sc_softintr_cookie = 311 softint_establish(SOFTINT_SERIAL, clmpcc_softintr, sc); 312 if (sc->sc_softintr_cookie == NULL) 313 panic("clmpcc_attach: softintr_establish"); 314 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 315 316 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 317 ch = &sc->sc_chans[chan]; 318 319 ch->ch_sc = sc; 320 ch->ch_car = chan; 321 322 tp = ttymalloc(); 323 tp->t_oproc = clmpcc_start; 324 tp->t_param = clmpcc_param; 325 326 ch->ch_tty = tp; 327 328 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 329 if ( ch->ch_ibuf == NULL ) { 330 printf("%s(%d): unable to allocate ring buffer\n", 331 sc->sc_dev.dv_xname, chan); 332 return; 333 } 334 335 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 336 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 337 338 tty_attach(tp); 339 } 340 341 printf("%s: %d channels available", sc->sc_dev.dv_xname, 342 CLMPCC_NUM_CHANS); 343 if ( cons_sc == sc ) { 344 printf(", console on channel %d.\n", cons_chan); 345 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 346 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 347 } else 348 printf(".\n"); 349 } 350 351 static int 352 clmpcc_init(sc) 353 struct clmpcc_softc *sc; 354 { 355 u_int tcor, tbpr; 356 u_int rcor, rbpr; 357 u_int msvr_rts, msvr_dtr; 358 u_int ccr; 359 int is_console; 360 int i; 361 362 /* 363 * All we're really concerned about here is putting the chip 364 * into a quiescent state so that it won't do anything until 365 * clmpccopen() is called. (Except the console channel.) 366 */ 367 368 /* 369 * If the chip is acting as console, set all channels to the supplied 370 * console baud rate. Otherwise, plump for 9600. 371 */ 372 if ( cons_sc && 373 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 374 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 375 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 376 is_console = 1; 377 } else { 378 clmpcc_speed(sc, 9600, &tcor, &tbpr); 379 clmpcc_speed(sc, 9600, &rcor, &rbpr); 380 is_console = 0; 381 } 382 383 /* Allow any pending output to be sent */ 384 delay(10000); 385 386 /* Send the Reset All command to channel 0 (resets all channels!) */ 387 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 388 389 delay(1000); 390 391 /* 392 * The chip will set it's firmware revision register to a non-zero 393 * value to indicate completion of reset. 394 */ 395 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 396 delay(1); 397 398 if ( i == 0 ) { 399 /* 400 * Watch out... If this chip is console, the message 401 * probably won't be sent since we just reset it! 402 */ 403 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 404 return -1; 405 } 406 407 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 408 clmpcc_select_channel(sc, i); 409 410 /* All interrupts are disabled to begin with */ 411 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 412 413 /* Make sure the channel interrupts on the correct vectors */ 414 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 415 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 416 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 417 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 418 419 /* Receive timer prescaler set to 1ms */ 420 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 421 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 422 423 /* We support Async mode only */ 424 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 425 426 /* Set the required baud rate */ 427 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 428 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 429 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 430 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 431 432 /* Always default to 8N1 (XXX what about console?) */ 433 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 434 CLMPCC_COR1_NO_PARITY | 435 CLMPCC_COR1_IGNORE_PAR); 436 437 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 438 439 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 440 441 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 442 CLMPCC_COR4_CDzd | 443 CLMPCC_COR4_CTSzd); 444 445 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 446 CLMPCC_COR5_CDod | 447 CLMPCC_COR5_CTSod | 448 CLMPCC_COR5_FLOW_NORM); 449 450 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 451 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 452 453 /* Set the receive FIFO timeout */ 454 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 455 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 456 457 /* At this point, we set up the console differently */ 458 if ( is_console && i == cons_chan ) { 459 msvr_rts = CLMPCC_MSVR_RTS; 460 msvr_dtr = CLMPCC_MSVR_DTR; 461 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 462 } else { 463 msvr_rts = 0; 464 msvr_dtr = 0; 465 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 466 } 467 468 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 469 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 470 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 471 delay(100); 472 } 473 474 return 0; 475 } 476 477 static void 478 clmpcc_shutdown(ch) 479 struct clmpcc_chan *ch; 480 { 481 int oldch; 482 483 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 484 485 /* Turn off interrupts. */ 486 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 487 488 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 489 /* Disable the transmitter and receiver */ 490 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 491 CLMPCC_CCR_T0_TX_DIS); 492 493 /* Drop RTS and DTR */ 494 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 495 } 496 497 clmpcc_select_channel(ch->ch_sc, oldch); 498 } 499 500 int 501 clmpccopen(dev, flag, mode, l) 502 dev_t dev; 503 int flag, mode; 504 struct lwp *l; 505 { 506 struct clmpcc_softc *sc; 507 struct clmpcc_chan *ch; 508 struct tty *tp; 509 int oldch; 510 int error; 511 512 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 513 if (sc == NULL) 514 return (ENXIO); 515 516 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 517 518 tp = ch->ch_tty; 519 520 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 521 return EBUSY; 522 523 /* 524 * Do the following iff this is a first open. 525 */ 526 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 527 528 ttychars(tp); 529 530 tp->t_dev = dev; 531 tp->t_iflag = TTYDEF_IFLAG; 532 tp->t_oflag = TTYDEF_OFLAG; 533 tp->t_lflag = TTYDEF_LFLAG; 534 tp->t_cflag = TTYDEF_CFLAG; 535 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 536 537 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 538 SET(tp->t_cflag, CLOCAL); 539 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 540 SET(tp->t_cflag, CRTSCTS); 541 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 542 SET(tp->t_cflag, MDMBUF); 543 544 /* 545 * Override some settings if the channel is being 546 * used as the console. 547 */ 548 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 549 tp->t_ospeed = tp->t_ispeed = cons_rate; 550 SET(tp->t_cflag, CLOCAL); 551 CLR(tp->t_cflag, CRTSCTS); 552 CLR(tp->t_cflag, HUPCL); 553 } 554 555 ch->ch_control = 0; 556 557 clmpcc_param(tp, &tp->t_termios); 558 ttsetwater(tp); 559 560 /* Clear the input ring */ 561 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 562 563 /* Select the channel */ 564 oldch = clmpcc_select_channel(sc, ch->ch_car); 565 566 /* Reset it */ 567 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 568 CLMPCC_CCR_T0_RX_EN | 569 CLMPCC_CCR_T0_TX_EN); 570 571 /* Enable receiver and modem change interrupts. */ 572 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 573 CLMPCC_IER_RET | 574 CLMPCC_IER_RX_FIFO); 575 576 /* Raise RTS and DTR */ 577 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 578 579 clmpcc_select_channel(sc, oldch); 580 } 581 582 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 583 if (error) 584 goto bad; 585 586 error = (*tp->t_linesw->l_open)(dev, tp); 587 if (error) 588 goto bad; 589 590 return 0; 591 592 bad: 593 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 594 /* 595 * We failed to open the device, and nobody else had it opened. 596 * Clean up the state as appropriate. 597 */ 598 clmpcc_shutdown(ch); 599 } 600 601 return error; 602 } 603 604 int 605 clmpccclose(dev, flag, mode, l) 606 dev_t dev; 607 int flag, mode; 608 struct lwp *l; 609 { 610 struct clmpcc_softc *sc = 611 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 612 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 613 struct tty *tp = ch->ch_tty; 614 int s; 615 616 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 617 return 0; 618 619 (*tp->t_linesw->l_close)(tp, flag); 620 621 s = spltty(); 622 623 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 624 /* 625 * Although we got a last close, the device may still be in 626 * use; e.g. if this was the dialout node, and there are still 627 * processes waiting for carrier on the non-dialout node. 628 */ 629 clmpcc_shutdown(ch); 630 } 631 632 ttyclose(tp); 633 634 splx(s); 635 636 return 0; 637 } 638 639 int 640 clmpccread(dev, uio, flag) 641 dev_t dev; 642 struct uio *uio; 643 int flag; 644 { 645 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 646 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 647 648 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 649 } 650 651 int 652 clmpccwrite(dev, uio, flag) 653 dev_t dev; 654 struct uio *uio; 655 int flag; 656 { 657 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 658 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 659 660 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 661 } 662 663 int 664 clmpccpoll(dev, events, l) 665 dev_t dev; 666 int events; 667 struct lwp *l; 668 { 669 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 670 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 671 672 return ((*tp->t_linesw->l_poll)(tp, events, l)); 673 } 674 675 struct tty * 676 clmpcctty(dev) 677 dev_t dev; 678 { 679 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 680 681 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 682 } 683 684 int 685 clmpccioctl(dev, cmd, data, flag, l) 686 dev_t dev; 687 u_long cmd; 688 void *data; 689 int flag; 690 struct lwp *l; 691 { 692 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 693 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 694 struct tty *tp = ch->ch_tty; 695 int error; 696 697 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 698 if (error != EPASSTHROUGH) 699 return error; 700 701 error = ttioctl(tp, cmd, data, flag, l); 702 if (error != EPASSTHROUGH) 703 return error; 704 705 error = 0; 706 707 switch (cmd) { 708 case TIOCSBRK: 709 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 710 clmpcc_enable_transmitter(ch); 711 break; 712 713 case TIOCCBRK: 714 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 715 clmpcc_enable_transmitter(ch); 716 break; 717 718 case TIOCSDTR: 719 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 720 break; 721 722 case TIOCCDTR: 723 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 724 break; 725 726 case TIOCMSET: 727 clmpcc_modem_control(ch, *((int *)data), DMSET); 728 break; 729 730 case TIOCMBIS: 731 clmpcc_modem_control(ch, *((int *)data), DMBIS); 732 break; 733 734 case TIOCMBIC: 735 clmpcc_modem_control(ch, *((int *)data), DMBIC); 736 break; 737 738 case TIOCMGET: 739 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 740 break; 741 742 case TIOCGFLAGS: 743 *((int *)data) = ch->ch_openflags; 744 break; 745 746 case TIOCSFLAGS: 747 error = kauth_authorize_device_tty(l->l_cred, 748 KAUTH_DEVICE_TTY_PRIVSET, tp); 749 if ( error ) 750 break; 751 ch->ch_openflags = *((int *)data) & 752 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 753 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 754 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 755 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 756 break; 757 758 default: 759 error = EPASSTHROUGH; 760 break; 761 } 762 763 return error; 764 } 765 766 int 767 clmpcc_modem_control(ch, bits, howto) 768 struct clmpcc_chan *ch; 769 int bits; 770 int howto; 771 { 772 struct clmpcc_softc *sc = ch->ch_sc; 773 struct tty *tp = ch->ch_tty; 774 int oldch; 775 int msvr; 776 int rbits = 0; 777 778 oldch = clmpcc_select_channel(sc, ch->ch_car); 779 780 switch ( howto ) { 781 case DMGET: 782 msvr = clmpcc_rd_msvr(sc); 783 784 if ( sc->sc_swaprtsdtr ) { 785 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 786 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 787 } else { 788 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 789 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 790 } 791 792 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 793 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 794 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 795 break; 796 797 case DMSET: 798 if ( sc->sc_swaprtsdtr ) { 799 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 800 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 801 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 802 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 803 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 804 } else { 805 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 806 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 807 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 808 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 809 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 810 } 811 break; 812 813 case DMBIS: 814 if ( sc->sc_swaprtsdtr ) { 815 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 816 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 817 if ( ISSET(bits, TIOCM_DTR) ) 818 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 819 } else { 820 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 821 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 822 if ( ISSET(bits, TIOCM_DTR) ) 823 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 824 } 825 break; 826 827 case DMBIC: 828 if ( sc->sc_swaprtsdtr ) { 829 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 830 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 831 if ( ISCLR(bits, TIOCM_DTR) ) 832 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 833 } else { 834 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 835 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 836 if ( ISCLR(bits, TIOCM_DTR) ) 837 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 838 } 839 break; 840 } 841 842 clmpcc_select_channel(sc, oldch); 843 844 return rbits; 845 } 846 847 static int 848 clmpcc_param(tp, t) 849 struct tty *tp; 850 struct termios *t; 851 { 852 struct clmpcc_softc *sc = 853 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 854 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 855 u_char cor; 856 u_char oldch; 857 int oclk, obpr; 858 int iclk, ibpr; 859 int s; 860 861 /* Check requested parameters. */ 862 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 863 return EINVAL; 864 865 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 866 return EINVAL; 867 868 /* 869 * For the console, always force CLOCAL and !HUPCL, so that the port 870 * is always active. 871 */ 872 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 873 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 874 SET(t->c_cflag, CLOCAL); 875 CLR(t->c_cflag, HUPCL); 876 } 877 878 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 879 880 /* If ospeed it zero, hangup the line */ 881 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 882 883 if ( t->c_ospeed ) { 884 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 885 ch->ch_tbpr = obpr; 886 } else { 887 ch->ch_tcor = 0; 888 ch->ch_tbpr = 0; 889 } 890 891 if ( t->c_ispeed ) { 892 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 893 ch->ch_rbpr = ibpr; 894 } else { 895 ch->ch_rcor = 0; 896 ch->ch_rbpr = 0; 897 } 898 899 /* Work out value to use for COR1 */ 900 cor = 0; 901 if ( ISSET(t->c_cflag, PARENB) ) { 902 cor |= CLMPCC_COR1_NORM_PARITY; 903 if ( ISSET(t->c_cflag, PARODD) ) 904 cor |= CLMPCC_COR1_ODD_PARITY; 905 } 906 907 if ( ISCLR(t->c_cflag, INPCK) ) 908 cor |= CLMPCC_COR1_IGNORE_PAR; 909 910 switch ( t->c_cflag & CSIZE ) { 911 case CS5: 912 cor |= CLMPCC_COR1_CHAR_5BITS; 913 break; 914 915 case CS6: 916 cor |= CLMPCC_COR1_CHAR_6BITS; 917 break; 918 919 case CS7: 920 cor |= CLMPCC_COR1_CHAR_7BITS; 921 break; 922 923 case CS8: 924 cor |= CLMPCC_COR1_CHAR_8BITS; 925 break; 926 } 927 928 ch->ch_cor1 = cor; 929 930 /* 931 * The only interesting bit in COR2 is 'CTS Automatic Enable' 932 * when hardware flow control is in effect. 933 */ 934 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 935 936 /* COR3 needs to be set to the number of stop bits... */ 937 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 938 CLMPCC_COR3_STOP_1; 939 940 /* 941 * COR4 contains the FIFO threshold setting. 942 * We adjust the threshold depending on the input speed... 943 */ 944 if ( t->c_ispeed <= 1200 ) 945 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 946 else if ( t->c_ispeed <= 19200 ) 947 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 948 else 949 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 950 951 /* 952 * If chip is used with CTS and DTR swapped, we can enable 953 * automatic hardware flow control. 954 */ 955 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 956 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 957 else 958 ch->ch_cor5 = 0; 959 960 s = splserial(); 961 oldch = clmpcc_select_channel(sc, ch->ch_car); 962 963 /* 964 * COR2 needs to be set immediately otherwise we might never get 965 * a Tx EMPTY interrupt to change the other parameters. 966 */ 967 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 968 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 969 970 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 971 clmpcc_set_params(ch); 972 else 973 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 974 975 clmpcc_select_channel(sc, oldch); 976 977 splx(s); 978 979 return 0; 980 } 981 982 static void 983 clmpcc_set_params(ch) 984 struct clmpcc_chan *ch; 985 { 986 struct clmpcc_softc *sc = ch->ch_sc; 987 u_char r1; 988 u_char r2; 989 990 if ( ch->ch_tcor || ch->ch_tbpr ) { 991 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 992 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 993 /* Only write Tx rate if it really has changed */ 994 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 995 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 996 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 997 } 998 } 999 1000 if ( ch->ch_rcor || ch->ch_rbpr ) { 1001 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 1002 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 1003 /* Only write Rx rate if it really has changed */ 1004 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 1005 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 1006 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1007 } 1008 } 1009 1010 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1011 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1012 /* Any change to COR1 requires an INIT command */ 1013 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1014 } 1015 1016 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1017 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1018 1019 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1020 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1021 /* 1022 * Note: If the FIFO has changed, we always set it to 1023 * zero here and disable the Receive Timeout interrupt. 1024 * It's up to the Rx Interrupt handler to pick the 1025 * appropriate moment to write the new FIFO length. 1026 */ 1027 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1028 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1029 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1030 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1031 } 1032 1033 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1034 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1035 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1036 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1037 } 1038 } 1039 1040 static void 1041 clmpcc_start(tp) 1042 struct tty *tp; 1043 { 1044 struct clmpcc_softc *sc = 1045 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1046 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1047 u_int oldch; 1048 int s; 1049 1050 s = spltty(); 1051 1052 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1053 ttypull(tp); 1054 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1055 CLMPCC_FLG_END_BREAK) || 1056 tp->t_outq.c_cc > 0 ) { 1057 1058 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1059 CLMPCC_FLG_END_BREAK) ) { 1060 ch->ch_obuf_addr = tp->t_outq.c_cf; 1061 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1062 } 1063 1064 /* Enable TX empty interrupts */ 1065 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1066 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1067 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1068 CLMPCC_IER_TX_EMPTY); 1069 clmpcc_select_channel(ch->ch_sc, oldch); 1070 SET(tp->t_state, TS_BUSY); 1071 } 1072 } 1073 1074 splx(s); 1075 } 1076 1077 /* 1078 * Stop output on a line. 1079 */ 1080 void 1081 clmpccstop(tp, flag) 1082 struct tty *tp; 1083 int flag; 1084 { 1085 struct clmpcc_softc *sc = 1086 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1087 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1088 int s; 1089 1090 s = splserial(); 1091 1092 if ( ISSET(tp->t_state, TS_BUSY) ) { 1093 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1094 SET(tp->t_state, TS_FLUSH); 1095 ch->ch_obuf_size = 0; 1096 } 1097 splx(s); 1098 } 1099 1100 /* 1101 * RX interrupt routine 1102 */ 1103 int 1104 clmpcc_rxintr(arg) 1105 void *arg; 1106 { 1107 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1108 struct clmpcc_chan *ch; 1109 u_int8_t *put, *end, rxd; 1110 u_char errstat; 1111 u_char fc, tc; 1112 u_char risr; 1113 u_char rir; 1114 #ifdef DDB 1115 int saw_break = 0; 1116 #endif 1117 1118 /* Receive interrupt active? */ 1119 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1120 1121 /* 1122 * If we're using auto-vectored interrupts, we have to 1123 * verify if the chip is generating the interrupt. 1124 */ 1125 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1126 return 0; 1127 1128 /* Get pointer to interrupting channel's data structure */ 1129 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1130 1131 /* Get the interrupt status register */ 1132 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1133 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1134 u_char reg; 1135 /* 1136 * Set the FIFO threshold to zero, and disable 1137 * further receive timeout interrupts. 1138 */ 1139 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1140 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1141 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1142 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1143 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1144 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1145 return 1; 1146 } 1147 1148 /* How many bytes are waiting in the FIFO? */ 1149 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1150 1151 #ifdef DDB 1152 /* 1153 * Allow BREAK on the console to drop to the debugger. 1154 */ 1155 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1156 risr & CLMPCC_RISR_BREAK ) { 1157 saw_break = 1; 1158 } 1159 #endif 1160 1161 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1162 /* Just get rid of the data */ 1163 while ( fc-- ) 1164 (void) clmpcc_rd_rxdata(sc); 1165 goto rx_done; 1166 } 1167 1168 put = ch->ch_ibuf_wr; 1169 end = ch->ch_ibuf_end; 1170 1171 /* 1172 * Note: The chip is completely hosed WRT these error 1173 * conditions; there seems to be no way to associate 1174 * the error with the correct character in the FIFO. 1175 * We compromise by tagging the first character we read 1176 * with the error. Not perfect, but there's no other way. 1177 */ 1178 errstat = 0; 1179 if ( risr & CLMPCC_RISR_PARITY ) 1180 errstat |= TTY_PE; 1181 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1182 errstat |= TTY_FE; 1183 1184 /* 1185 * As long as there are characters in the FIFO, and we 1186 * have space for them... 1187 */ 1188 while ( fc > 0 ) { 1189 1190 *put++ = rxd = clmpcc_rd_rxdata(sc); 1191 *put++ = errstat; 1192 1193 if ( put >= end ) 1194 put = ch->ch_ibuf; 1195 1196 if ( put == ch->ch_ibuf_rd ) { 1197 put -= 2; 1198 if ( put < ch->ch_ibuf ) 1199 put = end - 2; 1200 } 1201 1202 errstat = 0; 1203 fc--; 1204 } 1205 1206 ch->ch_ibuf_wr = put; 1207 1208 #if 0 1209 if ( sc->sc_swaprtsdtr == 0 && 1210 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1211 /* 1212 * If RTS/DTR are not physically swapped, we have to 1213 * do hardware flow control manually 1214 */ 1215 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1216 } 1217 #endif 1218 1219 rx_done: 1220 if ( fc != tc ) { 1221 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1222 u_char reg; 1223 /* 1224 * Set the FIFO threshold to the preset value, 1225 * and enable receive timeout interrupts. 1226 */ 1227 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1228 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1229 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1230 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1231 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1232 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1233 } 1234 1235 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1236 softint_schedule(sc->sc_softintr_cookie); 1237 } else 1238 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1239 1240 #ifdef DDB 1241 /* 1242 * Only =after= we write REOIR is it safe to drop to the debugger. 1243 */ 1244 if ( saw_break ) 1245 Debugger(); 1246 #endif 1247 1248 return 1; 1249 } 1250 1251 /* 1252 * Tx interrupt routine 1253 */ 1254 int 1255 clmpcc_txintr(arg) 1256 void *arg; 1257 { 1258 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1259 struct clmpcc_chan *ch; 1260 struct tty *tp; 1261 u_char ftc, oftc; 1262 u_char tir, teoir; 1263 int etcmode = 0; 1264 1265 /* Tx interrupt active? */ 1266 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1267 1268 /* 1269 * If we're using auto-vectored interrupts, we have to 1270 * verify if the chip is generating the interrupt. 1271 */ 1272 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1273 return 0; 1274 1275 /* Get pointer to interrupting channel's data structure */ 1276 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1277 tp = ch->ch_tty; 1278 1279 /* Dummy read of the interrupt status register */ 1280 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1281 1282 /* Make sure embedded transmit commands are disabled */ 1283 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1284 1285 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1286 1287 /* Handle a delayed parameter change */ 1288 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1289 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1290 clmpcc_set_params(ch); 1291 } 1292 1293 if ( ch->ch_obuf_size > 0 ) { 1294 u_int n = min(ch->ch_obuf_size, ftc); 1295 1296 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1297 1298 ftc -= n; 1299 ch->ch_obuf_size -= n; 1300 ch->ch_obuf_addr += n; 1301 1302 } else { 1303 /* 1304 * Check if we should start/stop a break 1305 */ 1306 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1307 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1308 /* Enable embedded transmit commands */ 1309 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1310 ch->ch_cor2 | CLMPCC_COR2_ETC); 1311 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1312 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1313 ftc -= 2; 1314 etcmode = 1; 1315 } 1316 1317 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1318 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1319 /* Enable embedded transmit commands */ 1320 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1321 ch->ch_cor2 | CLMPCC_COR2_ETC); 1322 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1323 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1324 ftc -= 2; 1325 etcmode = 1; 1326 } 1327 } 1328 1329 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1330 1331 if ( ftc != oftc ) { 1332 /* 1333 * Enable/disable the Tx FIFO threshold interrupt 1334 * according to how much data is in the FIFO. 1335 * However, always disable the FIFO threshold if 1336 * we've left the channel in 'Embedded Transmit 1337 * Command' mode. 1338 */ 1339 if ( etcmode || ftc >= ch->ch_cor4 ) 1340 tir &= ~CLMPCC_IER_TX_FIFO; 1341 else 1342 tir |= CLMPCC_IER_TX_FIFO; 1343 teoir = 0; 1344 } else { 1345 /* 1346 * No data was sent. 1347 * Disable transmit interrupt. 1348 */ 1349 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1350 teoir = CLMPCC_TEOIR_NO_TRANS; 1351 1352 /* 1353 * Request Tx processing in the soft interrupt handler 1354 */ 1355 ch->ch_tx_done = 1; 1356 softint_schedule(sc->sc_softintr_cookie); 1357 } 1358 1359 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1360 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1361 1362 return 1; 1363 } 1364 1365 /* 1366 * Modem change interrupt routine 1367 */ 1368 int 1369 clmpcc_mdintr(arg) 1370 void *arg; 1371 { 1372 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1373 u_char mir; 1374 1375 /* Modem status interrupt active? */ 1376 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1377 1378 /* 1379 * If we're using auto-vectored interrupts, we have to 1380 * verify if the chip is generating the interrupt. 1381 */ 1382 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1383 return 0; 1384 1385 /* Dummy read of the interrupt status register */ 1386 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1387 1388 /* Retrieve current status of modem lines. */ 1389 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1390 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1391 1392 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1393 softint_schedule(sc->sc_softintr_cookie); 1394 1395 return 1; 1396 } 1397 1398 void 1399 clmpcc_softintr(arg) 1400 void *arg; 1401 { 1402 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1403 struct clmpcc_chan *ch; 1404 struct tty *tp; 1405 int (*rint)(int, struct tty *); 1406 u_char *get; 1407 u_char reg; 1408 u_int c; 1409 int chan; 1410 1411 /* Handle Modem state changes too... */ 1412 1413 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1414 ch = &sc->sc_chans[chan]; 1415 tp = ch->ch_tty; 1416 1417 get = ch->ch_ibuf_rd; 1418 rint = tp->t_linesw->l_rint; 1419 1420 /* Squirt buffered incoming data into the tty layer */ 1421 while ( get != ch->ch_ibuf_wr ) { 1422 c = get[0]; 1423 c |= ((u_int)get[1]) << 8; 1424 if ( (rint)(c, tp) == -1 ) { 1425 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1426 break; 1427 } 1428 1429 get += 2; 1430 if ( get == ch->ch_ibuf_end ) 1431 get = ch->ch_ibuf; 1432 1433 ch->ch_ibuf_rd = get; 1434 } 1435 1436 /* 1437 * Is the transmitter idle and in need of attention? 1438 */ 1439 if ( ch->ch_tx_done ) { 1440 ch->ch_tx_done = 0; 1441 1442 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1443 clmpcc_channel_cmd(sc, ch->ch_car, 1444 CLMPCC_CCR_T0_INIT | 1445 CLMPCC_CCR_T0_RX_EN | 1446 CLMPCC_CCR_T0_TX_EN); 1447 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1448 1449 /* 1450 * Allow time for the channel to initialise. 1451 * (Empirically derived duration; there must 1452 * be another way to determine the command 1453 * has completed without busy-waiting...) 1454 */ 1455 delay(800); 1456 1457 /* 1458 * Update the tty layer's idea of the carrier 1459 * bit, in case we changed CLOCAL or MDMBUF. 1460 * We don't hang up here; we only do that by 1461 * explicit request. 1462 */ 1463 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1464 (*tp->t_linesw->l_modem)(tp, reg != 0); 1465 } 1466 1467 CLR(tp->t_state, TS_BUSY); 1468 if ( ISSET(tp->t_state, TS_FLUSH) ) 1469 CLR(tp->t_state, TS_FLUSH); 1470 else 1471 ndflush(&tp->t_outq, 1472 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1473 1474 (*tp->t_linesw->l_start)(tp); 1475 } 1476 } 1477 } 1478 1479 1480 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1481 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1482 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1483 /* 1484 * Following are all routines needed for a cd240x channel to act as console 1485 */ 1486 int 1487 clmpcc_cnattach(sc, chan, rate) 1488 struct clmpcc_softc *sc; 1489 int chan; 1490 int rate; 1491 { 1492 cons_sc = sc; 1493 cons_chan = chan; 1494 cons_rate = rate; 1495 1496 return (clmpcc_init(sc)); 1497 } 1498 1499 /* 1500 * The following functions are polled getc and putc routines, for console use. 1501 */ 1502 static int 1503 clmpcc_common_getc(sc, chan) 1504 struct clmpcc_softc *sc; 1505 int chan; 1506 { 1507 u_char old_chan; 1508 u_char old_ier; 1509 u_char ch, rir, risr; 1510 int s; 1511 1512 s = splhigh(); 1513 1514 /* Save the currently active channel */ 1515 old_chan = clmpcc_select_channel(sc, chan); 1516 1517 /* 1518 * We have to put the channel into RX interrupt mode before 1519 * trying to read the Rx data register. So save the previous 1520 * interrupt mode. 1521 */ 1522 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1523 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1524 1525 /* Loop until we get a character */ 1526 for (;;) { 1527 /* 1528 * The REN bit will be set in the Receive Interrupt Register 1529 * when the CD240x has a character to process. Remember, 1530 * the RACT bit won't be set until we generate an interrupt 1531 * acknowledge cycle via the MD front-end. 1532 */ 1533 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1534 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1535 continue; 1536 1537 /* Acknowledge the request */ 1538 if ( sc->sc_iackhook ) 1539 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1540 1541 /* 1542 * Determine if the interrupt is for the required channel 1543 * and if valid data is available. 1544 */ 1545 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1546 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1547 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1548 risr != 0 ) { 1549 /* Rx error, or BREAK */ 1550 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1551 CLMPCC_REOIR_NO_TRANS); 1552 } else { 1553 /* Dummy read of the FIFO count register */ 1554 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1555 1556 /* Fetch the received character */ 1557 ch = clmpcc_rd_rxdata(sc); 1558 1559 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1560 break; 1561 } 1562 } 1563 1564 /* Restore the original IER and CAR register contents */ 1565 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1566 clmpcc_select_channel(sc, old_chan); 1567 1568 splx(s); 1569 return ch; 1570 } 1571 1572 1573 static void 1574 clmpcc_common_putc(sc, chan, c) 1575 struct clmpcc_softc *sc; 1576 int chan; 1577 int c; 1578 { 1579 u_char old_chan; 1580 int s = splhigh(); 1581 1582 /* Save the currently active channel */ 1583 old_chan = clmpcc_select_channel(sc, chan); 1584 1585 /* 1586 * Since we can only access the Tx Data register from within 1587 * the interrupt handler, the easiest way to get console data 1588 * onto the wire is using one of the Special Transmit Character 1589 * registers. 1590 */ 1591 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1592 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1593 CLMPCC_STCR_SND_SPC); 1594 1595 /* Wait until the "Send Special Character" command is accepted */ 1596 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1597 ; 1598 1599 /* Restore the previous channel selected */ 1600 clmpcc_select_channel(sc, old_chan); 1601 1602 splx(s); 1603 } 1604 1605 int 1606 clmpcccngetc(dev) 1607 dev_t dev; 1608 { 1609 return clmpcc_common_getc(cons_sc, cons_chan); 1610 } 1611 1612 /* 1613 * Console kernel output character routine. 1614 */ 1615 void 1616 clmpcccnputc(dev, c) 1617 dev_t dev; 1618 int c; 1619 { 1620 if ( c == '\n' ) 1621 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1622 1623 clmpcc_common_putc(cons_sc, cons_chan, c); 1624 } 1625