1 /* $NetBSD: clmpcc.c,v 1.11 2000/07/06 01:47:35 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include "opt_ddb.h" 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/select.h> 50 #include <sys/tty.h> 51 #include <sys/proc.h> 52 #include <sys/user.h> 53 #include <sys/conf.h> 54 #include <sys/file.h> 55 #include <sys/uio.h> 56 #include <sys/kernel.h> 57 #include <sys/syslog.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 61 #include <machine/bus.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/clmpccreg.h> 65 #include <dev/ic/clmpccvar.h> 66 #include <dev/cons.h> 67 68 69 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 70 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 71 #endif 72 73 74 static int clmpcc_init __P((struct clmpcc_softc *sc)); 75 static void clmpcc_shutdown __P((struct clmpcc_chan *)); 76 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t, 77 int *, int *)); 78 static int clmpcc_param __P((struct tty *, struct termios *)); 79 static void clmpcc_set_params __P((struct clmpcc_chan *)); 80 static void clmpcc_start __P((struct tty *)); 81 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int)); 82 83 84 cdev_decl(clmpcc); 85 86 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 87 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 88 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 89 90 /* 91 * These should be in a header file somewhere... 92 */ 93 #define ISSET(v, f) (((v) & (f)) != 0) 94 #define ISCLR(v, f) (((v) & (f)) == 0) 95 #define SET(v, f) (v) |= (f) 96 #define CLR(v, f) (v) &= ~(f) 97 98 99 extern struct cfdriver clmpcc_cd; 100 101 102 /* 103 * Make this an option variable one can patch. 104 */ 105 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 106 107 108 /* 109 * Things needed when the device is used as a console 110 */ 111 static struct clmpcc_softc *cons_sc = NULL; 112 static int cons_chan; 113 static int cons_rate; 114 115 static int clmpcc_common_getc __P((struct clmpcc_softc *, int)); 116 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int)); 117 int clmpcccngetc __P((dev_t)); 118 void clmpcccnputc __P((dev_t, int)); 119 120 121 /* 122 * Convenience functions, inlined for speed 123 */ 124 #define integrate static inline 125 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int)); 126 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int)); 127 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int)); 128 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int)); 129 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *, 130 u_int)); 131 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int)); 132 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int)); 133 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *)); 134 135 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 136 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 137 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 138 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 139 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 140 141 142 integrate u_int8_t 143 clmpcc_rdreg(sc, offset) 144 struct clmpcc_softc *sc; 145 u_int offset; 146 { 147 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 148 offset ^= sc->sc_byteswap; 149 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 150 offset ^= CLMPCC_BYTESWAP_HIGH; 151 #endif 152 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 153 } 154 155 integrate void 156 clmpcc_wrreg(sc, offset, val) 157 struct clmpcc_softc *sc; 158 u_int offset; 159 u_int val; 160 { 161 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 162 offset ^= sc->sc_byteswap; 163 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 164 offset ^= CLMPCC_BYTESWAP_HIGH; 165 #endif 166 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 167 } 168 169 integrate u_int8_t 170 clmpcc_rdreg_odd(sc, offset) 171 struct clmpcc_softc *sc; 172 u_int offset; 173 { 174 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 175 offset ^= (sc->sc_byteswap & 2); 176 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 177 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 178 #endif 179 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 180 } 181 182 integrate void 183 clmpcc_wrreg_odd(sc, offset, val) 184 struct clmpcc_softc *sc; 185 u_int offset; 186 u_int val; 187 { 188 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 189 offset ^= (sc->sc_byteswap & 2); 190 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 191 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 192 #endif 193 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 194 } 195 196 integrate void 197 clmpcc_wrtx_multi(sc, buff, count) 198 struct clmpcc_softc *sc; 199 u_int8_t *buff; 200 u_int count; 201 { 202 u_int offset = CLMPCC_REG_TDR; 203 204 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 205 offset ^= (sc->sc_byteswap & 2); 206 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 207 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 208 #endif 209 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 210 } 211 212 integrate u_int8_t 213 clmpcc_select_channel(sc, new_chan) 214 struct clmpcc_softc *sc; 215 u_int new_chan; 216 { 217 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 218 219 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 220 221 return old_chan; 222 } 223 224 integrate void 225 clmpcc_channel_cmd(sc, chan, cmd) 226 struct clmpcc_softc *sc; 227 int chan; 228 int cmd; 229 { 230 int i; 231 232 for (i = 5000; i; i--) { 233 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 234 break; 235 delay(1); 236 } 237 238 if ( i == 0 ) 239 printf("%s: channel %d command timeout (idle)\n", 240 sc->sc_dev.dv_xname, chan); 241 242 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 243 } 244 245 integrate void 246 clmpcc_enable_transmitter(ch) 247 struct clmpcc_chan *ch; 248 { 249 u_int old; 250 int s; 251 252 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 253 254 s = splserial(); 255 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 256 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 257 SET(ch->ch_tty->t_state, TS_BUSY); 258 splx(s); 259 260 clmpcc_select_channel(ch->ch_sc, old); 261 } 262 263 static int 264 clmpcc_speed(sc, speed, cor, bpr) 265 struct clmpcc_softc *sc; 266 speed_t speed; 267 int *cor, *bpr; 268 { 269 int c, co, br; 270 271 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 272 br = ((sc->sc_clk / c) / speed) - 1; 273 if ( br < 0x100 ) { 274 *cor = co; 275 *bpr = br; 276 return 0; 277 } 278 } 279 280 return -1; 281 } 282 283 void 284 clmpcc_attach(sc) 285 struct clmpcc_softc *sc; 286 { 287 struct clmpcc_chan *ch; 288 struct tty *tp; 289 int chan; 290 291 if ( cons_sc != NULL && 292 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 293 cons_sc = sc; 294 295 /* Initialise the chip */ 296 clmpcc_init(sc); 297 298 printf(": Cirrus Logic CD240%c Serial Controller\n", 299 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 300 301 sc->sc_soft_running = 0; 302 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 303 304 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 305 ch = &sc->sc_chans[chan]; 306 307 ch->ch_sc = sc; 308 ch->ch_car = chan; 309 310 tp = ttymalloc(); 311 tp->t_oproc = clmpcc_start; 312 tp->t_param = clmpcc_param; 313 314 ch->ch_tty = tp; 315 316 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 317 if ( ch->ch_ibuf == NULL ) { 318 printf("%s(%d): unable to allocate ring buffer\n", 319 sc->sc_dev.dv_xname, chan); 320 return; 321 } 322 323 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 324 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 325 326 tty_attach(tp); 327 } 328 329 printf("%s: %d channels available", sc->sc_dev.dv_xname, 330 CLMPCC_NUM_CHANS); 331 if ( cons_sc == sc ) { 332 printf(", console on channel %d.\n", cons_chan); 333 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 334 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 335 } else 336 printf(".\n"); 337 } 338 339 static int 340 clmpcc_init(sc) 341 struct clmpcc_softc *sc; 342 { 343 u_int tcor, tbpr; 344 u_int rcor, rbpr; 345 u_int msvr_rts, msvr_dtr; 346 u_int ccr; 347 int is_console; 348 int i; 349 350 /* 351 * All we're really concerned about here is putting the chip 352 * into a quiescent state so that it won't do anything until 353 * clmpccopen() is called. (Except the console channel.) 354 */ 355 356 /* 357 * If the chip is acting as console, set all channels to the supplied 358 * console baud rate. Otherwise, plump for 9600. 359 */ 360 if ( cons_sc && 361 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 362 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 363 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 364 is_console = 1; 365 } else { 366 clmpcc_speed(sc, 9600, &tcor, &tbpr); 367 clmpcc_speed(sc, 9600, &rcor, &rbpr); 368 is_console = 0; 369 } 370 371 /* Allow any pending output to be sent */ 372 delay(10000); 373 374 /* Send the Reset All command to channel 0 (resets all channels!) */ 375 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 376 377 delay(1000); 378 379 /* 380 * The chip will set it's firmware revision register to a non-zero 381 * value to indicate completion of reset. 382 */ 383 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 384 delay(1); 385 386 if ( i == 0 ) { 387 /* 388 * Watch out... If this chip is console, the message 389 * probably won't be sent since we just reset it! 390 */ 391 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 392 return -1; 393 } 394 395 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 396 clmpcc_select_channel(sc, i); 397 398 /* All interrupts are disabled to begin with */ 399 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 400 401 /* Make sure the channel interrupts on the correct vectors */ 402 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 403 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 404 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 405 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 406 407 /* Receive timer prescaler set to 1ms */ 408 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 409 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 410 411 /* We support Async mode only */ 412 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 413 414 /* Set the required baud rate */ 415 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 416 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 417 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 418 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 419 420 /* Always default to 8N1 (XXX what about console?) */ 421 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 422 CLMPCC_COR1_NO_PARITY | 423 CLMPCC_COR1_IGNORE_PAR); 424 425 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 426 427 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 428 429 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 430 CLMPCC_COR4_CDzd | 431 CLMPCC_COR4_CTSzd); 432 433 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 434 CLMPCC_COR5_CDod | 435 CLMPCC_COR5_CTSod | 436 CLMPCC_COR5_FLOW_NORM); 437 438 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 439 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 440 441 /* Set the receive FIFO timeout */ 442 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 443 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 444 445 /* At this point, we set up the console differently */ 446 if ( is_console && i == cons_chan ) { 447 msvr_rts = CLMPCC_MSVR_RTS; 448 msvr_dtr = CLMPCC_MSVR_DTR; 449 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 450 } else { 451 msvr_rts = 0; 452 msvr_dtr = 0; 453 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 454 } 455 456 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 457 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 458 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 459 delay(100); 460 } 461 462 return 0; 463 } 464 465 static void 466 clmpcc_shutdown(ch) 467 struct clmpcc_chan *ch; 468 { 469 int oldch; 470 471 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 472 473 /* Turn off interrupts. */ 474 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 475 476 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 477 /* Disable the transmitter and receiver */ 478 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 479 CLMPCC_CCR_T0_TX_DIS); 480 481 /* Drop RTS and DTR */ 482 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 483 } 484 485 clmpcc_select_channel(ch->ch_sc, oldch); 486 } 487 488 int 489 clmpccopen(dev, flag, mode, p) 490 dev_t dev; 491 int flag, mode; 492 struct proc *p; 493 { 494 struct clmpcc_softc *sc; 495 struct clmpcc_chan *ch; 496 struct tty *tp; 497 int oldch; 498 int error; 499 500 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 501 if (sc == NULL) 502 return (ENXIO); 503 504 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 505 506 tp = ch->ch_tty; 507 508 if ( ISSET(tp->t_state, TS_ISOPEN) && 509 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 510 return EBUSY; 511 512 /* 513 * Do the following iff this is a first open. 514 */ 515 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 516 517 ttychars(tp); 518 519 tp->t_dev = dev; 520 tp->t_iflag = TTYDEF_IFLAG; 521 tp->t_oflag = TTYDEF_OFLAG; 522 tp->t_lflag = TTYDEF_LFLAG; 523 tp->t_cflag = TTYDEF_CFLAG; 524 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 525 526 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 527 SET(tp->t_cflag, CLOCAL); 528 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 529 SET(tp->t_cflag, CRTSCTS); 530 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 531 SET(tp->t_cflag, MDMBUF); 532 533 /* 534 * Override some settings if the channel is being 535 * used as the console. 536 */ 537 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 538 tp->t_ospeed = tp->t_ispeed = cons_rate; 539 SET(tp->t_cflag, CLOCAL); 540 CLR(tp->t_cflag, CRTSCTS); 541 CLR(tp->t_cflag, HUPCL); 542 } 543 544 ch->ch_control = 0; 545 546 clmpcc_param(tp, &tp->t_termios); 547 ttsetwater(tp); 548 549 /* Clear the input ring */ 550 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 551 552 /* Select the channel */ 553 oldch = clmpcc_select_channel(sc, ch->ch_car); 554 555 /* Reset it */ 556 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 557 CLMPCC_CCR_T0_RX_EN | 558 CLMPCC_CCR_T0_TX_EN); 559 560 /* Enable receiver and modem change interrupts. */ 561 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 562 CLMPCC_IER_RET | 563 CLMPCC_IER_RX_FIFO); 564 565 /* Raise RTS and DTR */ 566 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 567 568 clmpcc_select_channel(sc, oldch); 569 } else 570 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 571 return EBUSY; 572 573 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 574 if (error) 575 goto bad; 576 577 error = (*linesw[tp->t_line].l_open)(dev, tp); 578 if (error) 579 goto bad; 580 581 return 0; 582 583 bad: 584 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 585 /* 586 * We failed to open the device, and nobody else had it opened. 587 * Clean up the state as appropriate. 588 */ 589 clmpcc_shutdown(ch); 590 } 591 592 return error; 593 } 594 595 int 596 clmpccclose(dev, flag, mode, p) 597 dev_t dev; 598 int flag, mode; 599 struct proc *p; 600 { 601 struct clmpcc_softc *sc = 602 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 603 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 604 struct tty *tp = ch->ch_tty; 605 int s; 606 607 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 608 return 0; 609 610 (*linesw[tp->t_line].l_close)(tp, flag); 611 612 s = spltty(); 613 614 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 615 /* 616 * Although we got a last close, the device may still be in 617 * use; e.g. if this was the dialout node, and there are still 618 * processes waiting for carrier on the non-dialout node. 619 */ 620 clmpcc_shutdown(ch); 621 } 622 623 ttyclose(tp); 624 625 splx(s); 626 627 return 0; 628 } 629 630 int 631 clmpccread(dev, uio, flag) 632 dev_t dev; 633 struct uio *uio; 634 int flag; 635 { 636 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 637 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 638 639 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 640 } 641 642 int 643 clmpccwrite(dev, uio, flag) 644 dev_t dev; 645 struct uio *uio; 646 int flag; 647 { 648 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 649 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 650 651 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 652 } 653 654 struct tty * 655 clmpcctty(dev) 656 dev_t dev; 657 { 658 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 659 660 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 661 } 662 663 int 664 clmpccioctl(dev, cmd, data, flag, p) 665 dev_t dev; 666 u_long cmd; 667 caddr_t data; 668 int flag; 669 struct proc *p; 670 { 671 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 672 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 673 struct tty *tp = ch->ch_tty; 674 int error; 675 676 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 677 if (error >= 0) 678 return error; 679 680 error = ttioctl(tp, cmd, data, flag, p); 681 if (error >= 0) 682 return error; 683 684 error = 0; 685 686 switch (cmd) { 687 case TIOCSBRK: 688 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 689 clmpcc_enable_transmitter(ch); 690 break; 691 692 case TIOCCBRK: 693 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 694 clmpcc_enable_transmitter(ch); 695 break; 696 697 case TIOCSDTR: 698 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 699 break; 700 701 case TIOCCDTR: 702 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 703 break; 704 705 case TIOCMSET: 706 clmpcc_modem_control(ch, *((int *)data), DMSET); 707 break; 708 709 case TIOCMBIS: 710 clmpcc_modem_control(ch, *((int *)data), DMBIS); 711 break; 712 713 case TIOCMBIC: 714 clmpcc_modem_control(ch, *((int *)data), DMBIC); 715 break; 716 717 case TIOCMGET: 718 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 719 break; 720 721 case TIOCGFLAGS: 722 *((int *)data) = ch->ch_openflags; 723 break; 724 725 case TIOCSFLAGS: 726 error = suser(p->p_ucred, &p->p_acflag); 727 if ( error ) 728 break; 729 ch->ch_openflags = *((int *)data) & 730 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 731 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 732 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 733 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 734 break; 735 736 default: 737 error = ENOTTY; 738 break; 739 } 740 741 return error; 742 } 743 744 int 745 clmpcc_modem_control(ch, bits, howto) 746 struct clmpcc_chan *ch; 747 int bits; 748 int howto; 749 { 750 struct clmpcc_softc *sc = ch->ch_sc; 751 struct tty *tp = ch->ch_tty; 752 int oldch; 753 int msvr; 754 int rbits = 0; 755 756 oldch = clmpcc_select_channel(sc, ch->ch_car); 757 758 switch ( howto ) { 759 case DMGET: 760 msvr = clmpcc_rd_msvr(sc); 761 762 if ( sc->sc_swaprtsdtr ) { 763 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 764 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 765 } else { 766 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 767 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 768 } 769 770 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 771 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 772 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 773 break; 774 775 case DMSET: 776 if ( sc->sc_swaprtsdtr ) { 777 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 778 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 779 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 780 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 781 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 782 } else { 783 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 784 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 785 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 786 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 787 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 788 } 789 break; 790 791 case DMBIS: 792 if ( sc->sc_swaprtsdtr ) { 793 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 794 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 795 if ( ISSET(bits, TIOCM_DTR) ) 796 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 797 } else { 798 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 799 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 800 if ( ISSET(bits, TIOCM_DTR) ) 801 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 802 } 803 break; 804 805 case DMBIC: 806 if ( sc->sc_swaprtsdtr ) { 807 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 808 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 809 if ( ISCLR(bits, TIOCM_DTR) ) 810 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 811 } else { 812 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 813 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 814 if ( ISCLR(bits, TIOCM_DTR) ) 815 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 816 } 817 break; 818 } 819 820 clmpcc_select_channel(sc, oldch); 821 822 return rbits; 823 } 824 825 static int 826 clmpcc_param(tp, t) 827 struct tty *tp; 828 struct termios *t; 829 { 830 struct clmpcc_softc *sc = 831 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 832 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 833 u_char cor; 834 u_char oldch; 835 int oclk, obpr; 836 int iclk, ibpr; 837 int s; 838 839 /* Check requested parameters. */ 840 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 841 return EINVAL; 842 843 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 844 return EINVAL; 845 846 /* 847 * For the console, always force CLOCAL and !HUPCL, so that the port 848 * is always active. 849 */ 850 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 851 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 852 SET(t->c_cflag, CLOCAL); 853 CLR(t->c_cflag, HUPCL); 854 } 855 856 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 857 858 /* If ospeed it zero, hangup the line */ 859 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 860 861 if ( t->c_ospeed ) { 862 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 863 ch->ch_tbpr = obpr; 864 } else { 865 ch->ch_tcor = 0; 866 ch->ch_tbpr = 0; 867 } 868 869 if ( t->c_ispeed ) { 870 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 871 ch->ch_rbpr = ibpr; 872 } else { 873 ch->ch_rcor = 0; 874 ch->ch_rbpr = 0; 875 } 876 877 /* Work out value to use for COR1 */ 878 cor = 0; 879 if ( ISSET(t->c_cflag, PARENB) ) { 880 cor |= CLMPCC_COR1_NORM_PARITY; 881 if ( ISSET(t->c_cflag, PARODD) ) 882 cor |= CLMPCC_COR1_ODD_PARITY; 883 } 884 885 if ( ISCLR(t->c_cflag, INPCK) ) 886 cor |= CLMPCC_COR1_IGNORE_PAR; 887 888 switch ( t->c_cflag & CSIZE ) { 889 case CS5: 890 cor |= CLMPCC_COR1_CHAR_5BITS; 891 break; 892 893 case CS6: 894 cor |= CLMPCC_COR1_CHAR_6BITS; 895 break; 896 897 case CS7: 898 cor |= CLMPCC_COR1_CHAR_7BITS; 899 break; 900 901 case CS8: 902 cor |= CLMPCC_COR1_CHAR_8BITS; 903 break; 904 } 905 906 ch->ch_cor1 = cor; 907 908 /* 909 * The only interesting bit in COR2 is 'CTS Automatic Enable' 910 * when hardware flow control is in effect. 911 */ 912 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 913 914 /* COR3 needs to be set to the number of stop bits... */ 915 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 916 CLMPCC_COR3_STOP_1; 917 918 /* 919 * COR4 contains the FIFO threshold setting. 920 * We adjust the threshold depending on the input speed... 921 */ 922 if ( t->c_ispeed <= 1200 ) 923 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 924 else if ( t->c_ispeed <= 19200 ) 925 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 926 else 927 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 928 929 /* 930 * If chip is used with CTS and DTR swapped, we can enable 931 * automatic hardware flow control. 932 */ 933 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 934 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 935 else 936 ch->ch_cor5 = 0; 937 938 s = splserial(); 939 oldch = clmpcc_select_channel(sc, ch->ch_car); 940 941 /* 942 * COR2 needs to be set immediately otherwise we might never get 943 * a Tx EMPTY interrupt to change the other parameters. 944 */ 945 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 946 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 947 948 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 949 clmpcc_set_params(ch); 950 else 951 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 952 953 clmpcc_select_channel(sc, oldch); 954 955 splx(s); 956 957 return 0; 958 } 959 960 static void 961 clmpcc_set_params(ch) 962 struct clmpcc_chan *ch; 963 { 964 struct clmpcc_softc *sc = ch->ch_sc; 965 u_char r1; 966 u_char r2; 967 968 if ( ch->ch_tcor || ch->ch_tbpr ) { 969 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 970 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 971 /* Only write Tx rate if it really has changed */ 972 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 973 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 974 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 975 } 976 } 977 978 if ( ch->ch_rcor || ch->ch_rbpr ) { 979 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 980 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 981 /* Only write Rx rate if it really has changed */ 982 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 983 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 984 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 985 } 986 } 987 988 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 989 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 990 /* Any change to COR1 requires an INIT command */ 991 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 992 } 993 994 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 995 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 996 997 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 998 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 999 /* 1000 * Note: If the FIFO has changed, we always set it to 1001 * zero here and disable the Receive Timeout interrupt. 1002 * It's up to the Rx Interrupt handler to pick the 1003 * appropriate moment to write the new FIFO length. 1004 */ 1005 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1006 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1007 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1008 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1009 } 1010 1011 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1012 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1013 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1014 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1015 } 1016 } 1017 1018 static void 1019 clmpcc_start(tp) 1020 struct tty *tp; 1021 { 1022 struct clmpcc_softc *sc = 1023 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1024 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1025 u_int oldch; 1026 int s; 1027 1028 s = spltty(); 1029 1030 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1031 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1032 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1033 CLR(tp->t_state, TS_ASLEEP); 1034 wakeup(&tp->t_outq); 1035 } 1036 selwakeup(&tp->t_wsel); 1037 } 1038 1039 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1040 CLMPCC_FLG_END_BREAK) || 1041 tp->t_outq.c_cc > 0 ) { 1042 1043 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1044 CLMPCC_FLG_END_BREAK) ) { 1045 ch->ch_obuf_addr = tp->t_outq.c_cf; 1046 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1047 } 1048 1049 /* Enable TX empty interrupts */ 1050 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1051 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1052 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1053 CLMPCC_IER_TX_EMPTY); 1054 clmpcc_select_channel(ch->ch_sc, oldch); 1055 SET(tp->t_state, TS_BUSY); 1056 } 1057 } 1058 1059 splx(s); 1060 } 1061 1062 /* 1063 * Stop output on a line. 1064 */ 1065 void 1066 clmpccstop(tp, flag) 1067 struct tty *tp; 1068 int flag; 1069 { 1070 struct clmpcc_softc *sc = 1071 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->dev)); 1072 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1073 int s; 1074 1075 s = splserial(); 1076 1077 if ( ISSET(tp->t_state, TS_BUSY) ) { 1078 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1079 SET(tp->t_state, TS_FLUSH); 1080 ch->ch_obuf_size = 0; 1081 } 1082 splx(s); 1083 } 1084 1085 /* 1086 * RX interrupt routine 1087 */ 1088 int 1089 clmpcc_rxintr(arg) 1090 void *arg; 1091 { 1092 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1093 struct clmpcc_chan *ch; 1094 u_int8_t *put, *end, rxd; 1095 u_char errstat; 1096 u_char fc, tc; 1097 u_char risr; 1098 u_char rir; 1099 #ifdef DDB 1100 int saw_break = 0; 1101 #endif 1102 1103 /* Receive interrupt active? */ 1104 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1105 1106 /* 1107 * If we're using auto-vectored interrupts, we have to 1108 * verify if the chip is generating the interrupt. 1109 */ 1110 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1111 return 0; 1112 1113 /* Get pointer to interrupting channel's data structure */ 1114 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1115 1116 /* Get the interrupt status register */ 1117 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1118 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1119 u_char reg; 1120 /* 1121 * Set the FIFO threshold to zero, and disable 1122 * further receive timeout interrupts. 1123 */ 1124 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1125 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1126 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1127 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1128 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1129 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1130 return 1; 1131 } 1132 1133 /* How many bytes are waiting in the FIFO? */ 1134 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1135 1136 #ifdef DDB 1137 /* 1138 * Allow BREAK on the console to drop to the debugger. 1139 */ 1140 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1141 risr & CLMPCC_RISR_BREAK ) { 1142 saw_break = 1; 1143 } 1144 #endif 1145 1146 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1147 /* Just get rid of the data */ 1148 while ( fc-- ) 1149 (void) clmpcc_rd_rxdata(sc); 1150 goto rx_done; 1151 } 1152 1153 put = ch->ch_ibuf_wr; 1154 end = ch->ch_ibuf_end; 1155 1156 /* 1157 * Note: The chip is completely hosed WRT these error 1158 * conditions; there seems to be no way to associate 1159 * the error with the correct character in the FIFO. 1160 * We compromise by tagging the first character we read 1161 * with the error. Not perfect, but there's no other way. 1162 */ 1163 errstat = 0; 1164 if ( risr & CLMPCC_RISR_PARITY ) 1165 errstat |= TTY_PE; 1166 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1167 errstat |= TTY_FE; 1168 1169 /* 1170 * As long as there are characters in the FIFO, and we 1171 * have space for them... 1172 */ 1173 while ( fc > 0 ) { 1174 1175 *put++ = rxd = clmpcc_rd_rxdata(sc); 1176 *put++ = errstat; 1177 1178 if ( put >= end ) 1179 put = ch->ch_ibuf; 1180 1181 if ( put == ch->ch_ibuf_rd ) { 1182 put -= 2; 1183 if ( put < ch->ch_ibuf ) 1184 put = end - 2; 1185 } 1186 1187 errstat = 0; 1188 fc--; 1189 } 1190 1191 ch->ch_ibuf_wr = put; 1192 1193 #if 0 1194 if ( sc->sc_swaprtsdtr == 0 && 1195 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1196 /* 1197 * If RTS/DTR are not physically swapped, we have to 1198 * do hardware flow control manually 1199 */ 1200 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1201 } 1202 #endif 1203 1204 rx_done: 1205 if ( fc != tc ) { 1206 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1207 u_char reg; 1208 /* 1209 * Set the FIFO threshold to the preset value, 1210 * and enable receive timeout interrupts. 1211 */ 1212 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1213 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1214 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1215 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1216 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1217 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1218 } 1219 1220 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1221 if ( sc->sc_soft_running == 0 ) { 1222 sc->sc_soft_running = 1; 1223 (sc->sc_softhook)(sc); 1224 } 1225 } else 1226 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1227 1228 #ifdef DDB 1229 /* 1230 * Only =after= we write REOIR is it safe to drop to the debugger. 1231 */ 1232 if ( saw_break ) 1233 Debugger(); 1234 #endif 1235 1236 return 1; 1237 } 1238 1239 /* 1240 * Tx interrupt routine 1241 */ 1242 int 1243 clmpcc_txintr(arg) 1244 void *arg; 1245 { 1246 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1247 struct clmpcc_chan *ch; 1248 struct tty *tp; 1249 u_char ftc, oftc; 1250 u_char tir, teoir; 1251 int etcmode = 0; 1252 1253 /* Tx interrupt active? */ 1254 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1255 1256 /* 1257 * If we're using auto-vectored interrupts, we have to 1258 * verify if the chip is generating the interrupt. 1259 */ 1260 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1261 return 0; 1262 1263 /* Get pointer to interrupting channel's data structure */ 1264 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1265 tp = ch->ch_tty; 1266 1267 /* Dummy read of the interrupt status register */ 1268 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1269 1270 /* Make sure embedded transmit commands are disabled */ 1271 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1272 1273 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1274 1275 /* Handle a delayed parameter change */ 1276 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1277 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1278 clmpcc_set_params(ch); 1279 } 1280 1281 if ( ch->ch_obuf_size > 0 ) { 1282 u_int n = min(ch->ch_obuf_size, ftc); 1283 1284 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1285 1286 ftc -= n; 1287 ch->ch_obuf_size -= n; 1288 ch->ch_obuf_addr += n; 1289 1290 } else { 1291 /* 1292 * Check if we should start/stop a break 1293 */ 1294 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1295 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1296 /* Enable embedded transmit commands */ 1297 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1298 ch->ch_cor2 | CLMPCC_COR2_ETC); 1299 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1300 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1301 ftc -= 2; 1302 etcmode = 1; 1303 } 1304 1305 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1306 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1307 /* Enable embedded transmit commands */ 1308 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1309 ch->ch_cor2 | CLMPCC_COR2_ETC); 1310 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1311 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1312 ftc -= 2; 1313 etcmode = 1; 1314 } 1315 } 1316 1317 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1318 1319 if ( ftc != oftc ) { 1320 /* 1321 * Enable/disable the Tx FIFO threshold interrupt 1322 * according to how much data is in the FIFO. 1323 * However, always disable the FIFO threshold if 1324 * we've left the channel in 'Embedded Transmit 1325 * Command' mode. 1326 */ 1327 if ( etcmode || ftc >= ch->ch_cor4 ) 1328 tir &= ~CLMPCC_IER_TX_FIFO; 1329 else 1330 tir |= CLMPCC_IER_TX_FIFO; 1331 teoir = 0; 1332 } else { 1333 /* 1334 * No data was sent. 1335 * Disable transmit interrupt. 1336 */ 1337 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1338 teoir = CLMPCC_TEOIR_NO_TRANS; 1339 1340 /* 1341 * Request Tx processing in the soft interrupt handler 1342 */ 1343 ch->ch_tx_done = 1; 1344 if ( ! sc->sc_soft_running ) { 1345 sc->sc_soft_running = 1; 1346 (sc->sc_softhook)(sc); 1347 } 1348 } 1349 1350 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1351 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1352 1353 return 1; 1354 } 1355 1356 /* 1357 * Modem change interrupt routine 1358 */ 1359 int 1360 clmpcc_mdintr(arg) 1361 void *arg; 1362 { 1363 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1364 u_char mir; 1365 1366 /* Modem status interrupt active? */ 1367 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1368 1369 /* 1370 * If we're using auto-vectored interrupts, we have to 1371 * verify if the chip is generating the interrupt. 1372 */ 1373 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1374 return 0; 1375 1376 /* Dummy read of the interrupt status register */ 1377 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1378 1379 /* Retrieve current status of modem lines. */ 1380 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1381 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1382 1383 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1384 1385 if ( sc->sc_soft_running == 0 ) { 1386 sc->sc_soft_running = 1; 1387 (sc->sc_softhook)(sc); 1388 } 1389 1390 return 1; 1391 } 1392 1393 void 1394 clmpcc_softintr(arg) 1395 void *arg; 1396 { 1397 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1398 struct clmpcc_chan *ch; 1399 struct tty *tp; 1400 int (*rint) __P((int, struct tty *)); 1401 u_char *get; 1402 u_char reg; 1403 u_int c; 1404 int chan; 1405 1406 sc->sc_soft_running = 0; 1407 1408 /* Handle Modem state changes too... */ 1409 1410 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1411 ch = &sc->sc_chans[chan]; 1412 tp = ch->ch_tty; 1413 1414 get = ch->ch_ibuf_rd; 1415 rint = linesw[tp->t_line].l_rint; 1416 1417 /* Squirt buffered incoming data into the tty layer */ 1418 while ( get != ch->ch_ibuf_wr ) { 1419 c = get[0]; 1420 c |= ((u_int)get[1]) << 8; 1421 if ( (rint)(c, tp) == -1 ) { 1422 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1423 break; 1424 } 1425 1426 get += 2; 1427 if ( get == ch->ch_ibuf_end ) 1428 get = ch->ch_ibuf; 1429 1430 ch->ch_ibuf_rd = get; 1431 } 1432 1433 /* 1434 * Is the transmitter idle and in need of attention? 1435 */ 1436 if ( ch->ch_tx_done ) { 1437 ch->ch_tx_done = 0; 1438 1439 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1440 clmpcc_channel_cmd(sc, ch->ch_car, 1441 CLMPCC_CCR_T0_INIT | 1442 CLMPCC_CCR_T0_RX_EN | 1443 CLMPCC_CCR_T0_TX_EN); 1444 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1445 1446 /* 1447 * Allow time for the channel to initialise. 1448 * (Empirically derived duration; there must 1449 * be another way to determine the command 1450 * has completed without busy-waiting...) 1451 */ 1452 delay(800); 1453 1454 /* 1455 * Update the tty layer's idea of the carrier 1456 * bit, in case we changed CLOCAL or MDMBUF. 1457 * We don't hang up here; we only do that by 1458 * explicit request. 1459 */ 1460 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1461 (*linesw[tp->t_line].l_modem)(tp, reg != 0); 1462 } 1463 1464 CLR(tp->t_state, TS_BUSY); 1465 if ( ISSET(tp->t_state, TS_FLUSH) ) 1466 CLR(tp->t_state, TS_FLUSH); 1467 else 1468 ndflush(&tp->t_outq, 1469 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1470 1471 (*linesw[tp->t_line].l_start)(tp); 1472 } 1473 } 1474 } 1475 1476 1477 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1478 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1479 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1480 /* 1481 * Following are all routines needed for a cd240x channel to act as console 1482 */ 1483 int 1484 clmpcc_cnattach(sc, chan, rate) 1485 struct clmpcc_softc *sc; 1486 int chan; 1487 int rate; 1488 { 1489 cons_sc = sc; 1490 cons_chan = chan; 1491 cons_rate = rate; 1492 1493 return 0; 1494 } 1495 1496 /* 1497 * The following functions are polled getc and putc routines, for console use. 1498 */ 1499 static int 1500 clmpcc_common_getc(sc, chan) 1501 struct clmpcc_softc *sc; 1502 int chan; 1503 { 1504 u_char old_chan; 1505 u_char old_ier; 1506 u_char ch, rir, risr; 1507 int s; 1508 1509 s = splhigh(); 1510 1511 /* Save the currently active channel */ 1512 old_chan = clmpcc_select_channel(sc, chan); 1513 1514 /* 1515 * We have to put the channel into RX interrupt mode before 1516 * trying to read the Rx data register. So save the previous 1517 * interrupt mode. 1518 */ 1519 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1520 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1521 1522 /* Loop until we get a character */ 1523 for (;;) { 1524 /* 1525 * The REN bit will be set in the Receive Interrupt Register 1526 * when the CD240x has a character to process. Remember, 1527 * the RACT bit won't be set until we generate an interrupt 1528 * acknowledge cycle via the MD front-end. 1529 */ 1530 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1531 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1532 continue; 1533 1534 /* Acknowledge the request */ 1535 if ( sc->sc_iackhook ) 1536 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1537 1538 /* 1539 * Determine if the interrupt is for the required channel 1540 * and if valid data is available. 1541 */ 1542 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1543 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1544 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1545 risr != 0 ) { 1546 /* Rx error, or BREAK */ 1547 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1548 CLMPCC_REOIR_NO_TRANS); 1549 } else { 1550 /* Dummy read of the FIFO count register */ 1551 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1552 1553 /* Fetch the received character */ 1554 ch = clmpcc_rd_rxdata(sc); 1555 1556 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1557 break; 1558 } 1559 } 1560 1561 /* Restore the original IER and CAR register contents */ 1562 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1563 clmpcc_select_channel(sc, old_chan); 1564 1565 splx(s); 1566 return ch; 1567 } 1568 1569 1570 static void 1571 clmpcc_common_putc(sc, chan, c) 1572 struct clmpcc_softc *sc; 1573 int chan; 1574 int c; 1575 { 1576 u_char old_chan; 1577 int s = splhigh(); 1578 1579 /* Save the currently active channel */ 1580 old_chan = clmpcc_select_channel(sc, chan); 1581 1582 /* 1583 * Since we can only access the Tx Data register from within 1584 * the interrupt handler, the easiest way to get console data 1585 * onto the wire is using one of the Special Transmit Character 1586 * registers. 1587 */ 1588 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1589 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1590 CLMPCC_STCR_SND_SPC); 1591 1592 /* Wait until the "Send Special Character" command is accepted */ 1593 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1594 ; 1595 1596 /* Restore the previous channel selected */ 1597 clmpcc_select_channel(sc, old_chan); 1598 1599 splx(s); 1600 } 1601 1602 int 1603 clmpcccngetc(dev) 1604 dev_t dev; 1605 { 1606 return clmpcc_common_getc(cons_sc, cons_chan); 1607 } 1608 1609 /* 1610 * Console kernel output character routine. 1611 */ 1612 void 1613 clmpcccnputc(dev, c) 1614 dev_t dev; 1615 int c; 1616 { 1617 if ( c == '\n' ) 1618 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1619 1620 clmpcc_common_putc(cons_sc, cons_chan, c); 1621 } 1622