1 /* $NetBSD: clmpcc.c,v 1.10 2000/03/19 10:38:43 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include "opt_ddb.h" 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/select.h> 50 #include <sys/tty.h> 51 #include <sys/proc.h> 52 #include <sys/user.h> 53 #include <sys/conf.h> 54 #include <sys/file.h> 55 #include <sys/uio.h> 56 #include <sys/kernel.h> 57 #include <sys/syslog.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 61 #include <machine/bus.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/clmpccreg.h> 65 #include <dev/ic/clmpccvar.h> 66 #include <dev/cons.h> 67 68 69 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 70 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 71 #endif 72 73 74 static int clmpcc_init __P((struct clmpcc_softc *sc)); 75 static void clmpcc_shutdown __P((struct clmpcc_chan *)); 76 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t, 77 int *, int *)); 78 static int clmpcc_param __P((struct tty *, struct termios *)); 79 static void clmpcc_set_params __P((struct clmpcc_chan *)); 80 static void clmpcc_start __P((struct tty *)); 81 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int)); 82 83 84 cdev_decl(clmpcc); 85 86 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 87 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 88 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 89 90 /* 91 * These should be in a header file somewhere... 92 */ 93 #define ISSET(v, f) (((v) & (f)) != 0) 94 #define ISCLR(v, f) (((v) & (f)) == 0) 95 #define SET(v, f) (v) |= (f) 96 #define CLR(v, f) (v) &= ~(f) 97 98 99 extern struct cfdriver clmpcc_cd; 100 101 102 /* 103 * Make this an option variable one can patch. 104 */ 105 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 106 107 108 /* 109 * Things needed when the device is used as a console 110 */ 111 static struct clmpcc_softc *cons_sc = NULL; 112 static int cons_chan; 113 static int cons_rate; 114 115 static int clmpcc_common_getc __P((struct clmpcc_softc *, int)); 116 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int)); 117 int clmpcccngetc __P((dev_t)); 118 void clmpcccnputc __P((dev_t, int)); 119 120 121 /* 122 * Convenience functions, inlined for speed 123 */ 124 #define integrate static inline 125 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int)); 126 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int)); 127 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int)); 128 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int)); 129 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *, 130 u_int)); 131 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int)); 132 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int)); 133 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *)); 134 135 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 136 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 137 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 138 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 139 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 140 141 142 integrate u_int8_t 143 clmpcc_rdreg(sc, offset) 144 struct clmpcc_softc *sc; 145 u_int offset; 146 { 147 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 148 offset ^= sc->sc_byteswap; 149 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 150 offset ^= CLMPCC_BYTESWAP_HIGH; 151 #endif 152 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 153 } 154 155 integrate void 156 clmpcc_wrreg(sc, offset, val) 157 struct clmpcc_softc *sc; 158 u_int offset; 159 u_int val; 160 { 161 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 162 offset ^= sc->sc_byteswap; 163 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 164 offset ^= CLMPCC_BYTESWAP_HIGH; 165 #endif 166 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 167 } 168 169 integrate u_int8_t 170 clmpcc_rdreg_odd(sc, offset) 171 struct clmpcc_softc *sc; 172 u_int offset; 173 { 174 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 175 offset ^= (sc->sc_byteswap & 2); 176 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 177 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 178 #endif 179 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 180 } 181 182 integrate void 183 clmpcc_wrreg_odd(sc, offset, val) 184 struct clmpcc_softc *sc; 185 u_int offset; 186 u_int val; 187 { 188 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 189 offset ^= (sc->sc_byteswap & 2); 190 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 191 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 192 #endif 193 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 194 } 195 196 integrate void 197 clmpcc_wrtx_multi(sc, buff, count) 198 struct clmpcc_softc *sc; 199 u_int8_t *buff; 200 u_int count; 201 { 202 u_int offset = CLMPCC_REG_TDR; 203 204 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 205 offset ^= (sc->sc_byteswap & 2); 206 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 207 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 208 #endif 209 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 210 } 211 212 integrate u_int8_t 213 clmpcc_select_channel(sc, new_chan) 214 struct clmpcc_softc *sc; 215 u_int new_chan; 216 { 217 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 218 219 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 220 221 return old_chan; 222 } 223 224 integrate void 225 clmpcc_channel_cmd(sc, chan, cmd) 226 struct clmpcc_softc *sc; 227 int chan; 228 int cmd; 229 { 230 int i; 231 232 for (i = 5000; i; i--) { 233 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 234 break; 235 delay(1); 236 } 237 238 if ( i == 0 ) 239 printf("%s: channel %d command timeout (idle)\n", 240 sc->sc_dev.dv_xname, chan); 241 242 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 243 } 244 245 integrate void 246 clmpcc_enable_transmitter(ch) 247 struct clmpcc_chan *ch; 248 { 249 u_int old; 250 int s; 251 252 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 253 254 s = splserial(); 255 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 256 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 257 SET(ch->ch_tty->t_state, TS_BUSY); 258 splx(s); 259 260 clmpcc_select_channel(ch->ch_sc, old); 261 } 262 263 static int 264 clmpcc_speed(sc, speed, cor, bpr) 265 struct clmpcc_softc *sc; 266 speed_t speed; 267 int *cor, *bpr; 268 { 269 int c, co, br; 270 271 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 272 br = ((sc->sc_clk / c) / speed) - 1; 273 if ( br < 0x100 ) { 274 *cor = co; 275 *bpr = br; 276 return 0; 277 } 278 } 279 280 return -1; 281 } 282 283 void 284 clmpcc_attach(sc) 285 struct clmpcc_softc *sc; 286 { 287 struct clmpcc_chan *ch; 288 struct tty *tp; 289 int chan; 290 291 if ( cons_sc != NULL && 292 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 293 cons_sc = sc; 294 295 /* Initialise the chip */ 296 clmpcc_init(sc); 297 298 printf(": Cirrus Logic CD240%c Serial Controller\n", 299 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 300 301 sc->sc_soft_running = 0; 302 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 303 304 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 305 ch = &sc->sc_chans[chan]; 306 307 ch->ch_sc = sc; 308 ch->ch_car = chan; 309 310 tp = ttymalloc(); 311 tp->t_oproc = clmpcc_start; 312 tp->t_param = clmpcc_param; 313 314 ch->ch_tty = tp; 315 316 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 317 if ( ch->ch_ibuf == NULL ) { 318 printf("%s(%d): unable to allocate ring buffer\n", 319 sc->sc_dev.dv_xname, chan); 320 return; 321 } 322 323 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 324 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 325 326 tty_attach(tp); 327 } 328 329 printf("%s: %d channels available", sc->sc_dev.dv_xname, 330 CLMPCC_NUM_CHANS); 331 if ( cons_sc == sc ) { 332 printf(", console on channel %d.\n", cons_chan); 333 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 334 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 335 } else 336 printf(".\n"); 337 } 338 339 static int 340 clmpcc_init(sc) 341 struct clmpcc_softc *sc; 342 { 343 u_int tcor, tbpr; 344 u_int rcor, rbpr; 345 u_int msvr_rts, msvr_dtr; 346 u_int ccr; 347 int is_console; 348 int i; 349 350 /* 351 * All we're really concerned about here is putting the chip 352 * into a quiescent state so that it won't do anything until 353 * clmpccopen() is called. (Except the console channel.) 354 */ 355 356 /* 357 * If the chip is acting as console, set all channels to the supplied 358 * console baud rate. Otherwise, plump for 9600. 359 */ 360 if ( cons_sc && 361 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 362 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 363 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 364 is_console = 1; 365 } else { 366 clmpcc_speed(sc, 9600, &tcor, &tbpr); 367 clmpcc_speed(sc, 9600, &rcor, &rbpr); 368 is_console = 0; 369 } 370 371 /* Allow any pending output to be sent */ 372 delay(10000); 373 374 /* Send the Reset All command to channel 0 (resets all channels!) */ 375 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 376 377 delay(1000); 378 379 /* 380 * The chip will set it's firmware revision register to a non-zero 381 * value to indicate completion of reset. 382 */ 383 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 384 delay(1); 385 386 if ( i == 0 ) { 387 /* 388 * Watch out... If this chip is console, the message 389 * probably won't be sent since we just reset it! 390 */ 391 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 392 return -1; 393 } 394 395 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 396 clmpcc_select_channel(sc, i); 397 398 /* All interrupts are disabled to begin with */ 399 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 400 401 /* Make sure the channel interrupts on the correct vectors */ 402 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 403 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 404 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 405 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 406 407 /* Receive timer prescaler set to 1ms */ 408 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 409 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 410 411 /* We support Async mode only */ 412 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 413 414 /* Set the required baud rate */ 415 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 416 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 417 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 418 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 419 420 /* Always default to 8N1 (XXX what about console?) */ 421 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 422 CLMPCC_COR1_NO_PARITY | 423 CLMPCC_COR1_IGNORE_PAR); 424 425 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 426 427 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 428 429 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 430 CLMPCC_COR4_CDzd | 431 CLMPCC_COR4_CTSzd); 432 433 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 434 CLMPCC_COR5_CDod | 435 CLMPCC_COR5_CTSod | 436 CLMPCC_COR5_FLOW_NORM); 437 438 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 439 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 440 441 /* Set the receive FIFO timeout */ 442 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 443 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 444 445 /* At this point, we set up the console differently */ 446 if ( is_console && i == cons_chan ) { 447 msvr_rts = CLMPCC_MSVR_RTS; 448 msvr_dtr = CLMPCC_MSVR_DTR; 449 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 450 } else { 451 msvr_rts = 0; 452 msvr_dtr = 0; 453 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 454 } 455 456 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 457 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 458 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 459 delay(100); 460 } 461 462 return 0; 463 } 464 465 static void 466 clmpcc_shutdown(ch) 467 struct clmpcc_chan *ch; 468 { 469 int oldch; 470 471 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 472 473 /* Turn off interrupts. */ 474 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 475 476 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 477 /* Disable the transmitter and receiver */ 478 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 479 CLMPCC_CCR_T0_TX_DIS); 480 481 /* Drop RTS and DTR */ 482 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 483 } 484 485 clmpcc_select_channel(ch->ch_sc, oldch); 486 } 487 488 int 489 clmpccopen(dev, flag, mode, p) 490 dev_t dev; 491 int flag, mode; 492 struct proc *p; 493 { 494 struct clmpcc_softc *sc; 495 struct clmpcc_chan *ch; 496 struct tty *tp; 497 int oldch; 498 int error; 499 int unit; 500 501 if ( (unit = CLMPCCUNIT(dev)) >= clmpcc_cd.cd_ndevs || 502 (sc = clmpcc_cd.cd_devs[unit]) == NULL ) { 503 return ENXIO; 504 } 505 506 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 507 508 tp = ch->ch_tty; 509 510 if ( ISSET(tp->t_state, TS_ISOPEN) && 511 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 512 return EBUSY; 513 514 /* 515 * Do the following iff this is a first open. 516 */ 517 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 518 519 ttychars(tp); 520 521 tp->t_dev = dev; 522 tp->t_iflag = TTYDEF_IFLAG; 523 tp->t_oflag = TTYDEF_OFLAG; 524 tp->t_lflag = TTYDEF_LFLAG; 525 tp->t_cflag = TTYDEF_CFLAG; 526 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 527 528 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 529 SET(tp->t_cflag, CLOCAL); 530 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 531 SET(tp->t_cflag, CRTSCTS); 532 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 533 SET(tp->t_cflag, MDMBUF); 534 535 /* 536 * Override some settings if the channel is being 537 * used as the console. 538 */ 539 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 540 tp->t_ospeed = tp->t_ispeed = cons_rate; 541 SET(tp->t_cflag, CLOCAL); 542 CLR(tp->t_cflag, CRTSCTS); 543 CLR(tp->t_cflag, HUPCL); 544 } 545 546 ch->ch_control = 0; 547 548 clmpcc_param(tp, &tp->t_termios); 549 ttsetwater(tp); 550 551 /* Clear the input ring */ 552 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 553 554 /* Select the channel */ 555 oldch = clmpcc_select_channel(sc, ch->ch_car); 556 557 /* Reset it */ 558 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 559 CLMPCC_CCR_T0_RX_EN | 560 CLMPCC_CCR_T0_TX_EN); 561 562 /* Enable receiver and modem change interrupts. */ 563 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 564 CLMPCC_IER_RET | 565 CLMPCC_IER_RX_FIFO); 566 567 /* Raise RTS and DTR */ 568 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 569 570 clmpcc_select_channel(sc, oldch); 571 } else 572 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 573 return EBUSY; 574 575 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 576 if (error) 577 goto bad; 578 579 error = (*linesw[tp->t_line].l_open)(dev, tp); 580 if (error) 581 goto bad; 582 583 return 0; 584 585 bad: 586 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 587 /* 588 * We failed to open the device, and nobody else had it opened. 589 * Clean up the state as appropriate. 590 */ 591 clmpcc_shutdown(ch); 592 } 593 594 return error; 595 } 596 597 int 598 clmpccclose(dev, flag, mode, p) 599 dev_t dev; 600 int flag, mode; 601 struct proc *p; 602 { 603 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)]; 604 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 605 struct tty *tp = ch->ch_tty; 606 int s; 607 608 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 609 return 0; 610 611 (*linesw[tp->t_line].l_close)(tp, flag); 612 613 s = spltty(); 614 615 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 616 /* 617 * Although we got a last close, the device may still be in 618 * use; e.g. if this was the dialout node, and there are still 619 * processes waiting for carrier on the non-dialout node. 620 */ 621 clmpcc_shutdown(ch); 622 } 623 624 ttyclose(tp); 625 626 splx(s); 627 628 return 0; 629 } 630 631 int 632 clmpccread(dev, uio, flag) 633 dev_t dev; 634 struct uio *uio; 635 int flag; 636 { 637 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)]; 638 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 639 640 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 641 } 642 643 int 644 clmpccwrite(dev, uio, flag) 645 dev_t dev; 646 struct uio *uio; 647 int flag; 648 { 649 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)]; 650 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 651 652 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 653 } 654 655 struct tty * 656 clmpcctty(dev) 657 dev_t dev; 658 { 659 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)]; 660 661 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 662 } 663 664 int 665 clmpccioctl(dev, cmd, data, flag, p) 666 dev_t dev; 667 u_long cmd; 668 caddr_t data; 669 int flag; 670 struct proc *p; 671 { 672 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)]; 673 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 674 struct tty *tp = ch->ch_tty; 675 int error; 676 677 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 678 if (error >= 0) 679 return error; 680 681 error = ttioctl(tp, cmd, data, flag, p); 682 if (error >= 0) 683 return error; 684 685 error = 0; 686 687 switch (cmd) { 688 case TIOCSBRK: 689 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 690 clmpcc_enable_transmitter(ch); 691 break; 692 693 case TIOCCBRK: 694 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 695 clmpcc_enable_transmitter(ch); 696 break; 697 698 case TIOCSDTR: 699 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 700 break; 701 702 case TIOCCDTR: 703 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 704 break; 705 706 case TIOCMSET: 707 clmpcc_modem_control(ch, *((int *)data), DMSET); 708 break; 709 710 case TIOCMBIS: 711 clmpcc_modem_control(ch, *((int *)data), DMBIS); 712 break; 713 714 case TIOCMBIC: 715 clmpcc_modem_control(ch, *((int *)data), DMBIC); 716 break; 717 718 case TIOCMGET: 719 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 720 break; 721 722 case TIOCGFLAGS: 723 *((int *)data) = ch->ch_openflags; 724 break; 725 726 case TIOCSFLAGS: 727 error = suser(p->p_ucred, &p->p_acflag); 728 if ( error ) 729 break; 730 ch->ch_openflags = *((int *)data) & 731 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 732 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 733 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 734 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 735 break; 736 737 default: 738 error = ENOTTY; 739 break; 740 } 741 742 return error; 743 } 744 745 int 746 clmpcc_modem_control(ch, bits, howto) 747 struct clmpcc_chan *ch; 748 int bits; 749 int howto; 750 { 751 struct clmpcc_softc *sc = ch->ch_sc; 752 struct tty *tp = ch->ch_tty; 753 int oldch; 754 int msvr; 755 int rbits = 0; 756 757 oldch = clmpcc_select_channel(sc, ch->ch_car); 758 759 switch ( howto ) { 760 case DMGET: 761 msvr = clmpcc_rd_msvr(sc); 762 763 if ( sc->sc_swaprtsdtr ) { 764 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 765 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 766 } else { 767 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 768 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 769 } 770 771 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 772 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 773 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 774 break; 775 776 case DMSET: 777 if ( sc->sc_swaprtsdtr ) { 778 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 779 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 780 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 781 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 782 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 783 } else { 784 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 785 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 786 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 787 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 788 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 789 } 790 break; 791 792 case DMBIS: 793 if ( sc->sc_swaprtsdtr ) { 794 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 795 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 796 if ( ISSET(bits, TIOCM_DTR) ) 797 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 798 } else { 799 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 800 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 801 if ( ISSET(bits, TIOCM_DTR) ) 802 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 803 } 804 break; 805 806 case DMBIC: 807 if ( sc->sc_swaprtsdtr ) { 808 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 809 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 810 if ( ISCLR(bits, TIOCM_DTR) ) 811 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 812 } else { 813 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 814 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 815 if ( ISCLR(bits, TIOCM_DTR) ) 816 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 817 } 818 break; 819 } 820 821 clmpcc_select_channel(sc, oldch); 822 823 return rbits; 824 } 825 826 static int 827 clmpcc_param(tp, t) 828 struct tty *tp; 829 struct termios *t; 830 { 831 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(tp->t_dev)]; 832 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 833 u_char cor; 834 u_char oldch; 835 int oclk, obpr; 836 int iclk, ibpr; 837 int s; 838 839 /* Check requested parameters. */ 840 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 841 return EINVAL; 842 843 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 844 return EINVAL; 845 846 /* 847 * For the console, always force CLOCAL and !HUPCL, so that the port 848 * is always active. 849 */ 850 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 851 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 852 SET(t->c_cflag, CLOCAL); 853 CLR(t->c_cflag, HUPCL); 854 } 855 856 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 857 858 /* If ospeed it zero, hangup the line */ 859 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 860 861 if ( t->c_ospeed ) { 862 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 863 ch->ch_tbpr = obpr; 864 } else { 865 ch->ch_tcor = 0; 866 ch->ch_tbpr = 0; 867 } 868 869 if ( t->c_ispeed ) { 870 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 871 ch->ch_rbpr = ibpr; 872 } else { 873 ch->ch_rcor = 0; 874 ch->ch_rbpr = 0; 875 } 876 877 /* Work out value to use for COR1 */ 878 cor = 0; 879 if ( ISSET(t->c_cflag, PARENB) ) { 880 cor |= CLMPCC_COR1_NORM_PARITY; 881 if ( ISSET(t->c_cflag, PARODD) ) 882 cor |= CLMPCC_COR1_ODD_PARITY; 883 } 884 885 if ( ISCLR(t->c_cflag, INPCK) ) 886 cor |= CLMPCC_COR1_IGNORE_PAR; 887 888 switch ( t->c_cflag & CSIZE ) { 889 case CS5: 890 cor |= CLMPCC_COR1_CHAR_5BITS; 891 break; 892 893 case CS6: 894 cor |= CLMPCC_COR1_CHAR_6BITS; 895 break; 896 897 case CS7: 898 cor |= CLMPCC_COR1_CHAR_7BITS; 899 break; 900 901 case CS8: 902 cor |= CLMPCC_COR1_CHAR_8BITS; 903 break; 904 } 905 906 ch->ch_cor1 = cor; 907 908 /* 909 * The only interesting bit in COR2 is 'CTS Automatic Enable' 910 * when hardware flow control is in effect. 911 */ 912 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 913 914 /* COR3 needs to be set to the number of stop bits... */ 915 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 916 CLMPCC_COR3_STOP_1; 917 918 /* 919 * COR4 contains the FIFO threshold setting. 920 * We adjust the threshold depending on the input speed... 921 */ 922 if ( t->c_ispeed <= 1200 ) 923 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 924 else if ( t->c_ispeed <= 19200 ) 925 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 926 else 927 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 928 929 /* 930 * If chip is used with CTS and DTR swapped, we can enable 931 * automatic hardware flow control. 932 */ 933 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 934 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 935 else 936 ch->ch_cor5 = 0; 937 938 s = splserial(); 939 oldch = clmpcc_select_channel(sc, ch->ch_car); 940 941 /* 942 * COR2 needs to be set immediately otherwise we might never get 943 * a Tx EMPTY interrupt to change the other parameters. 944 */ 945 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 946 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 947 948 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 949 clmpcc_set_params(ch); 950 else 951 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 952 953 clmpcc_select_channel(sc, oldch); 954 955 splx(s); 956 957 return 0; 958 } 959 960 static void 961 clmpcc_set_params(ch) 962 struct clmpcc_chan *ch; 963 { 964 struct clmpcc_softc *sc = ch->ch_sc; 965 u_char r1; 966 u_char r2; 967 968 if ( ch->ch_tcor || ch->ch_tbpr ) { 969 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 970 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 971 /* Only write Tx rate if it really has changed */ 972 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 973 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 974 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 975 } 976 } 977 978 if ( ch->ch_rcor || ch->ch_rbpr ) { 979 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 980 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 981 /* Only write Rx rate if it really has changed */ 982 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 983 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 984 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 985 } 986 } 987 988 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 989 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 990 /* Any change to COR1 requires an INIT command */ 991 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 992 } 993 994 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 995 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 996 997 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 998 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 999 /* 1000 * Note: If the FIFO has changed, we always set it to 1001 * zero here and disable the Receive Timeout interrupt. 1002 * It's up to the Rx Interrupt handler to pick the 1003 * appropriate moment to write the new FIFO length. 1004 */ 1005 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1006 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1007 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1008 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1009 } 1010 1011 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1012 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1013 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1014 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1015 } 1016 } 1017 1018 static void 1019 clmpcc_start(tp) 1020 struct tty *tp; 1021 { 1022 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(tp->t_dev)]; 1023 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1024 u_int oldch; 1025 int s; 1026 1027 s = spltty(); 1028 1029 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1030 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1031 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1032 CLR(tp->t_state, TS_ASLEEP); 1033 wakeup(&tp->t_outq); 1034 } 1035 selwakeup(&tp->t_wsel); 1036 } 1037 1038 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1039 CLMPCC_FLG_END_BREAK) || 1040 tp->t_outq.c_cc > 0 ) { 1041 1042 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1043 CLMPCC_FLG_END_BREAK) ) { 1044 ch->ch_obuf_addr = tp->t_outq.c_cf; 1045 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1046 } 1047 1048 /* Enable TX empty interrupts */ 1049 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1050 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1051 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1052 CLMPCC_IER_TX_EMPTY); 1053 clmpcc_select_channel(ch->ch_sc, oldch); 1054 SET(tp->t_state, TS_BUSY); 1055 } 1056 } 1057 1058 splx(s); 1059 } 1060 1061 /* 1062 * Stop output on a line. 1063 */ 1064 void 1065 clmpccstop(tp, flag) 1066 struct tty *tp; 1067 int flag; 1068 { 1069 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(tp->t_dev)]; 1070 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1071 int s; 1072 1073 s = splserial(); 1074 1075 if ( ISSET(tp->t_state, TS_BUSY) ) { 1076 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1077 SET(tp->t_state, TS_FLUSH); 1078 ch->ch_obuf_size = 0; 1079 } 1080 splx(s); 1081 } 1082 1083 /* 1084 * RX interrupt routine 1085 */ 1086 int 1087 clmpcc_rxintr(arg) 1088 void *arg; 1089 { 1090 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1091 struct clmpcc_chan *ch; 1092 u_int8_t *put, *end, rxd; 1093 u_char errstat; 1094 u_char fc, tc; 1095 u_char risr; 1096 u_char rir; 1097 #ifdef DDB 1098 int saw_break = 0; 1099 #endif 1100 1101 /* Receive interrupt active? */ 1102 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1103 1104 /* 1105 * If we're using auto-vectored interrupts, we have to 1106 * verify if the chip is generating the interrupt. 1107 */ 1108 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1109 return 0; 1110 1111 /* Get pointer to interrupting channel's data structure */ 1112 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1113 1114 /* Get the interrupt status register */ 1115 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1116 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1117 u_char reg; 1118 /* 1119 * Set the FIFO threshold to zero, and disable 1120 * further receive timeout interrupts. 1121 */ 1122 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1123 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1124 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1125 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1126 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1127 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1128 return 1; 1129 } 1130 1131 /* How many bytes are waiting in the FIFO? */ 1132 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1133 1134 #ifdef DDB 1135 /* 1136 * Allow BREAK on the console to drop to the debugger. 1137 */ 1138 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1139 risr & CLMPCC_RISR_BREAK ) { 1140 saw_break = 1; 1141 } 1142 #endif 1143 1144 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1145 /* Just get rid of the data */ 1146 while ( fc-- ) 1147 (void) clmpcc_rd_rxdata(sc); 1148 goto rx_done; 1149 } 1150 1151 put = ch->ch_ibuf_wr; 1152 end = ch->ch_ibuf_end; 1153 1154 /* 1155 * Note: The chip is completely hosed WRT these error 1156 * conditions; there seems to be no way to associate 1157 * the error with the correct character in the FIFO. 1158 * We compromise by tagging the first character we read 1159 * with the error. Not perfect, but there's no other way. 1160 */ 1161 errstat = 0; 1162 if ( risr & CLMPCC_RISR_PARITY ) 1163 errstat |= TTY_PE; 1164 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1165 errstat |= TTY_FE; 1166 1167 /* 1168 * As long as there are characters in the FIFO, and we 1169 * have space for them... 1170 */ 1171 while ( fc > 0 ) { 1172 1173 *put++ = rxd = clmpcc_rd_rxdata(sc); 1174 *put++ = errstat; 1175 1176 if ( put >= end ) 1177 put = ch->ch_ibuf; 1178 1179 if ( put == ch->ch_ibuf_rd ) { 1180 put -= 2; 1181 if ( put < ch->ch_ibuf ) 1182 put = end - 2; 1183 } 1184 1185 errstat = 0; 1186 fc--; 1187 } 1188 1189 ch->ch_ibuf_wr = put; 1190 1191 #if 0 1192 if ( sc->sc_swaprtsdtr == 0 && 1193 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1194 /* 1195 * If RTS/DTR are not physically swapped, we have to 1196 * do hardware flow control manually 1197 */ 1198 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1199 } 1200 #endif 1201 1202 rx_done: 1203 if ( fc != tc ) { 1204 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1205 u_char reg; 1206 /* 1207 * Set the FIFO threshold to the preset value, 1208 * and enable receive timeout interrupts. 1209 */ 1210 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1211 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1212 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1213 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1214 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1215 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1216 } 1217 1218 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1219 if ( sc->sc_soft_running == 0 ) { 1220 sc->sc_soft_running = 1; 1221 (sc->sc_softhook)(sc); 1222 } 1223 } else 1224 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1225 1226 #ifdef DDB 1227 /* 1228 * Only =after= we write REOIR is it safe to drop to the debugger. 1229 */ 1230 if ( saw_break ) 1231 Debugger(); 1232 #endif 1233 1234 return 1; 1235 } 1236 1237 /* 1238 * Tx interrupt routine 1239 */ 1240 int 1241 clmpcc_txintr(arg) 1242 void *arg; 1243 { 1244 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1245 struct clmpcc_chan *ch; 1246 struct tty *tp; 1247 u_char ftc, oftc; 1248 u_char tir, teoir; 1249 int etcmode = 0; 1250 1251 /* Tx interrupt active? */ 1252 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1253 1254 /* 1255 * If we're using auto-vectored interrupts, we have to 1256 * verify if the chip is generating the interrupt. 1257 */ 1258 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1259 return 0; 1260 1261 /* Get pointer to interrupting channel's data structure */ 1262 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1263 tp = ch->ch_tty; 1264 1265 /* Dummy read of the interrupt status register */ 1266 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1267 1268 /* Make sure embedded transmit commands are disabled */ 1269 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1270 1271 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1272 1273 /* Handle a delayed parameter change */ 1274 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1275 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1276 clmpcc_set_params(ch); 1277 } 1278 1279 if ( ch->ch_obuf_size > 0 ) { 1280 u_int n = min(ch->ch_obuf_size, ftc); 1281 1282 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1283 1284 ftc -= n; 1285 ch->ch_obuf_size -= n; 1286 ch->ch_obuf_addr += n; 1287 1288 } else { 1289 /* 1290 * Check if we should start/stop a break 1291 */ 1292 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1293 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1294 /* Enable embedded transmit commands */ 1295 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1296 ch->ch_cor2 | CLMPCC_COR2_ETC); 1297 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1298 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1299 ftc -= 2; 1300 etcmode = 1; 1301 } 1302 1303 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1304 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1305 /* Enable embedded transmit commands */ 1306 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1307 ch->ch_cor2 | CLMPCC_COR2_ETC); 1308 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1309 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1310 ftc -= 2; 1311 etcmode = 1; 1312 } 1313 } 1314 1315 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1316 1317 if ( ftc != oftc ) { 1318 /* 1319 * Enable/disable the Tx FIFO threshold interrupt 1320 * according to how much data is in the FIFO. 1321 * However, always disable the FIFO threshold if 1322 * we've left the channel in 'Embedded Transmit 1323 * Command' mode. 1324 */ 1325 if ( etcmode || ftc >= ch->ch_cor4 ) 1326 tir &= ~CLMPCC_IER_TX_FIFO; 1327 else 1328 tir |= CLMPCC_IER_TX_FIFO; 1329 teoir = 0; 1330 } else { 1331 /* 1332 * No data was sent. 1333 * Disable transmit interrupt. 1334 */ 1335 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1336 teoir = CLMPCC_TEOIR_NO_TRANS; 1337 1338 /* 1339 * Request Tx processing in the soft interrupt handler 1340 */ 1341 ch->ch_tx_done = 1; 1342 if ( ! sc->sc_soft_running ) { 1343 sc->sc_soft_running = 1; 1344 (sc->sc_softhook)(sc); 1345 } 1346 } 1347 1348 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1349 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1350 1351 return 1; 1352 } 1353 1354 /* 1355 * Modem change interrupt routine 1356 */ 1357 int 1358 clmpcc_mdintr(arg) 1359 void *arg; 1360 { 1361 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1362 u_char mir; 1363 1364 /* Modem status interrupt active? */ 1365 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1366 1367 /* 1368 * If we're using auto-vectored interrupts, we have to 1369 * verify if the chip is generating the interrupt. 1370 */ 1371 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1372 return 0; 1373 1374 /* Dummy read of the interrupt status register */ 1375 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1376 1377 /* Retrieve current status of modem lines. */ 1378 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1379 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1380 1381 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1382 1383 if ( sc->sc_soft_running == 0 ) { 1384 sc->sc_soft_running = 1; 1385 (sc->sc_softhook)(sc); 1386 } 1387 1388 return 1; 1389 } 1390 1391 void 1392 clmpcc_softintr(arg) 1393 void *arg; 1394 { 1395 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1396 struct clmpcc_chan *ch; 1397 struct tty *tp; 1398 int (*rint) __P((int, struct tty *)); 1399 u_char *get; 1400 u_char reg; 1401 u_int c; 1402 int chan; 1403 1404 sc->sc_soft_running = 0; 1405 1406 /* Handle Modem state changes too... */ 1407 1408 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1409 ch = &sc->sc_chans[chan]; 1410 tp = ch->ch_tty; 1411 1412 get = ch->ch_ibuf_rd; 1413 rint = linesw[tp->t_line].l_rint; 1414 1415 /* Squirt buffered incoming data into the tty layer */ 1416 while ( get != ch->ch_ibuf_wr ) { 1417 c = get[0]; 1418 c |= ((u_int)get[1]) << 8; 1419 if ( (rint)(c, tp) == -1 ) { 1420 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1421 break; 1422 } 1423 1424 get += 2; 1425 if ( get == ch->ch_ibuf_end ) 1426 get = ch->ch_ibuf; 1427 1428 ch->ch_ibuf_rd = get; 1429 } 1430 1431 /* 1432 * Is the transmitter idle and in need of attention? 1433 */ 1434 if ( ch->ch_tx_done ) { 1435 ch->ch_tx_done = 0; 1436 1437 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1438 clmpcc_channel_cmd(sc, ch->ch_car, 1439 CLMPCC_CCR_T0_INIT | 1440 CLMPCC_CCR_T0_RX_EN | 1441 CLMPCC_CCR_T0_TX_EN); 1442 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1443 1444 /* 1445 * Allow time for the channel to initialise. 1446 * (Empirically derived duration; there must 1447 * be another way to determine the command 1448 * has completed without busy-waiting...) 1449 */ 1450 delay(800); 1451 1452 /* 1453 * Update the tty layer's idea of the carrier 1454 * bit, in case we changed CLOCAL or MDMBUF. 1455 * We don't hang up here; we only do that by 1456 * explicit request. 1457 */ 1458 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1459 (*linesw[tp->t_line].l_modem)(tp, reg != 0); 1460 } 1461 1462 CLR(tp->t_state, TS_BUSY); 1463 if ( ISSET(tp->t_state, TS_FLUSH) ) 1464 CLR(tp->t_state, TS_FLUSH); 1465 else 1466 ndflush(&tp->t_outq, 1467 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1468 1469 (*linesw[tp->t_line].l_start)(tp); 1470 } 1471 } 1472 } 1473 1474 1475 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1476 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1477 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1478 /* 1479 * Following are all routines needed for a cd240x channel to act as console 1480 */ 1481 int 1482 clmpcc_cnattach(sc, chan, rate) 1483 struct clmpcc_softc *sc; 1484 int chan; 1485 int rate; 1486 { 1487 cons_sc = sc; 1488 cons_chan = chan; 1489 cons_rate = rate; 1490 1491 return 0; 1492 } 1493 1494 /* 1495 * The following functions are polled getc and putc routines, for console use. 1496 */ 1497 static int 1498 clmpcc_common_getc(sc, chan) 1499 struct clmpcc_softc *sc; 1500 int chan; 1501 { 1502 u_char old_chan; 1503 u_char old_ier; 1504 u_char ch, rir, risr; 1505 int s; 1506 1507 s = splhigh(); 1508 1509 /* Save the currently active channel */ 1510 old_chan = clmpcc_select_channel(sc, chan); 1511 1512 /* 1513 * We have to put the channel into RX interrupt mode before 1514 * trying to read the Rx data register. So save the previous 1515 * interrupt mode. 1516 */ 1517 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1518 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1519 1520 /* Loop until we get a character */ 1521 for (;;) { 1522 /* 1523 * The REN bit will be set in the Receive Interrupt Register 1524 * when the CD240x has a character to process. Remember, 1525 * the RACT bit won't be set until we generate an interrupt 1526 * acknowledge cycle via the MD front-end. 1527 */ 1528 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1529 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1530 continue; 1531 1532 /* Acknowledge the request */ 1533 if ( sc->sc_iackhook ) 1534 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1535 1536 /* 1537 * Determine if the interrupt is for the required channel 1538 * and if valid data is available. 1539 */ 1540 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1541 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1542 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1543 risr != 0 ) { 1544 /* Rx error, or BREAK */ 1545 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1546 CLMPCC_REOIR_NO_TRANS); 1547 } else { 1548 /* Dummy read of the FIFO count register */ 1549 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1550 1551 /* Fetch the received character */ 1552 ch = clmpcc_rd_rxdata(sc); 1553 1554 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1555 break; 1556 } 1557 } 1558 1559 /* Restore the original IER and CAR register contents */ 1560 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1561 clmpcc_select_channel(sc, old_chan); 1562 1563 splx(s); 1564 return ch; 1565 } 1566 1567 1568 static void 1569 clmpcc_common_putc(sc, chan, c) 1570 struct clmpcc_softc *sc; 1571 int chan; 1572 int c; 1573 { 1574 u_char old_chan; 1575 int s = splhigh(); 1576 1577 /* Save the currently active channel */ 1578 old_chan = clmpcc_select_channel(sc, chan); 1579 1580 /* 1581 * Since we can only access the Tx Data register from within 1582 * the interrupt handler, the easiest way to get console data 1583 * onto the wire is using one of the Special Transmit Character 1584 * registers. 1585 */ 1586 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1587 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1588 CLMPCC_STCR_SND_SPC); 1589 1590 /* Wait until the "Send Special Character" command is accepted */ 1591 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1592 ; 1593 1594 /* Restore the previous channel selected */ 1595 clmpcc_select_channel(sc, old_chan); 1596 1597 splx(s); 1598 } 1599 1600 int 1601 clmpcccngetc(dev) 1602 dev_t dev; 1603 { 1604 return clmpcc_common_getc(cons_sc, cons_chan); 1605 } 1606 1607 /* 1608 * Console kernel output character routine. 1609 */ 1610 void 1611 clmpcccnputc(dev, c) 1612 dev_t dev; 1613 int c; 1614 { 1615 if ( c == '\n' ) 1616 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1617 1618 clmpcc_common_putc(cons_sc, cons_chan, c); 1619 } 1620