1 /* $NetBSD: clmpcc.c,v 1.17 2001/07/12 17:21:01 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include "opt_ddb.h" 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/select.h> 50 #include <sys/tty.h> 51 #include <sys/proc.h> 52 #include <sys/user.h> 53 #include <sys/conf.h> 54 #include <sys/file.h> 55 #include <sys/uio.h> 56 #include <sys/kernel.h> 57 #include <sys/syslog.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 #include <machine/param.h> 64 65 #include <dev/ic/clmpccreg.h> 66 #include <dev/ic/clmpccvar.h> 67 #include <dev/cons.h> 68 69 70 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 71 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 72 #endif 73 74 75 static int clmpcc_init __P((struct clmpcc_softc *sc)); 76 static void clmpcc_shutdown __P((struct clmpcc_chan *)); 77 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t, 78 int *, int *)); 79 static int clmpcc_param __P((struct tty *, struct termios *)); 80 static void clmpcc_set_params __P((struct clmpcc_chan *)); 81 static void clmpcc_start __P((struct tty *)); 82 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int)); 83 84 85 cdev_decl(clmpcc); 86 87 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 88 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 89 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 90 91 /* 92 * These should be in a header file somewhere... 93 */ 94 #define ISSET(v, f) (((v) & (f)) != 0) 95 #define ISCLR(v, f) (((v) & (f)) == 0) 96 #define SET(v, f) (v) |= (f) 97 #define CLR(v, f) (v) &= ~(f) 98 99 100 extern struct cfdriver clmpcc_cd; 101 102 103 /* 104 * Make this an option variable one can patch. 105 */ 106 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 107 108 109 /* 110 * Things needed when the device is used as a console 111 */ 112 static struct clmpcc_softc *cons_sc = NULL; 113 static int cons_chan; 114 static int cons_rate; 115 116 static int clmpcc_common_getc __P((struct clmpcc_softc *, int)); 117 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int)); 118 int clmpcccngetc __P((dev_t)); 119 void clmpcccnputc __P((dev_t, int)); 120 121 122 /* 123 * Convenience functions, inlined for speed 124 */ 125 #define integrate static inline 126 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int)); 127 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int)); 128 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int)); 129 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int)); 130 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *, 131 u_int)); 132 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int)); 133 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int)); 134 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *)); 135 136 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 137 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 138 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 139 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 140 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 141 142 143 integrate u_int8_t 144 clmpcc_rdreg(sc, offset) 145 struct clmpcc_softc *sc; 146 u_int offset; 147 { 148 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 149 offset ^= sc->sc_byteswap; 150 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 151 offset ^= CLMPCC_BYTESWAP_HIGH; 152 #endif 153 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 154 } 155 156 integrate void 157 clmpcc_wrreg(sc, offset, val) 158 struct clmpcc_softc *sc; 159 u_int offset; 160 u_int val; 161 { 162 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 163 offset ^= sc->sc_byteswap; 164 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 165 offset ^= CLMPCC_BYTESWAP_HIGH; 166 #endif 167 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 168 } 169 170 integrate u_int8_t 171 clmpcc_rdreg_odd(sc, offset) 172 struct clmpcc_softc *sc; 173 u_int offset; 174 { 175 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 176 offset ^= (sc->sc_byteswap & 2); 177 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 178 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 179 #endif 180 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 181 } 182 183 integrate void 184 clmpcc_wrreg_odd(sc, offset, val) 185 struct clmpcc_softc *sc; 186 u_int offset; 187 u_int val; 188 { 189 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 190 offset ^= (sc->sc_byteswap & 2); 191 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 192 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 193 #endif 194 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 195 } 196 197 integrate void 198 clmpcc_wrtx_multi(sc, buff, count) 199 struct clmpcc_softc *sc; 200 u_int8_t *buff; 201 u_int count; 202 { 203 u_int offset = CLMPCC_REG_TDR; 204 205 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 206 offset ^= (sc->sc_byteswap & 2); 207 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 208 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 209 #endif 210 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 211 } 212 213 integrate u_int8_t 214 clmpcc_select_channel(sc, new_chan) 215 struct clmpcc_softc *sc; 216 u_int new_chan; 217 { 218 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 219 220 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 221 222 return old_chan; 223 } 224 225 integrate void 226 clmpcc_channel_cmd(sc, chan, cmd) 227 struct clmpcc_softc *sc; 228 int chan; 229 int cmd; 230 { 231 int i; 232 233 for (i = 5000; i; i--) { 234 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 235 break; 236 delay(1); 237 } 238 239 if ( i == 0 ) 240 printf("%s: channel %d command timeout (idle)\n", 241 sc->sc_dev.dv_xname, chan); 242 243 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 244 } 245 246 integrate void 247 clmpcc_enable_transmitter(ch) 248 struct clmpcc_chan *ch; 249 { 250 u_int old; 251 int s; 252 253 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 254 255 s = splserial(); 256 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 257 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 258 SET(ch->ch_tty->t_state, TS_BUSY); 259 splx(s); 260 261 clmpcc_select_channel(ch->ch_sc, old); 262 } 263 264 static int 265 clmpcc_speed(sc, speed, cor, bpr) 266 struct clmpcc_softc *sc; 267 speed_t speed; 268 int *cor, *bpr; 269 { 270 int c, co, br; 271 272 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 273 br = ((sc->sc_clk / c) / speed) - 1; 274 if ( br < 0x100 ) { 275 *cor = co; 276 *bpr = br; 277 return 0; 278 } 279 } 280 281 return -1; 282 } 283 284 void 285 clmpcc_attach(sc) 286 struct clmpcc_softc *sc; 287 { 288 struct clmpcc_chan *ch; 289 struct tty *tp; 290 int chan; 291 292 if ( cons_sc != NULL && 293 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 294 cons_sc = sc; 295 296 /* Initialise the chip */ 297 clmpcc_init(sc); 298 299 printf(": Cirrus Logic CD240%c Serial Controller\n", 300 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 301 302 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 303 sc->sc_soft_running = 0; 304 #else 305 sc->sc_softintr_cookie = 306 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc); 307 #ifdef DEBUG 308 if (sc->sc_softintr_cookie == NULL) 309 panic("clmpcc_attach: softintr_establish"); 310 #endif 311 #endif 312 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 313 314 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 315 ch = &sc->sc_chans[chan]; 316 317 ch->ch_sc = sc; 318 ch->ch_car = chan; 319 320 tp = ttymalloc(); 321 tp->t_oproc = clmpcc_start; 322 tp->t_param = clmpcc_param; 323 324 ch->ch_tty = tp; 325 326 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 327 if ( ch->ch_ibuf == NULL ) { 328 printf("%s(%d): unable to allocate ring buffer\n", 329 sc->sc_dev.dv_xname, chan); 330 return; 331 } 332 333 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 334 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 335 336 tty_attach(tp); 337 } 338 339 printf("%s: %d channels available", sc->sc_dev.dv_xname, 340 CLMPCC_NUM_CHANS); 341 if ( cons_sc == sc ) { 342 printf(", console on channel %d.\n", cons_chan); 343 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 344 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 345 } else 346 printf(".\n"); 347 } 348 349 static int 350 clmpcc_init(sc) 351 struct clmpcc_softc *sc; 352 { 353 u_int tcor, tbpr; 354 u_int rcor, rbpr; 355 u_int msvr_rts, msvr_dtr; 356 u_int ccr; 357 int is_console; 358 int i; 359 360 /* 361 * All we're really concerned about here is putting the chip 362 * into a quiescent state so that it won't do anything until 363 * clmpccopen() is called. (Except the console channel.) 364 */ 365 366 /* 367 * If the chip is acting as console, set all channels to the supplied 368 * console baud rate. Otherwise, plump for 9600. 369 */ 370 if ( cons_sc && 371 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 372 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 373 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 374 is_console = 1; 375 } else { 376 clmpcc_speed(sc, 9600, &tcor, &tbpr); 377 clmpcc_speed(sc, 9600, &rcor, &rbpr); 378 is_console = 0; 379 } 380 381 /* Allow any pending output to be sent */ 382 delay(10000); 383 384 /* Send the Reset All command to channel 0 (resets all channels!) */ 385 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 386 387 delay(1000); 388 389 /* 390 * The chip will set it's firmware revision register to a non-zero 391 * value to indicate completion of reset. 392 */ 393 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 394 delay(1); 395 396 if ( i == 0 ) { 397 /* 398 * Watch out... If this chip is console, the message 399 * probably won't be sent since we just reset it! 400 */ 401 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 402 return -1; 403 } 404 405 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 406 clmpcc_select_channel(sc, i); 407 408 /* All interrupts are disabled to begin with */ 409 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 410 411 /* Make sure the channel interrupts on the correct vectors */ 412 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 413 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 414 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 415 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 416 417 /* Receive timer prescaler set to 1ms */ 418 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 419 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 420 421 /* We support Async mode only */ 422 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 423 424 /* Set the required baud rate */ 425 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 426 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 427 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 428 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 429 430 /* Always default to 8N1 (XXX what about console?) */ 431 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 432 CLMPCC_COR1_NO_PARITY | 433 CLMPCC_COR1_IGNORE_PAR); 434 435 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 436 437 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 438 439 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 440 CLMPCC_COR4_CDzd | 441 CLMPCC_COR4_CTSzd); 442 443 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 444 CLMPCC_COR5_CDod | 445 CLMPCC_COR5_CTSod | 446 CLMPCC_COR5_FLOW_NORM); 447 448 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 449 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 450 451 /* Set the receive FIFO timeout */ 452 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 453 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 454 455 /* At this point, we set up the console differently */ 456 if ( is_console && i == cons_chan ) { 457 msvr_rts = CLMPCC_MSVR_RTS; 458 msvr_dtr = CLMPCC_MSVR_DTR; 459 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 460 } else { 461 msvr_rts = 0; 462 msvr_dtr = 0; 463 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 464 } 465 466 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 467 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 468 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 469 delay(100); 470 } 471 472 return 0; 473 } 474 475 static void 476 clmpcc_shutdown(ch) 477 struct clmpcc_chan *ch; 478 { 479 int oldch; 480 481 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 482 483 /* Turn off interrupts. */ 484 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 485 486 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 487 /* Disable the transmitter and receiver */ 488 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 489 CLMPCC_CCR_T0_TX_DIS); 490 491 /* Drop RTS and DTR */ 492 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 493 } 494 495 clmpcc_select_channel(ch->ch_sc, oldch); 496 } 497 498 int 499 clmpccopen(dev, flag, mode, p) 500 dev_t dev; 501 int flag, mode; 502 struct proc *p; 503 { 504 struct clmpcc_softc *sc; 505 struct clmpcc_chan *ch; 506 struct tty *tp; 507 int oldch; 508 int error; 509 510 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 511 if (sc == NULL) 512 return (ENXIO); 513 514 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 515 516 tp = ch->ch_tty; 517 518 if ( ISSET(tp->t_state, TS_ISOPEN) && 519 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 520 return EBUSY; 521 522 /* 523 * Do the following iff this is a first open. 524 */ 525 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 526 527 ttychars(tp); 528 529 tp->t_dev = dev; 530 tp->t_iflag = TTYDEF_IFLAG; 531 tp->t_oflag = TTYDEF_OFLAG; 532 tp->t_lflag = TTYDEF_LFLAG; 533 tp->t_cflag = TTYDEF_CFLAG; 534 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 535 536 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 537 SET(tp->t_cflag, CLOCAL); 538 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 539 SET(tp->t_cflag, CRTSCTS); 540 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 541 SET(tp->t_cflag, MDMBUF); 542 543 /* 544 * Override some settings if the channel is being 545 * used as the console. 546 */ 547 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 548 tp->t_ospeed = tp->t_ispeed = cons_rate; 549 SET(tp->t_cflag, CLOCAL); 550 CLR(tp->t_cflag, CRTSCTS); 551 CLR(tp->t_cflag, HUPCL); 552 } 553 554 ch->ch_control = 0; 555 556 clmpcc_param(tp, &tp->t_termios); 557 ttsetwater(tp); 558 559 /* Clear the input ring */ 560 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 561 562 /* Select the channel */ 563 oldch = clmpcc_select_channel(sc, ch->ch_car); 564 565 /* Reset it */ 566 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 567 CLMPCC_CCR_T0_RX_EN | 568 CLMPCC_CCR_T0_TX_EN); 569 570 /* Enable receiver and modem change interrupts. */ 571 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 572 CLMPCC_IER_RET | 573 CLMPCC_IER_RX_FIFO); 574 575 /* Raise RTS and DTR */ 576 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 577 578 clmpcc_select_channel(sc, oldch); 579 } else 580 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 581 return EBUSY; 582 583 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 584 if (error) 585 goto bad; 586 587 error = (*tp->t_linesw->l_open)(dev, tp); 588 if (error) 589 goto bad; 590 591 return 0; 592 593 bad: 594 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 595 /* 596 * We failed to open the device, and nobody else had it opened. 597 * Clean up the state as appropriate. 598 */ 599 clmpcc_shutdown(ch); 600 } 601 602 return error; 603 } 604 605 int 606 clmpccclose(dev, flag, mode, p) 607 dev_t dev; 608 int flag, mode; 609 struct proc *p; 610 { 611 struct clmpcc_softc *sc = 612 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 613 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 614 struct tty *tp = ch->ch_tty; 615 int s; 616 617 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 618 return 0; 619 620 (*tp->t_linesw->l_close)(tp, flag); 621 622 s = spltty(); 623 624 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 625 /* 626 * Although we got a last close, the device may still be in 627 * use; e.g. if this was the dialout node, and there are still 628 * processes waiting for carrier on the non-dialout node. 629 */ 630 clmpcc_shutdown(ch); 631 } 632 633 ttyclose(tp); 634 635 splx(s); 636 637 return 0; 638 } 639 640 int 641 clmpccread(dev, uio, flag) 642 dev_t dev; 643 struct uio *uio; 644 int flag; 645 { 646 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 647 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 648 649 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 650 } 651 652 int 653 clmpccwrite(dev, uio, flag) 654 dev_t dev; 655 struct uio *uio; 656 int flag; 657 { 658 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 659 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 660 661 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 662 } 663 664 int 665 clmpccpoll(dev, events, p) 666 dev_t dev; 667 int events; 668 struct proc *p; 669 { 670 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 671 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 672 673 return ((*tp->t_linesw->l_poll)(tp, events, p)); 674 } 675 676 struct tty * 677 clmpcctty(dev) 678 dev_t dev; 679 { 680 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 681 682 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 683 } 684 685 int 686 clmpccioctl(dev, cmd, data, flag, p) 687 dev_t dev; 688 u_long cmd; 689 caddr_t data; 690 int flag; 691 struct proc *p; 692 { 693 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 694 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 695 struct tty *tp = ch->ch_tty; 696 int error; 697 698 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 699 if (error >= 0) 700 return error; 701 702 error = ttioctl(tp, cmd, data, flag, p); 703 if (error >= 0) 704 return error; 705 706 error = 0; 707 708 switch (cmd) { 709 case TIOCSBRK: 710 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 711 clmpcc_enable_transmitter(ch); 712 break; 713 714 case TIOCCBRK: 715 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 716 clmpcc_enable_transmitter(ch); 717 break; 718 719 case TIOCSDTR: 720 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 721 break; 722 723 case TIOCCDTR: 724 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 725 break; 726 727 case TIOCMSET: 728 clmpcc_modem_control(ch, *((int *)data), DMSET); 729 break; 730 731 case TIOCMBIS: 732 clmpcc_modem_control(ch, *((int *)data), DMBIS); 733 break; 734 735 case TIOCMBIC: 736 clmpcc_modem_control(ch, *((int *)data), DMBIC); 737 break; 738 739 case TIOCMGET: 740 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 741 break; 742 743 case TIOCGFLAGS: 744 *((int *)data) = ch->ch_openflags; 745 break; 746 747 case TIOCSFLAGS: 748 error = suser(p->p_ucred, &p->p_acflag); 749 if ( error ) 750 break; 751 ch->ch_openflags = *((int *)data) & 752 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 753 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 754 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 755 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 756 break; 757 758 default: 759 error = ENOTTY; 760 break; 761 } 762 763 return error; 764 } 765 766 int 767 clmpcc_modem_control(ch, bits, howto) 768 struct clmpcc_chan *ch; 769 int bits; 770 int howto; 771 { 772 struct clmpcc_softc *sc = ch->ch_sc; 773 struct tty *tp = ch->ch_tty; 774 int oldch; 775 int msvr; 776 int rbits = 0; 777 778 oldch = clmpcc_select_channel(sc, ch->ch_car); 779 780 switch ( howto ) { 781 case DMGET: 782 msvr = clmpcc_rd_msvr(sc); 783 784 if ( sc->sc_swaprtsdtr ) { 785 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 786 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 787 } else { 788 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 789 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 790 } 791 792 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 793 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 794 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 795 break; 796 797 case DMSET: 798 if ( sc->sc_swaprtsdtr ) { 799 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 800 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 801 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 802 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 803 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 804 } else { 805 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 806 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 807 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 808 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 809 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 810 } 811 break; 812 813 case DMBIS: 814 if ( sc->sc_swaprtsdtr ) { 815 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 816 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 817 if ( ISSET(bits, TIOCM_DTR) ) 818 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 819 } else { 820 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 821 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 822 if ( ISSET(bits, TIOCM_DTR) ) 823 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 824 } 825 break; 826 827 case DMBIC: 828 if ( sc->sc_swaprtsdtr ) { 829 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 830 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 831 if ( ISCLR(bits, TIOCM_DTR) ) 832 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 833 } else { 834 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 835 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 836 if ( ISCLR(bits, TIOCM_DTR) ) 837 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 838 } 839 break; 840 } 841 842 clmpcc_select_channel(sc, oldch); 843 844 return rbits; 845 } 846 847 static int 848 clmpcc_param(tp, t) 849 struct tty *tp; 850 struct termios *t; 851 { 852 struct clmpcc_softc *sc = 853 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 854 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 855 u_char cor; 856 u_char oldch; 857 int oclk, obpr; 858 int iclk, ibpr; 859 int s; 860 861 /* Check requested parameters. */ 862 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 863 return EINVAL; 864 865 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 866 return EINVAL; 867 868 /* 869 * For the console, always force CLOCAL and !HUPCL, so that the port 870 * is always active. 871 */ 872 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 873 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 874 SET(t->c_cflag, CLOCAL); 875 CLR(t->c_cflag, HUPCL); 876 } 877 878 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 879 880 /* If ospeed it zero, hangup the line */ 881 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 882 883 if ( t->c_ospeed ) { 884 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 885 ch->ch_tbpr = obpr; 886 } else { 887 ch->ch_tcor = 0; 888 ch->ch_tbpr = 0; 889 } 890 891 if ( t->c_ispeed ) { 892 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 893 ch->ch_rbpr = ibpr; 894 } else { 895 ch->ch_rcor = 0; 896 ch->ch_rbpr = 0; 897 } 898 899 /* Work out value to use for COR1 */ 900 cor = 0; 901 if ( ISSET(t->c_cflag, PARENB) ) { 902 cor |= CLMPCC_COR1_NORM_PARITY; 903 if ( ISSET(t->c_cflag, PARODD) ) 904 cor |= CLMPCC_COR1_ODD_PARITY; 905 } 906 907 if ( ISCLR(t->c_cflag, INPCK) ) 908 cor |= CLMPCC_COR1_IGNORE_PAR; 909 910 switch ( t->c_cflag & CSIZE ) { 911 case CS5: 912 cor |= CLMPCC_COR1_CHAR_5BITS; 913 break; 914 915 case CS6: 916 cor |= CLMPCC_COR1_CHAR_6BITS; 917 break; 918 919 case CS7: 920 cor |= CLMPCC_COR1_CHAR_7BITS; 921 break; 922 923 case CS8: 924 cor |= CLMPCC_COR1_CHAR_8BITS; 925 break; 926 } 927 928 ch->ch_cor1 = cor; 929 930 /* 931 * The only interesting bit in COR2 is 'CTS Automatic Enable' 932 * when hardware flow control is in effect. 933 */ 934 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 935 936 /* COR3 needs to be set to the number of stop bits... */ 937 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 938 CLMPCC_COR3_STOP_1; 939 940 /* 941 * COR4 contains the FIFO threshold setting. 942 * We adjust the threshold depending on the input speed... 943 */ 944 if ( t->c_ispeed <= 1200 ) 945 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 946 else if ( t->c_ispeed <= 19200 ) 947 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 948 else 949 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 950 951 /* 952 * If chip is used with CTS and DTR swapped, we can enable 953 * automatic hardware flow control. 954 */ 955 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 956 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 957 else 958 ch->ch_cor5 = 0; 959 960 s = splserial(); 961 oldch = clmpcc_select_channel(sc, ch->ch_car); 962 963 /* 964 * COR2 needs to be set immediately otherwise we might never get 965 * a Tx EMPTY interrupt to change the other parameters. 966 */ 967 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 968 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 969 970 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 971 clmpcc_set_params(ch); 972 else 973 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 974 975 clmpcc_select_channel(sc, oldch); 976 977 splx(s); 978 979 return 0; 980 } 981 982 static void 983 clmpcc_set_params(ch) 984 struct clmpcc_chan *ch; 985 { 986 struct clmpcc_softc *sc = ch->ch_sc; 987 u_char r1; 988 u_char r2; 989 990 if ( ch->ch_tcor || ch->ch_tbpr ) { 991 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 992 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 993 /* Only write Tx rate if it really has changed */ 994 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 995 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 996 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 997 } 998 } 999 1000 if ( ch->ch_rcor || ch->ch_rbpr ) { 1001 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 1002 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 1003 /* Only write Rx rate if it really has changed */ 1004 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 1005 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 1006 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1007 } 1008 } 1009 1010 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1011 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1012 /* Any change to COR1 requires an INIT command */ 1013 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1014 } 1015 1016 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1017 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1018 1019 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1020 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1021 /* 1022 * Note: If the FIFO has changed, we always set it to 1023 * zero here and disable the Receive Timeout interrupt. 1024 * It's up to the Rx Interrupt handler to pick the 1025 * appropriate moment to write the new FIFO length. 1026 */ 1027 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1028 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1029 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1030 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1031 } 1032 1033 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1034 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1035 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1036 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1037 } 1038 } 1039 1040 static void 1041 clmpcc_start(tp) 1042 struct tty *tp; 1043 { 1044 struct clmpcc_softc *sc = 1045 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1046 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1047 u_int oldch; 1048 int s; 1049 1050 s = spltty(); 1051 1052 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1053 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1054 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1055 CLR(tp->t_state, TS_ASLEEP); 1056 wakeup(&tp->t_outq); 1057 } 1058 selwakeup(&tp->t_wsel); 1059 } 1060 1061 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1062 CLMPCC_FLG_END_BREAK) || 1063 tp->t_outq.c_cc > 0 ) { 1064 1065 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1066 CLMPCC_FLG_END_BREAK) ) { 1067 ch->ch_obuf_addr = tp->t_outq.c_cf; 1068 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1069 } 1070 1071 /* Enable TX empty interrupts */ 1072 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1073 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1074 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1075 CLMPCC_IER_TX_EMPTY); 1076 clmpcc_select_channel(ch->ch_sc, oldch); 1077 SET(tp->t_state, TS_BUSY); 1078 } 1079 } 1080 1081 splx(s); 1082 } 1083 1084 /* 1085 * Stop output on a line. 1086 */ 1087 void 1088 clmpccstop(tp, flag) 1089 struct tty *tp; 1090 int flag; 1091 { 1092 struct clmpcc_softc *sc = 1093 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1094 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1095 int s; 1096 1097 s = splserial(); 1098 1099 if ( ISSET(tp->t_state, TS_BUSY) ) { 1100 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1101 SET(tp->t_state, TS_FLUSH); 1102 ch->ch_obuf_size = 0; 1103 } 1104 splx(s); 1105 } 1106 1107 /* 1108 * RX interrupt routine 1109 */ 1110 int 1111 clmpcc_rxintr(arg) 1112 void *arg; 1113 { 1114 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1115 struct clmpcc_chan *ch; 1116 u_int8_t *put, *end, rxd; 1117 u_char errstat; 1118 u_char fc, tc; 1119 u_char risr; 1120 u_char rir; 1121 #ifdef DDB 1122 int saw_break = 0; 1123 #endif 1124 1125 /* Receive interrupt active? */ 1126 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1127 1128 /* 1129 * If we're using auto-vectored interrupts, we have to 1130 * verify if the chip is generating the interrupt. 1131 */ 1132 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1133 return 0; 1134 1135 /* Get pointer to interrupting channel's data structure */ 1136 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1137 1138 /* Get the interrupt status register */ 1139 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1140 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1141 u_char reg; 1142 /* 1143 * Set the FIFO threshold to zero, and disable 1144 * further receive timeout interrupts. 1145 */ 1146 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1147 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1148 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1149 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1150 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1151 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1152 return 1; 1153 } 1154 1155 /* How many bytes are waiting in the FIFO? */ 1156 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1157 1158 #ifdef DDB 1159 /* 1160 * Allow BREAK on the console to drop to the debugger. 1161 */ 1162 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1163 risr & CLMPCC_RISR_BREAK ) { 1164 saw_break = 1; 1165 } 1166 #endif 1167 1168 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1169 /* Just get rid of the data */ 1170 while ( fc-- ) 1171 (void) clmpcc_rd_rxdata(sc); 1172 goto rx_done; 1173 } 1174 1175 put = ch->ch_ibuf_wr; 1176 end = ch->ch_ibuf_end; 1177 1178 /* 1179 * Note: The chip is completely hosed WRT these error 1180 * conditions; there seems to be no way to associate 1181 * the error with the correct character in the FIFO. 1182 * We compromise by tagging the first character we read 1183 * with the error. Not perfect, but there's no other way. 1184 */ 1185 errstat = 0; 1186 if ( risr & CLMPCC_RISR_PARITY ) 1187 errstat |= TTY_PE; 1188 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1189 errstat |= TTY_FE; 1190 1191 /* 1192 * As long as there are characters in the FIFO, and we 1193 * have space for them... 1194 */ 1195 while ( fc > 0 ) { 1196 1197 *put++ = rxd = clmpcc_rd_rxdata(sc); 1198 *put++ = errstat; 1199 1200 if ( put >= end ) 1201 put = ch->ch_ibuf; 1202 1203 if ( put == ch->ch_ibuf_rd ) { 1204 put -= 2; 1205 if ( put < ch->ch_ibuf ) 1206 put = end - 2; 1207 } 1208 1209 errstat = 0; 1210 fc--; 1211 } 1212 1213 ch->ch_ibuf_wr = put; 1214 1215 #if 0 1216 if ( sc->sc_swaprtsdtr == 0 && 1217 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1218 /* 1219 * If RTS/DTR are not physically swapped, we have to 1220 * do hardware flow control manually 1221 */ 1222 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1223 } 1224 #endif 1225 1226 rx_done: 1227 if ( fc != tc ) { 1228 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1229 u_char reg; 1230 /* 1231 * Set the FIFO threshold to the preset value, 1232 * and enable receive timeout interrupts. 1233 */ 1234 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1235 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1236 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1237 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1238 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1239 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1240 } 1241 1242 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1243 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1244 if ( sc->sc_soft_running == 0 ) { 1245 sc->sc_soft_running = 1; 1246 (sc->sc_softhook)(sc); 1247 } 1248 #else 1249 softintr_schedule(sc->sc_softintr_cookie); 1250 #endif 1251 } else 1252 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1253 1254 #ifdef DDB 1255 /* 1256 * Only =after= we write REOIR is it safe to drop to the debugger. 1257 */ 1258 if ( saw_break ) 1259 Debugger(); 1260 #endif 1261 1262 return 1; 1263 } 1264 1265 /* 1266 * Tx interrupt routine 1267 */ 1268 int 1269 clmpcc_txintr(arg) 1270 void *arg; 1271 { 1272 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1273 struct clmpcc_chan *ch; 1274 struct tty *tp; 1275 u_char ftc, oftc; 1276 u_char tir, teoir; 1277 int etcmode = 0; 1278 1279 /* Tx interrupt active? */ 1280 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1281 1282 /* 1283 * If we're using auto-vectored interrupts, we have to 1284 * verify if the chip is generating the interrupt. 1285 */ 1286 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1287 return 0; 1288 1289 /* Get pointer to interrupting channel's data structure */ 1290 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1291 tp = ch->ch_tty; 1292 1293 /* Dummy read of the interrupt status register */ 1294 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1295 1296 /* Make sure embedded transmit commands are disabled */ 1297 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1298 1299 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1300 1301 /* Handle a delayed parameter change */ 1302 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1303 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1304 clmpcc_set_params(ch); 1305 } 1306 1307 if ( ch->ch_obuf_size > 0 ) { 1308 u_int n = min(ch->ch_obuf_size, ftc); 1309 1310 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1311 1312 ftc -= n; 1313 ch->ch_obuf_size -= n; 1314 ch->ch_obuf_addr += n; 1315 1316 } else { 1317 /* 1318 * Check if we should start/stop a break 1319 */ 1320 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1321 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1322 /* Enable embedded transmit commands */ 1323 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1324 ch->ch_cor2 | CLMPCC_COR2_ETC); 1325 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1326 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1327 ftc -= 2; 1328 etcmode = 1; 1329 } 1330 1331 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1332 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1333 /* Enable embedded transmit commands */ 1334 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1335 ch->ch_cor2 | CLMPCC_COR2_ETC); 1336 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1337 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1338 ftc -= 2; 1339 etcmode = 1; 1340 } 1341 } 1342 1343 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1344 1345 if ( ftc != oftc ) { 1346 /* 1347 * Enable/disable the Tx FIFO threshold interrupt 1348 * according to how much data is in the FIFO. 1349 * However, always disable the FIFO threshold if 1350 * we've left the channel in 'Embedded Transmit 1351 * Command' mode. 1352 */ 1353 if ( etcmode || ftc >= ch->ch_cor4 ) 1354 tir &= ~CLMPCC_IER_TX_FIFO; 1355 else 1356 tir |= CLMPCC_IER_TX_FIFO; 1357 teoir = 0; 1358 } else { 1359 /* 1360 * No data was sent. 1361 * Disable transmit interrupt. 1362 */ 1363 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1364 teoir = CLMPCC_TEOIR_NO_TRANS; 1365 1366 /* 1367 * Request Tx processing in the soft interrupt handler 1368 */ 1369 ch->ch_tx_done = 1; 1370 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1371 if ( sc->sc_soft_running == 0 ) { 1372 sc->sc_soft_running = 1; 1373 (sc->sc_softhook)(sc); 1374 } 1375 #else 1376 softintr_schedule(sc->sc_softintr_cookie); 1377 #endif 1378 } 1379 1380 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1381 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1382 1383 return 1; 1384 } 1385 1386 /* 1387 * Modem change interrupt routine 1388 */ 1389 int 1390 clmpcc_mdintr(arg) 1391 void *arg; 1392 { 1393 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1394 u_char mir; 1395 1396 /* Modem status interrupt active? */ 1397 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1398 1399 /* 1400 * If we're using auto-vectored interrupts, we have to 1401 * verify if the chip is generating the interrupt. 1402 */ 1403 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1404 return 0; 1405 1406 /* Dummy read of the interrupt status register */ 1407 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1408 1409 /* Retrieve current status of modem lines. */ 1410 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1411 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1412 1413 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1414 1415 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1416 if ( sc->sc_soft_running == 0 ) { 1417 sc->sc_soft_running = 1; 1418 (sc->sc_softhook)(sc); 1419 } 1420 #else 1421 softintr_schedule(sc->sc_softintr_cookie); 1422 #endif 1423 1424 return 1; 1425 } 1426 1427 void 1428 clmpcc_softintr(arg) 1429 void *arg; 1430 { 1431 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1432 struct clmpcc_chan *ch; 1433 struct tty *tp; 1434 int (*rint) __P((int, struct tty *)); 1435 u_char *get; 1436 u_char reg; 1437 u_int c; 1438 int chan; 1439 1440 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1441 sc->sc_soft_running = 0; 1442 #endif 1443 1444 /* Handle Modem state changes too... */ 1445 1446 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1447 ch = &sc->sc_chans[chan]; 1448 tp = ch->ch_tty; 1449 1450 get = ch->ch_ibuf_rd; 1451 rint = tp->t_linesw->l_rint; 1452 1453 /* Squirt buffered incoming data into the tty layer */ 1454 while ( get != ch->ch_ibuf_wr ) { 1455 c = get[0]; 1456 c |= ((u_int)get[1]) << 8; 1457 if ( (rint)(c, tp) == -1 ) { 1458 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1459 break; 1460 } 1461 1462 get += 2; 1463 if ( get == ch->ch_ibuf_end ) 1464 get = ch->ch_ibuf; 1465 1466 ch->ch_ibuf_rd = get; 1467 } 1468 1469 /* 1470 * Is the transmitter idle and in need of attention? 1471 */ 1472 if ( ch->ch_tx_done ) { 1473 ch->ch_tx_done = 0; 1474 1475 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1476 clmpcc_channel_cmd(sc, ch->ch_car, 1477 CLMPCC_CCR_T0_INIT | 1478 CLMPCC_CCR_T0_RX_EN | 1479 CLMPCC_CCR_T0_TX_EN); 1480 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1481 1482 /* 1483 * Allow time for the channel to initialise. 1484 * (Empirically derived duration; there must 1485 * be another way to determine the command 1486 * has completed without busy-waiting...) 1487 */ 1488 delay(800); 1489 1490 /* 1491 * Update the tty layer's idea of the carrier 1492 * bit, in case we changed CLOCAL or MDMBUF. 1493 * We don't hang up here; we only do that by 1494 * explicit request. 1495 */ 1496 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1497 (*tp->t_linesw->l_modem)(tp, reg != 0); 1498 } 1499 1500 CLR(tp->t_state, TS_BUSY); 1501 if ( ISSET(tp->t_state, TS_FLUSH) ) 1502 CLR(tp->t_state, TS_FLUSH); 1503 else 1504 ndflush(&tp->t_outq, 1505 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1506 1507 (*tp->t_linesw->l_start)(tp); 1508 } 1509 } 1510 } 1511 1512 1513 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1514 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1515 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1516 /* 1517 * Following are all routines needed for a cd240x channel to act as console 1518 */ 1519 int 1520 clmpcc_cnattach(sc, chan, rate) 1521 struct clmpcc_softc *sc; 1522 int chan; 1523 int rate; 1524 { 1525 cons_sc = sc; 1526 cons_chan = chan; 1527 cons_rate = rate; 1528 1529 return (clmpcc_init(sc)); 1530 } 1531 1532 /* 1533 * The following functions are polled getc and putc routines, for console use. 1534 */ 1535 static int 1536 clmpcc_common_getc(sc, chan) 1537 struct clmpcc_softc *sc; 1538 int chan; 1539 { 1540 u_char old_chan; 1541 u_char old_ier; 1542 u_char ch, rir, risr; 1543 int s; 1544 1545 s = splhigh(); 1546 1547 /* Save the currently active channel */ 1548 old_chan = clmpcc_select_channel(sc, chan); 1549 1550 /* 1551 * We have to put the channel into RX interrupt mode before 1552 * trying to read the Rx data register. So save the previous 1553 * interrupt mode. 1554 */ 1555 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1556 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1557 1558 /* Loop until we get a character */ 1559 for (;;) { 1560 /* 1561 * The REN bit will be set in the Receive Interrupt Register 1562 * when the CD240x has a character to process. Remember, 1563 * the RACT bit won't be set until we generate an interrupt 1564 * acknowledge cycle via the MD front-end. 1565 */ 1566 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1567 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1568 continue; 1569 1570 /* Acknowledge the request */ 1571 if ( sc->sc_iackhook ) 1572 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1573 1574 /* 1575 * Determine if the interrupt is for the required channel 1576 * and if valid data is available. 1577 */ 1578 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1579 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1580 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1581 risr != 0 ) { 1582 /* Rx error, or BREAK */ 1583 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1584 CLMPCC_REOIR_NO_TRANS); 1585 } else { 1586 /* Dummy read of the FIFO count register */ 1587 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1588 1589 /* Fetch the received character */ 1590 ch = clmpcc_rd_rxdata(sc); 1591 1592 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1593 break; 1594 } 1595 } 1596 1597 /* Restore the original IER and CAR register contents */ 1598 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1599 clmpcc_select_channel(sc, old_chan); 1600 1601 splx(s); 1602 return ch; 1603 } 1604 1605 1606 static void 1607 clmpcc_common_putc(sc, chan, c) 1608 struct clmpcc_softc *sc; 1609 int chan; 1610 int c; 1611 { 1612 u_char old_chan; 1613 int s = splhigh(); 1614 1615 /* Save the currently active channel */ 1616 old_chan = clmpcc_select_channel(sc, chan); 1617 1618 /* 1619 * Since we can only access the Tx Data register from within 1620 * the interrupt handler, the easiest way to get console data 1621 * onto the wire is using one of the Special Transmit Character 1622 * registers. 1623 */ 1624 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1625 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1626 CLMPCC_STCR_SND_SPC); 1627 1628 /* Wait until the "Send Special Character" command is accepted */ 1629 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1630 ; 1631 1632 /* Restore the previous channel selected */ 1633 clmpcc_select_channel(sc, old_chan); 1634 1635 splx(s); 1636 } 1637 1638 int 1639 clmpcccngetc(dev) 1640 dev_t dev; 1641 { 1642 return clmpcc_common_getc(cons_sc, cons_chan); 1643 } 1644 1645 /* 1646 * Console kernel output character routine. 1647 */ 1648 void 1649 clmpcccnputc(dev, c) 1650 dev_t dev; 1651 int c; 1652 { 1653 if ( c == '\n' ) 1654 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1655 1656 clmpcc_common_putc(cons_sc, cons_chan, c); 1657 } 1658