1 /* $NetBSD: clmpcc.c,v 1.42 2009/03/14 21:04:19 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.42 2009/03/14 21:04:19 dsl Exp $"); 38 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ioctl.h> 44 #include <sys/select.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/conf.h> 49 #include <sys/file.h> 50 #include <sys/uio.h> 51 #include <sys/kernel.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/kauth.h> 56 #include <sys/intr.h> 57 58 #include <sys/bus.h> 59 #include <machine/param.h> 60 61 #include <dev/ic/clmpccreg.h> 62 #include <dev/ic/clmpccvar.h> 63 #include <dev/cons.h> 64 65 66 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 67 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 68 #endif 69 70 71 static int clmpcc_init(struct clmpcc_softc *sc); 72 static void clmpcc_shutdown(struct clmpcc_chan *); 73 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *); 74 static int clmpcc_param(struct tty *, struct termios *); 75 static void clmpcc_set_params(struct clmpcc_chan *); 76 static void clmpcc_start(struct tty *); 77 static int clmpcc_modem_control(struct clmpcc_chan *, int, int); 78 79 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 80 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 81 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 82 83 /* 84 * These should be in a header file somewhere... 85 */ 86 #define ISCLR(v, f) (((v) & (f)) == 0) 87 88 extern struct cfdriver clmpcc_cd; 89 90 dev_type_open(clmpccopen); 91 dev_type_close(clmpccclose); 92 dev_type_read(clmpccread); 93 dev_type_write(clmpccwrite); 94 dev_type_ioctl(clmpccioctl); 95 dev_type_stop(clmpccstop); 96 dev_type_tty(clmpcctty); 97 dev_type_poll(clmpccpoll); 98 99 const struct cdevsw clmpcc_cdevsw = { 100 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl, 101 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY 102 }; 103 104 /* 105 * Make this an option variable one can patch. 106 */ 107 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 108 109 110 /* 111 * Things needed when the device is used as a console 112 */ 113 static struct clmpcc_softc *cons_sc = NULL; 114 static int cons_chan; 115 static int cons_rate; 116 117 static int clmpcc_common_getc(struct clmpcc_softc *, int); 118 static void clmpcc_common_putc(struct clmpcc_softc *, int, int); 119 int clmpcccngetc(dev_t); 120 void clmpcccnputc(dev_t, int); 121 122 123 /* 124 * Convenience functions, inlined for speed 125 */ 126 #define integrate static inline 127 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int); 128 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int); 129 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int); 130 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int); 131 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *, 132 u_int); 133 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int); 134 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int); 135 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *); 136 137 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 138 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 139 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 140 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 141 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 142 143 144 integrate u_int8_t 145 clmpcc_rdreg(struct clmpcc_softc *sc, u_int offset) 146 { 147 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 148 offset ^= sc->sc_byteswap; 149 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 150 offset ^= CLMPCC_BYTESWAP_HIGH; 151 #endif 152 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 153 } 154 155 integrate void 156 clmpcc_wrreg(struct clmpcc_softc *sc, u_int offset, u_int val) 157 { 158 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 159 offset ^= sc->sc_byteswap; 160 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 161 offset ^= CLMPCC_BYTESWAP_HIGH; 162 #endif 163 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 164 } 165 166 integrate u_int8_t 167 clmpcc_rdreg_odd(struct clmpcc_softc *sc, u_int offset) 168 { 169 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 170 offset ^= (sc->sc_byteswap & 2); 171 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 172 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 173 #endif 174 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 175 } 176 177 integrate void 178 clmpcc_wrreg_odd(struct clmpcc_softc *sc, u_int offset, u_int val) 179 { 180 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 181 offset ^= (sc->sc_byteswap & 2); 182 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 183 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 184 #endif 185 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 186 } 187 188 integrate void 189 clmpcc_wrtx_multi(struct clmpcc_softc *sc, u_int8_t *buff, u_int count) 190 { 191 u_int offset = CLMPCC_REG_TDR; 192 193 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 194 offset ^= (sc->sc_byteswap & 2); 195 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 196 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 197 #endif 198 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 199 } 200 201 integrate u_int8_t 202 clmpcc_select_channel(struct clmpcc_softc *sc, u_int new_chan) 203 { 204 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 205 206 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 207 208 return old_chan; 209 } 210 211 integrate void 212 clmpcc_channel_cmd(struct clmpcc_softc *sc, int chan, int cmd) 213 { 214 int i; 215 216 for (i = 5000; i; i--) { 217 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 218 break; 219 delay(1); 220 } 221 222 if ( i == 0 ) 223 printf("%s: channel %d command timeout (idle)\n", 224 device_xname(&sc->sc_dev), chan); 225 226 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 227 } 228 229 integrate void 230 clmpcc_enable_transmitter(struct clmpcc_chan *ch) 231 { 232 u_int old; 233 int s; 234 235 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 236 237 s = splserial(); 238 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 239 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 240 SET(ch->ch_tty->t_state, TS_BUSY); 241 splx(s); 242 243 clmpcc_select_channel(ch->ch_sc, old); 244 } 245 246 static int 247 clmpcc_speed(struct clmpcc_softc *sc, speed_t speed, int *cor, int *bpr) 248 { 249 int c, co, br; 250 251 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 252 br = ((sc->sc_clk / c) / speed) - 1; 253 if ( br < 0x100 ) { 254 *cor = co; 255 *bpr = br; 256 return 0; 257 } 258 } 259 260 return -1; 261 } 262 263 void 264 clmpcc_attach(struct clmpcc_softc *sc) 265 { 266 struct clmpcc_chan *ch; 267 struct tty *tp; 268 int chan; 269 270 if ( cons_sc != NULL && 271 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 272 cons_sc = sc; 273 274 /* Initialise the chip */ 275 clmpcc_init(sc); 276 277 printf(": Cirrus Logic CD240%c Serial Controller\n", 278 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 279 280 sc->sc_softintr_cookie = 281 softint_establish(SOFTINT_SERIAL, clmpcc_softintr, sc); 282 if (sc->sc_softintr_cookie == NULL) 283 panic("clmpcc_attach: softintr_establish"); 284 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 285 286 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 287 ch = &sc->sc_chans[chan]; 288 289 ch->ch_sc = sc; 290 ch->ch_car = chan; 291 292 tp = ttymalloc(); 293 tp->t_oproc = clmpcc_start; 294 tp->t_param = clmpcc_param; 295 296 ch->ch_tty = tp; 297 298 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 299 if ( ch->ch_ibuf == NULL ) { 300 aprint_error_dev(&sc->sc_dev, "(%d): unable to allocate ring buffer\n", 301 chan); 302 return; 303 } 304 305 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 306 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 307 308 tty_attach(tp); 309 } 310 311 aprint_error_dev(&sc->sc_dev, "%d channels available", 312 CLMPCC_NUM_CHANS); 313 if ( cons_sc == sc ) { 314 printf(", console on channel %d.\n", cons_chan); 315 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 316 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 317 } else 318 printf(".\n"); 319 } 320 321 static int 322 clmpcc_init(struct clmpcc_softc *sc) 323 { 324 u_int tcor, tbpr; 325 u_int rcor, rbpr; 326 u_int msvr_rts, msvr_dtr; 327 u_int ccr; 328 int is_console; 329 int i; 330 331 /* 332 * All we're really concerned about here is putting the chip 333 * into a quiescent state so that it won't do anything until 334 * clmpccopen() is called. (Except the console channel.) 335 */ 336 337 /* 338 * If the chip is acting as console, set all channels to the supplied 339 * console baud rate. Otherwise, plump for 9600. 340 */ 341 if ( cons_sc && 342 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 343 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 344 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 345 is_console = 1; 346 } else { 347 clmpcc_speed(sc, 9600, &tcor, &tbpr); 348 clmpcc_speed(sc, 9600, &rcor, &rbpr); 349 is_console = 0; 350 } 351 352 /* Allow any pending output to be sent */ 353 delay(10000); 354 355 /* Send the Reset All command to channel 0 (resets all channels!) */ 356 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 357 358 delay(1000); 359 360 /* 361 * The chip will set it's firmware revision register to a non-zero 362 * value to indicate completion of reset. 363 */ 364 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 365 delay(1); 366 367 if ( i == 0 ) { 368 /* 369 * Watch out... If this chip is console, the message 370 * probably won't be sent since we just reset it! 371 */ 372 aprint_error_dev(&sc->sc_dev, "Failed to reset chip\n"); 373 return -1; 374 } 375 376 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 377 clmpcc_select_channel(sc, i); 378 379 /* All interrupts are disabled to begin with */ 380 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 381 382 /* Make sure the channel interrupts on the correct vectors */ 383 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 384 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 385 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 386 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 387 388 /* Receive timer prescaler set to 1ms */ 389 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 390 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 391 392 /* We support Async mode only */ 393 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 394 395 /* Set the required baud rate */ 396 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 397 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 398 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 399 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 400 401 /* Always default to 8N1 (XXX what about console?) */ 402 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 403 CLMPCC_COR1_NO_PARITY | 404 CLMPCC_COR1_IGNORE_PAR); 405 406 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 407 408 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 409 410 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 411 CLMPCC_COR4_CDzd | 412 CLMPCC_COR4_CTSzd); 413 414 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 415 CLMPCC_COR5_CDod | 416 CLMPCC_COR5_CTSod | 417 CLMPCC_COR5_FLOW_NORM); 418 419 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 420 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 421 422 /* Set the receive FIFO timeout */ 423 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 424 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 425 426 /* At this point, we set up the console differently */ 427 if ( is_console && i == cons_chan ) { 428 msvr_rts = CLMPCC_MSVR_RTS; 429 msvr_dtr = CLMPCC_MSVR_DTR; 430 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 431 } else { 432 msvr_rts = 0; 433 msvr_dtr = 0; 434 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 435 } 436 437 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 438 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 439 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 440 delay(100); 441 } 442 443 return 0; 444 } 445 446 static void 447 clmpcc_shutdown(struct clmpcc_chan *ch) 448 { 449 int oldch; 450 451 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 452 453 /* Turn off interrupts. */ 454 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 455 456 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 457 /* Disable the transmitter and receiver */ 458 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 459 CLMPCC_CCR_T0_TX_DIS); 460 461 /* Drop RTS and DTR */ 462 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 463 } 464 465 clmpcc_select_channel(ch->ch_sc, oldch); 466 } 467 468 int 469 clmpccopen(dev_t dev, int flag, int mode, struct lwp *l) 470 { 471 struct clmpcc_softc *sc; 472 struct clmpcc_chan *ch; 473 struct tty *tp; 474 int oldch; 475 int error; 476 477 sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 478 if (sc == NULL) 479 return (ENXIO); 480 481 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 482 483 tp = ch->ch_tty; 484 485 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 486 return EBUSY; 487 488 /* 489 * Do the following iff this is a first open. 490 */ 491 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 492 493 ttychars(tp); 494 495 tp->t_dev = dev; 496 tp->t_iflag = TTYDEF_IFLAG; 497 tp->t_oflag = TTYDEF_OFLAG; 498 tp->t_lflag = TTYDEF_LFLAG; 499 tp->t_cflag = TTYDEF_CFLAG; 500 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 501 502 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 503 SET(tp->t_cflag, CLOCAL); 504 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 505 SET(tp->t_cflag, CRTSCTS); 506 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 507 SET(tp->t_cflag, MDMBUF); 508 509 /* 510 * Override some settings if the channel is being 511 * used as the console. 512 */ 513 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 514 tp->t_ospeed = tp->t_ispeed = cons_rate; 515 SET(tp->t_cflag, CLOCAL); 516 CLR(tp->t_cflag, CRTSCTS); 517 CLR(tp->t_cflag, HUPCL); 518 } 519 520 ch->ch_control = 0; 521 522 clmpcc_param(tp, &tp->t_termios); 523 ttsetwater(tp); 524 525 /* Clear the input ring */ 526 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 527 528 /* Select the channel */ 529 oldch = clmpcc_select_channel(sc, ch->ch_car); 530 531 /* Reset it */ 532 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 533 CLMPCC_CCR_T0_RX_EN | 534 CLMPCC_CCR_T0_TX_EN); 535 536 /* Enable receiver and modem change interrupts. */ 537 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 538 CLMPCC_IER_RET | 539 CLMPCC_IER_RX_FIFO); 540 541 /* Raise RTS and DTR */ 542 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 543 544 clmpcc_select_channel(sc, oldch); 545 } 546 547 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 548 if (error) 549 goto bad; 550 551 error = (*tp->t_linesw->l_open)(dev, tp); 552 if (error) 553 goto bad; 554 555 return 0; 556 557 bad: 558 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 559 /* 560 * We failed to open the device, and nobody else had it opened. 561 * Clean up the state as appropriate. 562 */ 563 clmpcc_shutdown(ch); 564 } 565 566 return error; 567 } 568 569 int 570 clmpccclose(dev_t dev, int flag, int mode, struct lwp *l) 571 { 572 struct clmpcc_softc *sc = 573 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 574 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 575 struct tty *tp = ch->ch_tty; 576 int s; 577 578 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 579 return 0; 580 581 (*tp->t_linesw->l_close)(tp, flag); 582 583 s = spltty(); 584 585 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 586 /* 587 * Although we got a last close, the device may still be in 588 * use; e.g. if this was the dialout node, and there are still 589 * processes waiting for carrier on the non-dialout node. 590 */ 591 clmpcc_shutdown(ch); 592 } 593 594 ttyclose(tp); 595 596 splx(s); 597 598 return 0; 599 } 600 601 int 602 clmpccread(dev_t dev, struct uio *uio, int flag) 603 { 604 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 605 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 606 607 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 608 } 609 610 int 611 clmpccwrite(dev_t dev, struct uio *uio, int flag) 612 { 613 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 614 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 615 616 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 617 } 618 619 int 620 clmpccpoll(dev_t dev, int events, struct lwp *l) 621 { 622 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 623 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 624 625 return ((*tp->t_linesw->l_poll)(tp, events, l)); 626 } 627 628 struct tty * 629 clmpcctty(dev_t dev) 630 { 631 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 632 633 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 634 } 635 636 int 637 clmpccioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 638 { 639 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 640 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 641 struct tty *tp = ch->ch_tty; 642 int error; 643 644 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 645 if (error != EPASSTHROUGH) 646 return error; 647 648 error = ttioctl(tp, cmd, data, flag, l); 649 if (error != EPASSTHROUGH) 650 return error; 651 652 error = 0; 653 654 switch (cmd) { 655 case TIOCSBRK: 656 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 657 clmpcc_enable_transmitter(ch); 658 break; 659 660 case TIOCCBRK: 661 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 662 clmpcc_enable_transmitter(ch); 663 break; 664 665 case TIOCSDTR: 666 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 667 break; 668 669 case TIOCCDTR: 670 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 671 break; 672 673 case TIOCMSET: 674 clmpcc_modem_control(ch, *((int *)data), DMSET); 675 break; 676 677 case TIOCMBIS: 678 clmpcc_modem_control(ch, *((int *)data), DMBIS); 679 break; 680 681 case TIOCMBIC: 682 clmpcc_modem_control(ch, *((int *)data), DMBIC); 683 break; 684 685 case TIOCMGET: 686 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 687 break; 688 689 case TIOCGFLAGS: 690 *((int *)data) = ch->ch_openflags; 691 break; 692 693 case TIOCSFLAGS: 694 error = kauth_authorize_device_tty(l->l_cred, 695 KAUTH_DEVICE_TTY_PRIVSET, tp); 696 if ( error ) 697 break; 698 ch->ch_openflags = *((int *)data) & 699 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 700 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 701 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 702 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 703 break; 704 705 default: 706 error = EPASSTHROUGH; 707 break; 708 } 709 710 return error; 711 } 712 713 int 714 clmpcc_modem_control(struct clmpcc_chan *ch, int bits, int howto) 715 { 716 struct clmpcc_softc *sc = ch->ch_sc; 717 struct tty *tp = ch->ch_tty; 718 int oldch; 719 int msvr; 720 int rbits = 0; 721 722 oldch = clmpcc_select_channel(sc, ch->ch_car); 723 724 switch ( howto ) { 725 case DMGET: 726 msvr = clmpcc_rd_msvr(sc); 727 728 if ( sc->sc_swaprtsdtr ) { 729 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 730 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 731 } else { 732 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 733 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 734 } 735 736 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 737 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 738 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 739 break; 740 741 case DMSET: 742 if ( sc->sc_swaprtsdtr ) { 743 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 744 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 745 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 746 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 747 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 748 } else { 749 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 750 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 751 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 752 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 753 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 754 } 755 break; 756 757 case DMBIS: 758 if ( sc->sc_swaprtsdtr ) { 759 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 760 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 761 if ( ISSET(bits, TIOCM_DTR) ) 762 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 763 } else { 764 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 765 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 766 if ( ISSET(bits, TIOCM_DTR) ) 767 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 768 } 769 break; 770 771 case DMBIC: 772 if ( sc->sc_swaprtsdtr ) { 773 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 774 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 775 if ( ISCLR(bits, TIOCM_DTR) ) 776 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 777 } else { 778 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 779 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 780 if ( ISCLR(bits, TIOCM_DTR) ) 781 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 782 } 783 break; 784 } 785 786 clmpcc_select_channel(sc, oldch); 787 788 return rbits; 789 } 790 791 static int 792 clmpcc_param(struct tty *tp, struct termios *t) 793 { 794 struct clmpcc_softc *sc = 795 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 796 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 797 u_char cor; 798 u_char oldch; 799 int oclk, obpr; 800 int iclk, ibpr; 801 int s; 802 803 /* Check requested parameters. */ 804 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 805 return EINVAL; 806 807 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 808 return EINVAL; 809 810 /* 811 * For the console, always force CLOCAL and !HUPCL, so that the port 812 * is always active. 813 */ 814 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 815 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 816 SET(t->c_cflag, CLOCAL); 817 CLR(t->c_cflag, HUPCL); 818 } 819 820 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 821 822 /* If ospeed it zero, hangup the line */ 823 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 824 825 if ( t->c_ospeed ) { 826 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 827 ch->ch_tbpr = obpr; 828 } else { 829 ch->ch_tcor = 0; 830 ch->ch_tbpr = 0; 831 } 832 833 if ( t->c_ispeed ) { 834 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 835 ch->ch_rbpr = ibpr; 836 } else { 837 ch->ch_rcor = 0; 838 ch->ch_rbpr = 0; 839 } 840 841 /* Work out value to use for COR1 */ 842 cor = 0; 843 if ( ISSET(t->c_cflag, PARENB) ) { 844 cor |= CLMPCC_COR1_NORM_PARITY; 845 if ( ISSET(t->c_cflag, PARODD) ) 846 cor |= CLMPCC_COR1_ODD_PARITY; 847 } 848 849 if ( ISCLR(t->c_cflag, INPCK) ) 850 cor |= CLMPCC_COR1_IGNORE_PAR; 851 852 switch ( t->c_cflag & CSIZE ) { 853 case CS5: 854 cor |= CLMPCC_COR1_CHAR_5BITS; 855 break; 856 857 case CS6: 858 cor |= CLMPCC_COR1_CHAR_6BITS; 859 break; 860 861 case CS7: 862 cor |= CLMPCC_COR1_CHAR_7BITS; 863 break; 864 865 case CS8: 866 cor |= CLMPCC_COR1_CHAR_8BITS; 867 break; 868 } 869 870 ch->ch_cor1 = cor; 871 872 /* 873 * The only interesting bit in COR2 is 'CTS Automatic Enable' 874 * when hardware flow control is in effect. 875 */ 876 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 877 878 /* COR3 needs to be set to the number of stop bits... */ 879 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 880 CLMPCC_COR3_STOP_1; 881 882 /* 883 * COR4 contains the FIFO threshold setting. 884 * We adjust the threshold depending on the input speed... 885 */ 886 if ( t->c_ispeed <= 1200 ) 887 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 888 else if ( t->c_ispeed <= 19200 ) 889 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 890 else 891 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 892 893 /* 894 * If chip is used with CTS and DTR swapped, we can enable 895 * automatic hardware flow control. 896 */ 897 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 898 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 899 else 900 ch->ch_cor5 = 0; 901 902 s = splserial(); 903 oldch = clmpcc_select_channel(sc, ch->ch_car); 904 905 /* 906 * COR2 needs to be set immediately otherwise we might never get 907 * a Tx EMPTY interrupt to change the other parameters. 908 */ 909 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 910 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 911 912 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 913 clmpcc_set_params(ch); 914 else 915 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 916 917 clmpcc_select_channel(sc, oldch); 918 919 splx(s); 920 921 return 0; 922 } 923 924 static void 925 clmpcc_set_params(struct clmpcc_chan *ch) 926 { 927 struct clmpcc_softc *sc = ch->ch_sc; 928 u_char r1; 929 u_char r2; 930 931 if ( ch->ch_tcor || ch->ch_tbpr ) { 932 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 933 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 934 /* Only write Tx rate if it really has changed */ 935 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 936 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 937 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 938 } 939 } 940 941 if ( ch->ch_rcor || ch->ch_rbpr ) { 942 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 943 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 944 /* Only write Rx rate if it really has changed */ 945 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 946 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 947 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 948 } 949 } 950 951 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 952 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 953 /* Any change to COR1 requires an INIT command */ 954 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 955 } 956 957 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 958 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 959 960 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 961 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 962 /* 963 * Note: If the FIFO has changed, we always set it to 964 * zero here and disable the Receive Timeout interrupt. 965 * It's up to the Rx Interrupt handler to pick the 966 * appropriate moment to write the new FIFO length. 967 */ 968 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 969 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 970 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 971 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 972 } 973 974 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 975 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 976 r1 &= ~CLMPCC_COR5_FLOW_MASK; 977 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 978 } 979 } 980 981 static void 982 clmpcc_start(struct tty *tp) 983 { 984 struct clmpcc_softc *sc = 985 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 986 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 987 u_int oldch; 988 int s; 989 990 s = spltty(); 991 992 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 993 ttypull(tp); 994 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 995 CLMPCC_FLG_END_BREAK) || 996 tp->t_outq.c_cc > 0 ) { 997 998 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 999 CLMPCC_FLG_END_BREAK) ) { 1000 ch->ch_obuf_addr = tp->t_outq.c_cf; 1001 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1002 } 1003 1004 /* Enable TX empty interrupts */ 1005 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1006 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1007 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1008 CLMPCC_IER_TX_EMPTY); 1009 clmpcc_select_channel(ch->ch_sc, oldch); 1010 SET(tp->t_state, TS_BUSY); 1011 } 1012 } 1013 1014 splx(s); 1015 } 1016 1017 /* 1018 * Stop output on a line. 1019 */ 1020 void 1021 clmpccstop(struct tty *tp, int flag) 1022 { 1023 struct clmpcc_softc *sc = 1024 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1025 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1026 int s; 1027 1028 s = splserial(); 1029 1030 if ( ISSET(tp->t_state, TS_BUSY) ) { 1031 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1032 SET(tp->t_state, TS_FLUSH); 1033 ch->ch_obuf_size = 0; 1034 } 1035 splx(s); 1036 } 1037 1038 /* 1039 * RX interrupt routine 1040 */ 1041 int 1042 clmpcc_rxintr(void *arg) 1043 { 1044 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1045 struct clmpcc_chan *ch; 1046 u_int8_t *put, *end, rxd; 1047 u_char errstat; 1048 u_char fc, tc; 1049 u_char risr; 1050 u_char rir; 1051 #ifdef DDB 1052 int saw_break = 0; 1053 #endif 1054 1055 /* Receive interrupt active? */ 1056 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1057 1058 /* 1059 * If we're using auto-vectored interrupts, we have to 1060 * verify if the chip is generating the interrupt. 1061 */ 1062 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1063 return 0; 1064 1065 /* Get pointer to interrupting channel's data structure */ 1066 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1067 1068 /* Get the interrupt status register */ 1069 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1070 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1071 u_char reg; 1072 /* 1073 * Set the FIFO threshold to zero, and disable 1074 * further receive timeout interrupts. 1075 */ 1076 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1077 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1078 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1079 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1080 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1081 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1082 return 1; 1083 } 1084 1085 /* How many bytes are waiting in the FIFO? */ 1086 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1087 1088 #ifdef DDB 1089 /* 1090 * Allow BREAK on the console to drop to the debugger. 1091 */ 1092 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1093 risr & CLMPCC_RISR_BREAK ) { 1094 saw_break = 1; 1095 } 1096 #endif 1097 1098 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1099 /* Just get rid of the data */ 1100 while ( fc-- ) 1101 (void) clmpcc_rd_rxdata(sc); 1102 goto rx_done; 1103 } 1104 1105 put = ch->ch_ibuf_wr; 1106 end = ch->ch_ibuf_end; 1107 1108 /* 1109 * Note: The chip is completely hosed WRT these error 1110 * conditions; there seems to be no way to associate 1111 * the error with the correct character in the FIFO. 1112 * We compromise by tagging the first character we read 1113 * with the error. Not perfect, but there's no other way. 1114 */ 1115 errstat = 0; 1116 if ( risr & CLMPCC_RISR_PARITY ) 1117 errstat |= TTY_PE; 1118 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1119 errstat |= TTY_FE; 1120 1121 /* 1122 * As long as there are characters in the FIFO, and we 1123 * have space for them... 1124 */ 1125 while ( fc > 0 ) { 1126 1127 *put++ = rxd = clmpcc_rd_rxdata(sc); 1128 *put++ = errstat; 1129 1130 if ( put >= end ) 1131 put = ch->ch_ibuf; 1132 1133 if ( put == ch->ch_ibuf_rd ) { 1134 put -= 2; 1135 if ( put < ch->ch_ibuf ) 1136 put = end - 2; 1137 } 1138 1139 errstat = 0; 1140 fc--; 1141 } 1142 1143 ch->ch_ibuf_wr = put; 1144 1145 #if 0 1146 if ( sc->sc_swaprtsdtr == 0 && 1147 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1148 /* 1149 * If RTS/DTR are not physically swapped, we have to 1150 * do hardware flow control manually 1151 */ 1152 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1153 } 1154 #endif 1155 1156 rx_done: 1157 if ( fc != tc ) { 1158 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1159 u_char reg; 1160 /* 1161 * Set the FIFO threshold to the preset value, 1162 * and enable receive timeout interrupts. 1163 */ 1164 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1165 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1166 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1167 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1168 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1169 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1170 } 1171 1172 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1173 softint_schedule(sc->sc_softintr_cookie); 1174 } else 1175 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1176 1177 #ifdef DDB 1178 /* 1179 * Only =after= we write REOIR is it safe to drop to the debugger. 1180 */ 1181 if ( saw_break ) 1182 Debugger(); 1183 #endif 1184 1185 return 1; 1186 } 1187 1188 /* 1189 * Tx interrupt routine 1190 */ 1191 int 1192 clmpcc_txintr(void *arg) 1193 { 1194 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1195 struct clmpcc_chan *ch; 1196 struct tty *tp; 1197 u_char ftc, oftc; 1198 u_char tir, teoir; 1199 int etcmode = 0; 1200 1201 /* Tx interrupt active? */ 1202 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1203 1204 /* 1205 * If we're using auto-vectored interrupts, we have to 1206 * verify if the chip is generating the interrupt. 1207 */ 1208 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1209 return 0; 1210 1211 /* Get pointer to interrupting channel's data structure */ 1212 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1213 tp = ch->ch_tty; 1214 1215 /* Dummy read of the interrupt status register */ 1216 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1217 1218 /* Make sure embedded transmit commands are disabled */ 1219 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1220 1221 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1222 1223 /* Handle a delayed parameter change */ 1224 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1225 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1226 clmpcc_set_params(ch); 1227 } 1228 1229 if ( ch->ch_obuf_size > 0 ) { 1230 u_int n = min(ch->ch_obuf_size, ftc); 1231 1232 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1233 1234 ftc -= n; 1235 ch->ch_obuf_size -= n; 1236 ch->ch_obuf_addr += n; 1237 1238 } else { 1239 /* 1240 * Check if we should start/stop a break 1241 */ 1242 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1243 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1244 /* Enable embedded transmit commands */ 1245 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1246 ch->ch_cor2 | CLMPCC_COR2_ETC); 1247 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1248 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1249 ftc -= 2; 1250 etcmode = 1; 1251 } 1252 1253 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1254 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1255 /* Enable embedded transmit commands */ 1256 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1257 ch->ch_cor2 | CLMPCC_COR2_ETC); 1258 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1259 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1260 ftc -= 2; 1261 etcmode = 1; 1262 } 1263 } 1264 1265 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1266 1267 if ( ftc != oftc ) { 1268 /* 1269 * Enable/disable the Tx FIFO threshold interrupt 1270 * according to how much data is in the FIFO. 1271 * However, always disable the FIFO threshold if 1272 * we've left the channel in 'Embedded Transmit 1273 * Command' mode. 1274 */ 1275 if ( etcmode || ftc >= ch->ch_cor4 ) 1276 tir &= ~CLMPCC_IER_TX_FIFO; 1277 else 1278 tir |= CLMPCC_IER_TX_FIFO; 1279 teoir = 0; 1280 } else { 1281 /* 1282 * No data was sent. 1283 * Disable transmit interrupt. 1284 */ 1285 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1286 teoir = CLMPCC_TEOIR_NO_TRANS; 1287 1288 /* 1289 * Request Tx processing in the soft interrupt handler 1290 */ 1291 ch->ch_tx_done = 1; 1292 softint_schedule(sc->sc_softintr_cookie); 1293 } 1294 1295 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1296 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1297 1298 return 1; 1299 } 1300 1301 /* 1302 * Modem change interrupt routine 1303 */ 1304 int 1305 clmpcc_mdintr(void *arg) 1306 { 1307 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1308 u_char mir; 1309 1310 /* Modem status interrupt active? */ 1311 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1312 1313 /* 1314 * If we're using auto-vectored interrupts, we have to 1315 * verify if the chip is generating the interrupt. 1316 */ 1317 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1318 return 0; 1319 1320 /* Dummy read of the interrupt status register */ 1321 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1322 1323 /* Retrieve current status of modem lines. */ 1324 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1325 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1326 1327 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1328 softint_schedule(sc->sc_softintr_cookie); 1329 1330 return 1; 1331 } 1332 1333 void 1334 clmpcc_softintr(void *arg) 1335 { 1336 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1337 struct clmpcc_chan *ch; 1338 struct tty *tp; 1339 int (*rint)(int, struct tty *); 1340 u_char *get; 1341 u_char reg; 1342 u_int c; 1343 int chan; 1344 1345 /* Handle Modem state changes too... */ 1346 1347 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1348 ch = &sc->sc_chans[chan]; 1349 tp = ch->ch_tty; 1350 1351 get = ch->ch_ibuf_rd; 1352 rint = tp->t_linesw->l_rint; 1353 1354 /* Squirt buffered incoming data into the tty layer */ 1355 while ( get != ch->ch_ibuf_wr ) { 1356 c = get[0]; 1357 c |= ((u_int)get[1]) << 8; 1358 if ( (rint)(c, tp) == -1 ) { 1359 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1360 break; 1361 } 1362 1363 get += 2; 1364 if ( get == ch->ch_ibuf_end ) 1365 get = ch->ch_ibuf; 1366 1367 ch->ch_ibuf_rd = get; 1368 } 1369 1370 /* 1371 * Is the transmitter idle and in need of attention? 1372 */ 1373 if ( ch->ch_tx_done ) { 1374 ch->ch_tx_done = 0; 1375 1376 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1377 clmpcc_channel_cmd(sc, ch->ch_car, 1378 CLMPCC_CCR_T0_INIT | 1379 CLMPCC_CCR_T0_RX_EN | 1380 CLMPCC_CCR_T0_TX_EN); 1381 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1382 1383 /* 1384 * Allow time for the channel to initialise. 1385 * (Empirically derived duration; there must 1386 * be another way to determine the command 1387 * has completed without busy-waiting...) 1388 */ 1389 delay(800); 1390 1391 /* 1392 * Update the tty layer's idea of the carrier 1393 * bit, in case we changed CLOCAL or MDMBUF. 1394 * We don't hang up here; we only do that by 1395 * explicit request. 1396 */ 1397 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1398 (*tp->t_linesw->l_modem)(tp, reg != 0); 1399 } 1400 1401 CLR(tp->t_state, TS_BUSY); 1402 if ( ISSET(tp->t_state, TS_FLUSH) ) 1403 CLR(tp->t_state, TS_FLUSH); 1404 else 1405 ndflush(&tp->t_outq, 1406 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1407 1408 (*tp->t_linesw->l_start)(tp); 1409 } 1410 } 1411 } 1412 1413 1414 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1415 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1416 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1417 /* 1418 * Following are all routines needed for a cd240x channel to act as console 1419 */ 1420 int 1421 clmpcc_cnattach(struct clmpcc_softc *sc, int chan, int rate) 1422 { 1423 cons_sc = sc; 1424 cons_chan = chan; 1425 cons_rate = rate; 1426 1427 return (clmpcc_init(sc)); 1428 } 1429 1430 /* 1431 * The following functions are polled getc and putc routines, for console use. 1432 */ 1433 static int 1434 clmpcc_common_getc(struct clmpcc_softc *sc, int chan) 1435 { 1436 u_char old_chan; 1437 u_char old_ier; 1438 u_char ch, rir, risr; 1439 int s; 1440 1441 s = splhigh(); 1442 1443 /* Save the currently active channel */ 1444 old_chan = clmpcc_select_channel(sc, chan); 1445 1446 /* 1447 * We have to put the channel into RX interrupt mode before 1448 * trying to read the Rx data register. So save the previous 1449 * interrupt mode. 1450 */ 1451 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1452 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1453 1454 /* Loop until we get a character */ 1455 for (;;) { 1456 /* 1457 * The REN bit will be set in the Receive Interrupt Register 1458 * when the CD240x has a character to process. Remember, 1459 * the RACT bit won't be set until we generate an interrupt 1460 * acknowledge cycle via the MD front-end. 1461 */ 1462 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1463 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1464 continue; 1465 1466 /* Acknowledge the request */ 1467 if ( sc->sc_iackhook ) 1468 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1469 1470 /* 1471 * Determine if the interrupt is for the required channel 1472 * and if valid data is available. 1473 */ 1474 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1475 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1476 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1477 risr != 0 ) { 1478 /* Rx error, or BREAK */ 1479 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1480 CLMPCC_REOIR_NO_TRANS); 1481 } else { 1482 /* Dummy read of the FIFO count register */ 1483 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1484 1485 /* Fetch the received character */ 1486 ch = clmpcc_rd_rxdata(sc); 1487 1488 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1489 break; 1490 } 1491 } 1492 1493 /* Restore the original IER and CAR register contents */ 1494 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1495 clmpcc_select_channel(sc, old_chan); 1496 1497 splx(s); 1498 return ch; 1499 } 1500 1501 1502 static void 1503 clmpcc_common_putc(struct clmpcc_softc *sc, int chan, int c) 1504 { 1505 u_char old_chan; 1506 int s = splhigh(); 1507 1508 /* Save the currently active channel */ 1509 old_chan = clmpcc_select_channel(sc, chan); 1510 1511 /* 1512 * Since we can only access the Tx Data register from within 1513 * the interrupt handler, the easiest way to get console data 1514 * onto the wire is using one of the Special Transmit Character 1515 * registers. 1516 */ 1517 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1518 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1519 CLMPCC_STCR_SND_SPC); 1520 1521 /* Wait until the "Send Special Character" command is accepted */ 1522 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1523 ; 1524 1525 /* Restore the previous channel selected */ 1526 clmpcc_select_channel(sc, old_chan); 1527 1528 splx(s); 1529 } 1530 1531 int 1532 clmpcccngetc(dev_t dev) 1533 { 1534 return clmpcc_common_getc(cons_sc, cons_chan); 1535 } 1536 1537 /* 1538 * Console kernel output character routine. 1539 */ 1540 void 1541 clmpcccnputc(dev_t dev, int c) 1542 { 1543 if ( c == '\n' ) 1544 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1545 1546 clmpcc_common_putc(cons_sc, cons_chan, c); 1547 } 1548