1 /* $NetBSD: clmpcc.c,v 1.18 2001/11/13 13:14:35 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.18 2001/11/13 13:14:35 lukem Exp $"); 45 46 #include "opt_ddb.h" 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/ioctl.h> 52 #include <sys/select.h> 53 #include <sys/tty.h> 54 #include <sys/proc.h> 55 #include <sys/user.h> 56 #include <sys/conf.h> 57 #include <sys/file.h> 58 #include <sys/uio.h> 59 #include <sys/kernel.h> 60 #include <sys/syslog.h> 61 #include <sys/device.h> 62 #include <sys/malloc.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 #include <machine/param.h> 67 68 #include <dev/ic/clmpccreg.h> 69 #include <dev/ic/clmpccvar.h> 70 #include <dev/cons.h> 71 72 73 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 74 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 75 #endif 76 77 78 static int clmpcc_init __P((struct clmpcc_softc *sc)); 79 static void clmpcc_shutdown __P((struct clmpcc_chan *)); 80 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t, 81 int *, int *)); 82 static int clmpcc_param __P((struct tty *, struct termios *)); 83 static void clmpcc_set_params __P((struct clmpcc_chan *)); 84 static void clmpcc_start __P((struct tty *)); 85 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int)); 86 87 88 cdev_decl(clmpcc); 89 90 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 91 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 92 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 93 94 /* 95 * These should be in a header file somewhere... 96 */ 97 #define ISSET(v, f) (((v) & (f)) != 0) 98 #define ISCLR(v, f) (((v) & (f)) == 0) 99 #define SET(v, f) (v) |= (f) 100 #define CLR(v, f) (v) &= ~(f) 101 102 103 extern struct cfdriver clmpcc_cd; 104 105 106 /* 107 * Make this an option variable one can patch. 108 */ 109 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 110 111 112 /* 113 * Things needed when the device is used as a console 114 */ 115 static struct clmpcc_softc *cons_sc = NULL; 116 static int cons_chan; 117 static int cons_rate; 118 119 static int clmpcc_common_getc __P((struct clmpcc_softc *, int)); 120 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int)); 121 int clmpcccngetc __P((dev_t)); 122 void clmpcccnputc __P((dev_t, int)); 123 124 125 /* 126 * Convenience functions, inlined for speed 127 */ 128 #define integrate static inline 129 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int)); 130 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int)); 131 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int)); 132 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int)); 133 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *, 134 u_int)); 135 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int)); 136 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int)); 137 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *)); 138 139 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 140 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 141 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 142 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 143 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 144 145 146 integrate u_int8_t 147 clmpcc_rdreg(sc, offset) 148 struct clmpcc_softc *sc; 149 u_int offset; 150 { 151 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 152 offset ^= sc->sc_byteswap; 153 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 154 offset ^= CLMPCC_BYTESWAP_HIGH; 155 #endif 156 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 157 } 158 159 integrate void 160 clmpcc_wrreg(sc, offset, val) 161 struct clmpcc_softc *sc; 162 u_int offset; 163 u_int val; 164 { 165 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 166 offset ^= sc->sc_byteswap; 167 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 168 offset ^= CLMPCC_BYTESWAP_HIGH; 169 #endif 170 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 171 } 172 173 integrate u_int8_t 174 clmpcc_rdreg_odd(sc, offset) 175 struct clmpcc_softc *sc; 176 u_int offset; 177 { 178 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 179 offset ^= (sc->sc_byteswap & 2); 180 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 181 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 182 #endif 183 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 184 } 185 186 integrate void 187 clmpcc_wrreg_odd(sc, offset, val) 188 struct clmpcc_softc *sc; 189 u_int offset; 190 u_int val; 191 { 192 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 193 offset ^= (sc->sc_byteswap & 2); 194 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 195 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 196 #endif 197 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 198 } 199 200 integrate void 201 clmpcc_wrtx_multi(sc, buff, count) 202 struct clmpcc_softc *sc; 203 u_int8_t *buff; 204 u_int count; 205 { 206 u_int offset = CLMPCC_REG_TDR; 207 208 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 209 offset ^= (sc->sc_byteswap & 2); 210 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 211 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 212 #endif 213 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 214 } 215 216 integrate u_int8_t 217 clmpcc_select_channel(sc, new_chan) 218 struct clmpcc_softc *sc; 219 u_int new_chan; 220 { 221 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 222 223 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 224 225 return old_chan; 226 } 227 228 integrate void 229 clmpcc_channel_cmd(sc, chan, cmd) 230 struct clmpcc_softc *sc; 231 int chan; 232 int cmd; 233 { 234 int i; 235 236 for (i = 5000; i; i--) { 237 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 238 break; 239 delay(1); 240 } 241 242 if ( i == 0 ) 243 printf("%s: channel %d command timeout (idle)\n", 244 sc->sc_dev.dv_xname, chan); 245 246 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 247 } 248 249 integrate void 250 clmpcc_enable_transmitter(ch) 251 struct clmpcc_chan *ch; 252 { 253 u_int old; 254 int s; 255 256 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 257 258 s = splserial(); 259 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 260 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 261 SET(ch->ch_tty->t_state, TS_BUSY); 262 splx(s); 263 264 clmpcc_select_channel(ch->ch_sc, old); 265 } 266 267 static int 268 clmpcc_speed(sc, speed, cor, bpr) 269 struct clmpcc_softc *sc; 270 speed_t speed; 271 int *cor, *bpr; 272 { 273 int c, co, br; 274 275 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 276 br = ((sc->sc_clk / c) / speed) - 1; 277 if ( br < 0x100 ) { 278 *cor = co; 279 *bpr = br; 280 return 0; 281 } 282 } 283 284 return -1; 285 } 286 287 void 288 clmpcc_attach(sc) 289 struct clmpcc_softc *sc; 290 { 291 struct clmpcc_chan *ch; 292 struct tty *tp; 293 int chan; 294 295 if ( cons_sc != NULL && 296 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 297 cons_sc = sc; 298 299 /* Initialise the chip */ 300 clmpcc_init(sc); 301 302 printf(": Cirrus Logic CD240%c Serial Controller\n", 303 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 304 305 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 306 sc->sc_soft_running = 0; 307 #else 308 sc->sc_softintr_cookie = 309 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc); 310 #ifdef DEBUG 311 if (sc->sc_softintr_cookie == NULL) 312 panic("clmpcc_attach: softintr_establish"); 313 #endif 314 #endif 315 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 316 317 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 318 ch = &sc->sc_chans[chan]; 319 320 ch->ch_sc = sc; 321 ch->ch_car = chan; 322 323 tp = ttymalloc(); 324 tp->t_oproc = clmpcc_start; 325 tp->t_param = clmpcc_param; 326 327 ch->ch_tty = tp; 328 329 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 330 if ( ch->ch_ibuf == NULL ) { 331 printf("%s(%d): unable to allocate ring buffer\n", 332 sc->sc_dev.dv_xname, chan); 333 return; 334 } 335 336 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 337 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 338 339 tty_attach(tp); 340 } 341 342 printf("%s: %d channels available", sc->sc_dev.dv_xname, 343 CLMPCC_NUM_CHANS); 344 if ( cons_sc == sc ) { 345 printf(", console on channel %d.\n", cons_chan); 346 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 347 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 348 } else 349 printf(".\n"); 350 } 351 352 static int 353 clmpcc_init(sc) 354 struct clmpcc_softc *sc; 355 { 356 u_int tcor, tbpr; 357 u_int rcor, rbpr; 358 u_int msvr_rts, msvr_dtr; 359 u_int ccr; 360 int is_console; 361 int i; 362 363 /* 364 * All we're really concerned about here is putting the chip 365 * into a quiescent state so that it won't do anything until 366 * clmpccopen() is called. (Except the console channel.) 367 */ 368 369 /* 370 * If the chip is acting as console, set all channels to the supplied 371 * console baud rate. Otherwise, plump for 9600. 372 */ 373 if ( cons_sc && 374 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 375 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 376 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 377 is_console = 1; 378 } else { 379 clmpcc_speed(sc, 9600, &tcor, &tbpr); 380 clmpcc_speed(sc, 9600, &rcor, &rbpr); 381 is_console = 0; 382 } 383 384 /* Allow any pending output to be sent */ 385 delay(10000); 386 387 /* Send the Reset All command to channel 0 (resets all channels!) */ 388 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 389 390 delay(1000); 391 392 /* 393 * The chip will set it's firmware revision register to a non-zero 394 * value to indicate completion of reset. 395 */ 396 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 397 delay(1); 398 399 if ( i == 0 ) { 400 /* 401 * Watch out... If this chip is console, the message 402 * probably won't be sent since we just reset it! 403 */ 404 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 405 return -1; 406 } 407 408 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 409 clmpcc_select_channel(sc, i); 410 411 /* All interrupts are disabled to begin with */ 412 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 413 414 /* Make sure the channel interrupts on the correct vectors */ 415 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 416 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 417 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 418 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 419 420 /* Receive timer prescaler set to 1ms */ 421 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 422 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 423 424 /* We support Async mode only */ 425 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 426 427 /* Set the required baud rate */ 428 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 429 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 430 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 431 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 432 433 /* Always default to 8N1 (XXX what about console?) */ 434 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 435 CLMPCC_COR1_NO_PARITY | 436 CLMPCC_COR1_IGNORE_PAR); 437 438 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 439 440 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 441 442 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 443 CLMPCC_COR4_CDzd | 444 CLMPCC_COR4_CTSzd); 445 446 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 447 CLMPCC_COR5_CDod | 448 CLMPCC_COR5_CTSod | 449 CLMPCC_COR5_FLOW_NORM); 450 451 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 452 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 453 454 /* Set the receive FIFO timeout */ 455 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 456 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 457 458 /* At this point, we set up the console differently */ 459 if ( is_console && i == cons_chan ) { 460 msvr_rts = CLMPCC_MSVR_RTS; 461 msvr_dtr = CLMPCC_MSVR_DTR; 462 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 463 } else { 464 msvr_rts = 0; 465 msvr_dtr = 0; 466 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 467 } 468 469 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 470 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 471 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 472 delay(100); 473 } 474 475 return 0; 476 } 477 478 static void 479 clmpcc_shutdown(ch) 480 struct clmpcc_chan *ch; 481 { 482 int oldch; 483 484 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 485 486 /* Turn off interrupts. */ 487 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 488 489 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 490 /* Disable the transmitter and receiver */ 491 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 492 CLMPCC_CCR_T0_TX_DIS); 493 494 /* Drop RTS and DTR */ 495 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 496 } 497 498 clmpcc_select_channel(ch->ch_sc, oldch); 499 } 500 501 int 502 clmpccopen(dev, flag, mode, p) 503 dev_t dev; 504 int flag, mode; 505 struct proc *p; 506 { 507 struct clmpcc_softc *sc; 508 struct clmpcc_chan *ch; 509 struct tty *tp; 510 int oldch; 511 int error; 512 513 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 514 if (sc == NULL) 515 return (ENXIO); 516 517 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 518 519 tp = ch->ch_tty; 520 521 if ( ISSET(tp->t_state, TS_ISOPEN) && 522 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 523 return EBUSY; 524 525 /* 526 * Do the following iff this is a first open. 527 */ 528 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 529 530 ttychars(tp); 531 532 tp->t_dev = dev; 533 tp->t_iflag = TTYDEF_IFLAG; 534 tp->t_oflag = TTYDEF_OFLAG; 535 tp->t_lflag = TTYDEF_LFLAG; 536 tp->t_cflag = TTYDEF_CFLAG; 537 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 538 539 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 540 SET(tp->t_cflag, CLOCAL); 541 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 542 SET(tp->t_cflag, CRTSCTS); 543 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 544 SET(tp->t_cflag, MDMBUF); 545 546 /* 547 * Override some settings if the channel is being 548 * used as the console. 549 */ 550 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 551 tp->t_ospeed = tp->t_ispeed = cons_rate; 552 SET(tp->t_cflag, CLOCAL); 553 CLR(tp->t_cflag, CRTSCTS); 554 CLR(tp->t_cflag, HUPCL); 555 } 556 557 ch->ch_control = 0; 558 559 clmpcc_param(tp, &tp->t_termios); 560 ttsetwater(tp); 561 562 /* Clear the input ring */ 563 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 564 565 /* Select the channel */ 566 oldch = clmpcc_select_channel(sc, ch->ch_car); 567 568 /* Reset it */ 569 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 570 CLMPCC_CCR_T0_RX_EN | 571 CLMPCC_CCR_T0_TX_EN); 572 573 /* Enable receiver and modem change interrupts. */ 574 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 575 CLMPCC_IER_RET | 576 CLMPCC_IER_RX_FIFO); 577 578 /* Raise RTS and DTR */ 579 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 580 581 clmpcc_select_channel(sc, oldch); 582 } else 583 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 584 return EBUSY; 585 586 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 587 if (error) 588 goto bad; 589 590 error = (*tp->t_linesw->l_open)(dev, tp); 591 if (error) 592 goto bad; 593 594 return 0; 595 596 bad: 597 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 598 /* 599 * We failed to open the device, and nobody else had it opened. 600 * Clean up the state as appropriate. 601 */ 602 clmpcc_shutdown(ch); 603 } 604 605 return error; 606 } 607 608 int 609 clmpccclose(dev, flag, mode, p) 610 dev_t dev; 611 int flag, mode; 612 struct proc *p; 613 { 614 struct clmpcc_softc *sc = 615 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 616 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 617 struct tty *tp = ch->ch_tty; 618 int s; 619 620 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 621 return 0; 622 623 (*tp->t_linesw->l_close)(tp, flag); 624 625 s = spltty(); 626 627 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 628 /* 629 * Although we got a last close, the device may still be in 630 * use; e.g. if this was the dialout node, and there are still 631 * processes waiting for carrier on the non-dialout node. 632 */ 633 clmpcc_shutdown(ch); 634 } 635 636 ttyclose(tp); 637 638 splx(s); 639 640 return 0; 641 } 642 643 int 644 clmpccread(dev, uio, flag) 645 dev_t dev; 646 struct uio *uio; 647 int flag; 648 { 649 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 650 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 651 652 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 653 } 654 655 int 656 clmpccwrite(dev, uio, flag) 657 dev_t dev; 658 struct uio *uio; 659 int flag; 660 { 661 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 662 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 663 664 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 665 } 666 667 int 668 clmpccpoll(dev, events, p) 669 dev_t dev; 670 int events; 671 struct proc *p; 672 { 673 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 674 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 675 676 return ((*tp->t_linesw->l_poll)(tp, events, p)); 677 } 678 679 struct tty * 680 clmpcctty(dev) 681 dev_t dev; 682 { 683 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 684 685 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 686 } 687 688 int 689 clmpccioctl(dev, cmd, data, flag, p) 690 dev_t dev; 691 u_long cmd; 692 caddr_t data; 693 int flag; 694 struct proc *p; 695 { 696 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 697 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 698 struct tty *tp = ch->ch_tty; 699 int error; 700 701 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 702 if (error >= 0) 703 return error; 704 705 error = ttioctl(tp, cmd, data, flag, p); 706 if (error >= 0) 707 return error; 708 709 error = 0; 710 711 switch (cmd) { 712 case TIOCSBRK: 713 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 714 clmpcc_enable_transmitter(ch); 715 break; 716 717 case TIOCCBRK: 718 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 719 clmpcc_enable_transmitter(ch); 720 break; 721 722 case TIOCSDTR: 723 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 724 break; 725 726 case TIOCCDTR: 727 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 728 break; 729 730 case TIOCMSET: 731 clmpcc_modem_control(ch, *((int *)data), DMSET); 732 break; 733 734 case TIOCMBIS: 735 clmpcc_modem_control(ch, *((int *)data), DMBIS); 736 break; 737 738 case TIOCMBIC: 739 clmpcc_modem_control(ch, *((int *)data), DMBIC); 740 break; 741 742 case TIOCMGET: 743 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 744 break; 745 746 case TIOCGFLAGS: 747 *((int *)data) = ch->ch_openflags; 748 break; 749 750 case TIOCSFLAGS: 751 error = suser(p->p_ucred, &p->p_acflag); 752 if ( error ) 753 break; 754 ch->ch_openflags = *((int *)data) & 755 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 756 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 757 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 758 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 759 break; 760 761 default: 762 error = ENOTTY; 763 break; 764 } 765 766 return error; 767 } 768 769 int 770 clmpcc_modem_control(ch, bits, howto) 771 struct clmpcc_chan *ch; 772 int bits; 773 int howto; 774 { 775 struct clmpcc_softc *sc = ch->ch_sc; 776 struct tty *tp = ch->ch_tty; 777 int oldch; 778 int msvr; 779 int rbits = 0; 780 781 oldch = clmpcc_select_channel(sc, ch->ch_car); 782 783 switch ( howto ) { 784 case DMGET: 785 msvr = clmpcc_rd_msvr(sc); 786 787 if ( sc->sc_swaprtsdtr ) { 788 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 789 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 790 } else { 791 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 792 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 793 } 794 795 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 796 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 797 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 798 break; 799 800 case DMSET: 801 if ( sc->sc_swaprtsdtr ) { 802 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 803 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 804 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 805 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 806 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 807 } else { 808 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 809 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 810 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 811 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 812 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 813 } 814 break; 815 816 case DMBIS: 817 if ( sc->sc_swaprtsdtr ) { 818 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 819 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 820 if ( ISSET(bits, TIOCM_DTR) ) 821 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 822 } else { 823 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 824 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 825 if ( ISSET(bits, TIOCM_DTR) ) 826 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 827 } 828 break; 829 830 case DMBIC: 831 if ( sc->sc_swaprtsdtr ) { 832 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 833 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 834 if ( ISCLR(bits, TIOCM_DTR) ) 835 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 836 } else { 837 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 838 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 839 if ( ISCLR(bits, TIOCM_DTR) ) 840 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 841 } 842 break; 843 } 844 845 clmpcc_select_channel(sc, oldch); 846 847 return rbits; 848 } 849 850 static int 851 clmpcc_param(tp, t) 852 struct tty *tp; 853 struct termios *t; 854 { 855 struct clmpcc_softc *sc = 856 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 857 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 858 u_char cor; 859 u_char oldch; 860 int oclk, obpr; 861 int iclk, ibpr; 862 int s; 863 864 /* Check requested parameters. */ 865 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 866 return EINVAL; 867 868 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 869 return EINVAL; 870 871 /* 872 * For the console, always force CLOCAL and !HUPCL, so that the port 873 * is always active. 874 */ 875 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 876 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 877 SET(t->c_cflag, CLOCAL); 878 CLR(t->c_cflag, HUPCL); 879 } 880 881 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 882 883 /* If ospeed it zero, hangup the line */ 884 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 885 886 if ( t->c_ospeed ) { 887 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 888 ch->ch_tbpr = obpr; 889 } else { 890 ch->ch_tcor = 0; 891 ch->ch_tbpr = 0; 892 } 893 894 if ( t->c_ispeed ) { 895 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 896 ch->ch_rbpr = ibpr; 897 } else { 898 ch->ch_rcor = 0; 899 ch->ch_rbpr = 0; 900 } 901 902 /* Work out value to use for COR1 */ 903 cor = 0; 904 if ( ISSET(t->c_cflag, PARENB) ) { 905 cor |= CLMPCC_COR1_NORM_PARITY; 906 if ( ISSET(t->c_cflag, PARODD) ) 907 cor |= CLMPCC_COR1_ODD_PARITY; 908 } 909 910 if ( ISCLR(t->c_cflag, INPCK) ) 911 cor |= CLMPCC_COR1_IGNORE_PAR; 912 913 switch ( t->c_cflag & CSIZE ) { 914 case CS5: 915 cor |= CLMPCC_COR1_CHAR_5BITS; 916 break; 917 918 case CS6: 919 cor |= CLMPCC_COR1_CHAR_6BITS; 920 break; 921 922 case CS7: 923 cor |= CLMPCC_COR1_CHAR_7BITS; 924 break; 925 926 case CS8: 927 cor |= CLMPCC_COR1_CHAR_8BITS; 928 break; 929 } 930 931 ch->ch_cor1 = cor; 932 933 /* 934 * The only interesting bit in COR2 is 'CTS Automatic Enable' 935 * when hardware flow control is in effect. 936 */ 937 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 938 939 /* COR3 needs to be set to the number of stop bits... */ 940 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 941 CLMPCC_COR3_STOP_1; 942 943 /* 944 * COR4 contains the FIFO threshold setting. 945 * We adjust the threshold depending on the input speed... 946 */ 947 if ( t->c_ispeed <= 1200 ) 948 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 949 else if ( t->c_ispeed <= 19200 ) 950 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 951 else 952 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 953 954 /* 955 * If chip is used with CTS and DTR swapped, we can enable 956 * automatic hardware flow control. 957 */ 958 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 959 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 960 else 961 ch->ch_cor5 = 0; 962 963 s = splserial(); 964 oldch = clmpcc_select_channel(sc, ch->ch_car); 965 966 /* 967 * COR2 needs to be set immediately otherwise we might never get 968 * a Tx EMPTY interrupt to change the other parameters. 969 */ 970 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 971 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 972 973 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 974 clmpcc_set_params(ch); 975 else 976 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 977 978 clmpcc_select_channel(sc, oldch); 979 980 splx(s); 981 982 return 0; 983 } 984 985 static void 986 clmpcc_set_params(ch) 987 struct clmpcc_chan *ch; 988 { 989 struct clmpcc_softc *sc = ch->ch_sc; 990 u_char r1; 991 u_char r2; 992 993 if ( ch->ch_tcor || ch->ch_tbpr ) { 994 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 995 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 996 /* Only write Tx rate if it really has changed */ 997 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 998 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 999 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 1000 } 1001 } 1002 1003 if ( ch->ch_rcor || ch->ch_rbpr ) { 1004 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 1005 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 1006 /* Only write Rx rate if it really has changed */ 1007 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 1008 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 1009 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1010 } 1011 } 1012 1013 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1014 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1015 /* Any change to COR1 requires an INIT command */ 1016 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1017 } 1018 1019 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1020 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1021 1022 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1023 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1024 /* 1025 * Note: If the FIFO has changed, we always set it to 1026 * zero here and disable the Receive Timeout interrupt. 1027 * It's up to the Rx Interrupt handler to pick the 1028 * appropriate moment to write the new FIFO length. 1029 */ 1030 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1031 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1032 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1033 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1034 } 1035 1036 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1037 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1038 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1039 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1040 } 1041 } 1042 1043 static void 1044 clmpcc_start(tp) 1045 struct tty *tp; 1046 { 1047 struct clmpcc_softc *sc = 1048 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1049 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1050 u_int oldch; 1051 int s; 1052 1053 s = spltty(); 1054 1055 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1056 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1057 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1058 CLR(tp->t_state, TS_ASLEEP); 1059 wakeup(&tp->t_outq); 1060 } 1061 selwakeup(&tp->t_wsel); 1062 } 1063 1064 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1065 CLMPCC_FLG_END_BREAK) || 1066 tp->t_outq.c_cc > 0 ) { 1067 1068 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1069 CLMPCC_FLG_END_BREAK) ) { 1070 ch->ch_obuf_addr = tp->t_outq.c_cf; 1071 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1072 } 1073 1074 /* Enable TX empty interrupts */ 1075 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1076 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1077 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1078 CLMPCC_IER_TX_EMPTY); 1079 clmpcc_select_channel(ch->ch_sc, oldch); 1080 SET(tp->t_state, TS_BUSY); 1081 } 1082 } 1083 1084 splx(s); 1085 } 1086 1087 /* 1088 * Stop output on a line. 1089 */ 1090 void 1091 clmpccstop(tp, flag) 1092 struct tty *tp; 1093 int flag; 1094 { 1095 struct clmpcc_softc *sc = 1096 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1097 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1098 int s; 1099 1100 s = splserial(); 1101 1102 if ( ISSET(tp->t_state, TS_BUSY) ) { 1103 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1104 SET(tp->t_state, TS_FLUSH); 1105 ch->ch_obuf_size = 0; 1106 } 1107 splx(s); 1108 } 1109 1110 /* 1111 * RX interrupt routine 1112 */ 1113 int 1114 clmpcc_rxintr(arg) 1115 void *arg; 1116 { 1117 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1118 struct clmpcc_chan *ch; 1119 u_int8_t *put, *end, rxd; 1120 u_char errstat; 1121 u_char fc, tc; 1122 u_char risr; 1123 u_char rir; 1124 #ifdef DDB 1125 int saw_break = 0; 1126 #endif 1127 1128 /* Receive interrupt active? */ 1129 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1130 1131 /* 1132 * If we're using auto-vectored interrupts, we have to 1133 * verify if the chip is generating the interrupt. 1134 */ 1135 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1136 return 0; 1137 1138 /* Get pointer to interrupting channel's data structure */ 1139 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1140 1141 /* Get the interrupt status register */ 1142 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1143 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1144 u_char reg; 1145 /* 1146 * Set the FIFO threshold to zero, and disable 1147 * further receive timeout interrupts. 1148 */ 1149 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1150 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1151 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1152 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1153 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1154 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1155 return 1; 1156 } 1157 1158 /* How many bytes are waiting in the FIFO? */ 1159 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1160 1161 #ifdef DDB 1162 /* 1163 * Allow BREAK on the console to drop to the debugger. 1164 */ 1165 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1166 risr & CLMPCC_RISR_BREAK ) { 1167 saw_break = 1; 1168 } 1169 #endif 1170 1171 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1172 /* Just get rid of the data */ 1173 while ( fc-- ) 1174 (void) clmpcc_rd_rxdata(sc); 1175 goto rx_done; 1176 } 1177 1178 put = ch->ch_ibuf_wr; 1179 end = ch->ch_ibuf_end; 1180 1181 /* 1182 * Note: The chip is completely hosed WRT these error 1183 * conditions; there seems to be no way to associate 1184 * the error with the correct character in the FIFO. 1185 * We compromise by tagging the first character we read 1186 * with the error. Not perfect, but there's no other way. 1187 */ 1188 errstat = 0; 1189 if ( risr & CLMPCC_RISR_PARITY ) 1190 errstat |= TTY_PE; 1191 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1192 errstat |= TTY_FE; 1193 1194 /* 1195 * As long as there are characters in the FIFO, and we 1196 * have space for them... 1197 */ 1198 while ( fc > 0 ) { 1199 1200 *put++ = rxd = clmpcc_rd_rxdata(sc); 1201 *put++ = errstat; 1202 1203 if ( put >= end ) 1204 put = ch->ch_ibuf; 1205 1206 if ( put == ch->ch_ibuf_rd ) { 1207 put -= 2; 1208 if ( put < ch->ch_ibuf ) 1209 put = end - 2; 1210 } 1211 1212 errstat = 0; 1213 fc--; 1214 } 1215 1216 ch->ch_ibuf_wr = put; 1217 1218 #if 0 1219 if ( sc->sc_swaprtsdtr == 0 && 1220 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1221 /* 1222 * If RTS/DTR are not physically swapped, we have to 1223 * do hardware flow control manually 1224 */ 1225 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1226 } 1227 #endif 1228 1229 rx_done: 1230 if ( fc != tc ) { 1231 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1232 u_char reg; 1233 /* 1234 * Set the FIFO threshold to the preset value, 1235 * and enable receive timeout interrupts. 1236 */ 1237 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1238 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1239 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1240 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1241 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1242 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1243 } 1244 1245 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1246 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1247 if ( sc->sc_soft_running == 0 ) { 1248 sc->sc_soft_running = 1; 1249 (sc->sc_softhook)(sc); 1250 } 1251 #else 1252 softintr_schedule(sc->sc_softintr_cookie); 1253 #endif 1254 } else 1255 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1256 1257 #ifdef DDB 1258 /* 1259 * Only =after= we write REOIR is it safe to drop to the debugger. 1260 */ 1261 if ( saw_break ) 1262 Debugger(); 1263 #endif 1264 1265 return 1; 1266 } 1267 1268 /* 1269 * Tx interrupt routine 1270 */ 1271 int 1272 clmpcc_txintr(arg) 1273 void *arg; 1274 { 1275 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1276 struct clmpcc_chan *ch; 1277 struct tty *tp; 1278 u_char ftc, oftc; 1279 u_char tir, teoir; 1280 int etcmode = 0; 1281 1282 /* Tx interrupt active? */ 1283 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1284 1285 /* 1286 * If we're using auto-vectored interrupts, we have to 1287 * verify if the chip is generating the interrupt. 1288 */ 1289 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1290 return 0; 1291 1292 /* Get pointer to interrupting channel's data structure */ 1293 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1294 tp = ch->ch_tty; 1295 1296 /* Dummy read of the interrupt status register */ 1297 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1298 1299 /* Make sure embedded transmit commands are disabled */ 1300 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1301 1302 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1303 1304 /* Handle a delayed parameter change */ 1305 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1306 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1307 clmpcc_set_params(ch); 1308 } 1309 1310 if ( ch->ch_obuf_size > 0 ) { 1311 u_int n = min(ch->ch_obuf_size, ftc); 1312 1313 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1314 1315 ftc -= n; 1316 ch->ch_obuf_size -= n; 1317 ch->ch_obuf_addr += n; 1318 1319 } else { 1320 /* 1321 * Check if we should start/stop a break 1322 */ 1323 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1324 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1325 /* Enable embedded transmit commands */ 1326 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1327 ch->ch_cor2 | CLMPCC_COR2_ETC); 1328 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1329 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1330 ftc -= 2; 1331 etcmode = 1; 1332 } 1333 1334 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1335 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1336 /* Enable embedded transmit commands */ 1337 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1338 ch->ch_cor2 | CLMPCC_COR2_ETC); 1339 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1340 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1341 ftc -= 2; 1342 etcmode = 1; 1343 } 1344 } 1345 1346 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1347 1348 if ( ftc != oftc ) { 1349 /* 1350 * Enable/disable the Tx FIFO threshold interrupt 1351 * according to how much data is in the FIFO. 1352 * However, always disable the FIFO threshold if 1353 * we've left the channel in 'Embedded Transmit 1354 * Command' mode. 1355 */ 1356 if ( etcmode || ftc >= ch->ch_cor4 ) 1357 tir &= ~CLMPCC_IER_TX_FIFO; 1358 else 1359 tir |= CLMPCC_IER_TX_FIFO; 1360 teoir = 0; 1361 } else { 1362 /* 1363 * No data was sent. 1364 * Disable transmit interrupt. 1365 */ 1366 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1367 teoir = CLMPCC_TEOIR_NO_TRANS; 1368 1369 /* 1370 * Request Tx processing in the soft interrupt handler 1371 */ 1372 ch->ch_tx_done = 1; 1373 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1374 if ( sc->sc_soft_running == 0 ) { 1375 sc->sc_soft_running = 1; 1376 (sc->sc_softhook)(sc); 1377 } 1378 #else 1379 softintr_schedule(sc->sc_softintr_cookie); 1380 #endif 1381 } 1382 1383 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1384 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1385 1386 return 1; 1387 } 1388 1389 /* 1390 * Modem change interrupt routine 1391 */ 1392 int 1393 clmpcc_mdintr(arg) 1394 void *arg; 1395 { 1396 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1397 u_char mir; 1398 1399 /* Modem status interrupt active? */ 1400 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1401 1402 /* 1403 * If we're using auto-vectored interrupts, we have to 1404 * verify if the chip is generating the interrupt. 1405 */ 1406 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1407 return 0; 1408 1409 /* Dummy read of the interrupt status register */ 1410 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1411 1412 /* Retrieve current status of modem lines. */ 1413 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1414 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1415 1416 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1417 1418 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1419 if ( sc->sc_soft_running == 0 ) { 1420 sc->sc_soft_running = 1; 1421 (sc->sc_softhook)(sc); 1422 } 1423 #else 1424 softintr_schedule(sc->sc_softintr_cookie); 1425 #endif 1426 1427 return 1; 1428 } 1429 1430 void 1431 clmpcc_softintr(arg) 1432 void *arg; 1433 { 1434 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1435 struct clmpcc_chan *ch; 1436 struct tty *tp; 1437 int (*rint) __P((int, struct tty *)); 1438 u_char *get; 1439 u_char reg; 1440 u_int c; 1441 int chan; 1442 1443 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1444 sc->sc_soft_running = 0; 1445 #endif 1446 1447 /* Handle Modem state changes too... */ 1448 1449 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1450 ch = &sc->sc_chans[chan]; 1451 tp = ch->ch_tty; 1452 1453 get = ch->ch_ibuf_rd; 1454 rint = tp->t_linesw->l_rint; 1455 1456 /* Squirt buffered incoming data into the tty layer */ 1457 while ( get != ch->ch_ibuf_wr ) { 1458 c = get[0]; 1459 c |= ((u_int)get[1]) << 8; 1460 if ( (rint)(c, tp) == -1 ) { 1461 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1462 break; 1463 } 1464 1465 get += 2; 1466 if ( get == ch->ch_ibuf_end ) 1467 get = ch->ch_ibuf; 1468 1469 ch->ch_ibuf_rd = get; 1470 } 1471 1472 /* 1473 * Is the transmitter idle and in need of attention? 1474 */ 1475 if ( ch->ch_tx_done ) { 1476 ch->ch_tx_done = 0; 1477 1478 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1479 clmpcc_channel_cmd(sc, ch->ch_car, 1480 CLMPCC_CCR_T0_INIT | 1481 CLMPCC_CCR_T0_RX_EN | 1482 CLMPCC_CCR_T0_TX_EN); 1483 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1484 1485 /* 1486 * Allow time for the channel to initialise. 1487 * (Empirically derived duration; there must 1488 * be another way to determine the command 1489 * has completed without busy-waiting...) 1490 */ 1491 delay(800); 1492 1493 /* 1494 * Update the tty layer's idea of the carrier 1495 * bit, in case we changed CLOCAL or MDMBUF. 1496 * We don't hang up here; we only do that by 1497 * explicit request. 1498 */ 1499 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1500 (*tp->t_linesw->l_modem)(tp, reg != 0); 1501 } 1502 1503 CLR(tp->t_state, TS_BUSY); 1504 if ( ISSET(tp->t_state, TS_FLUSH) ) 1505 CLR(tp->t_state, TS_FLUSH); 1506 else 1507 ndflush(&tp->t_outq, 1508 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1509 1510 (*tp->t_linesw->l_start)(tp); 1511 } 1512 } 1513 } 1514 1515 1516 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1517 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1518 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1519 /* 1520 * Following are all routines needed for a cd240x channel to act as console 1521 */ 1522 int 1523 clmpcc_cnattach(sc, chan, rate) 1524 struct clmpcc_softc *sc; 1525 int chan; 1526 int rate; 1527 { 1528 cons_sc = sc; 1529 cons_chan = chan; 1530 cons_rate = rate; 1531 1532 return (clmpcc_init(sc)); 1533 } 1534 1535 /* 1536 * The following functions are polled getc and putc routines, for console use. 1537 */ 1538 static int 1539 clmpcc_common_getc(sc, chan) 1540 struct clmpcc_softc *sc; 1541 int chan; 1542 { 1543 u_char old_chan; 1544 u_char old_ier; 1545 u_char ch, rir, risr; 1546 int s; 1547 1548 s = splhigh(); 1549 1550 /* Save the currently active channel */ 1551 old_chan = clmpcc_select_channel(sc, chan); 1552 1553 /* 1554 * We have to put the channel into RX interrupt mode before 1555 * trying to read the Rx data register. So save the previous 1556 * interrupt mode. 1557 */ 1558 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1559 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1560 1561 /* Loop until we get a character */ 1562 for (;;) { 1563 /* 1564 * The REN bit will be set in the Receive Interrupt Register 1565 * when the CD240x has a character to process. Remember, 1566 * the RACT bit won't be set until we generate an interrupt 1567 * acknowledge cycle via the MD front-end. 1568 */ 1569 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1570 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1571 continue; 1572 1573 /* Acknowledge the request */ 1574 if ( sc->sc_iackhook ) 1575 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1576 1577 /* 1578 * Determine if the interrupt is for the required channel 1579 * and if valid data is available. 1580 */ 1581 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1582 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1583 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1584 risr != 0 ) { 1585 /* Rx error, or BREAK */ 1586 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1587 CLMPCC_REOIR_NO_TRANS); 1588 } else { 1589 /* Dummy read of the FIFO count register */ 1590 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1591 1592 /* Fetch the received character */ 1593 ch = clmpcc_rd_rxdata(sc); 1594 1595 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1596 break; 1597 } 1598 } 1599 1600 /* Restore the original IER and CAR register contents */ 1601 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1602 clmpcc_select_channel(sc, old_chan); 1603 1604 splx(s); 1605 return ch; 1606 } 1607 1608 1609 static void 1610 clmpcc_common_putc(sc, chan, c) 1611 struct clmpcc_softc *sc; 1612 int chan; 1613 int c; 1614 { 1615 u_char old_chan; 1616 int s = splhigh(); 1617 1618 /* Save the currently active channel */ 1619 old_chan = clmpcc_select_channel(sc, chan); 1620 1621 /* 1622 * Since we can only access the Tx Data register from within 1623 * the interrupt handler, the easiest way to get console data 1624 * onto the wire is using one of the Special Transmit Character 1625 * registers. 1626 */ 1627 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1628 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1629 CLMPCC_STCR_SND_SPC); 1630 1631 /* Wait until the "Send Special Character" command is accepted */ 1632 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1633 ; 1634 1635 /* Restore the previous channel selected */ 1636 clmpcc_select_channel(sc, old_chan); 1637 1638 splx(s); 1639 } 1640 1641 int 1642 clmpcccngetc(dev) 1643 dev_t dev; 1644 { 1645 return clmpcc_common_getc(cons_sc, cons_chan); 1646 } 1647 1648 /* 1649 * Console kernel output character routine. 1650 */ 1651 void 1652 clmpcccnputc(dev, c) 1653 dev_t dev; 1654 int c; 1655 { 1656 if ( c == '\n' ) 1657 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1658 1659 clmpcc_common_putc(cons_sc, cons_chan, c); 1660 } 1661