1 /* $NetBSD: tsl256xreg.h,v 1.2 2021/01/04 21:59:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jason R. Thorpe 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef tsl256xreg_h_included 30 #define tsl256xreg_h_included 31 32 /* 33 * Hardware definitions for the TAOS TSL2560 (SMBus) and TSL2561 (I2C). 34 * 35 * These devices combine a broadband photodiode (visible light + infrared) 36 * and an additional ifrared phtodiode onto a single CMOS integrated circuit. 37 * The devices include programmable thresholds that can trigger SMB-Alert 38 * type interrupts (TSL2560) or a traditional level-triggered interrupt 39 * (TSL2561) that remains asserted until cleared. 40 */ 41 42 /* 43 * Valid I2C addresses for the TSL2561. The address is selected based 44 * on how the ADDR_SEL pin is connected. 45 */ 46 #define TSL256x_SLAVEADDR_GND 0x29 /* ADDR SEL tied to ground */ 47 #define TSL256x_SLAVEADDR_FLOAT 0x39 /* ADDR SEL left floating */ 48 #define TSL256x_SLAVEADDR_VDD 0x49 /* ADDR SEL tied to Vdd */ 49 #define TSL256x_SMB_ALERT_ADDR 0x0c /* SMB Alert address (all configs) */ 50 51 /* 52 * TSL256x register definitions. 53 */ 54 55 /* COMMAND - Specifies register address and other parameters */ 56 #define COMMAND6x_REGMASK 0x0f /* register address mask */ 57 #define COMMAND6x_BLOCK 0x10 /* transaction uses block read/write */ 58 #define COMMAND6x_WORD 0x20 /* transaction uses word read/write */ 59 #define COMMAND6x_CLEAR 0x40 /* clear pending interrupt */ 60 #define COMMAND6x_CMD 0x80 /* Select command register; MBO */ 61 62 63 /* CONTROL - Control of basic functions */ 64 #define TSL256x_REG_CONTROL 0x0 65 #define CONTROL6x_POWER_OFF 0x00 66 #define CONTROL6x_POWER_ON 0x03 67 68 69 /* TIMING - Integration time / gain control */ 70 #define TSL256x_REG_TIMING 0x1 71 #define TIMING6x_INTEG_13_7ms 0x00 /* 13.7ms integration time */ 72 #define TIMING6x_INTEG_101ms 0x01 /* 101ms integration time */ 73 #define TIMING6x_INTEG_402ms 0x02 /* 402ms integration time */ 74 #define TIMING6x_INTEG_MANUAL 0x03 /* use manual timing */ 75 #define TIMING6x_MANUAL 0x08 /* manual timing; 1 starts, 0 stops */ 76 #define TIMING6x_GAIN_1X 0x00 77 #define TIMING6x_GAIN_16X 0x10 78 79 80 /* THRESHLOWLOW - Low byte of low interrupt threshold */ 81 #define TSL256x_REG_LOWLOW 0x2 82 83 84 /* THRESHLOWHIGH - High byte of low interrupt threshold */ 85 #define TSL256x_REG_LOWHIGH 0x3 86 87 88 /* THRESHHIGHLOW - Low byte of high interrupt threshold */ 89 #define TSL256x_REG_HIGHLOW 0x4 90 91 92 /* THRESHHIGHHIGH - High byte of high interrupt threshold */ 93 #define TSL256x_REG_HIGHHIGH 0x5 94 95 96 /* INTERRUPT - Interrupt control */ 97 #define TSL256x_REG_INTERRUPT 0x6 98 #define INTERRUPT6x_LEVEL 0x01 /* Level-triggered interrupt */ 99 #define INTERRUPT6x_SMB_ALERT 0x02 /* SMB Alert compliant interrupt */ 100 #define INTERRUPT6x_TEST 0x03 /* interrupt test */ 101 #define INTERRUPT6x_PERSIST(x) ((x) << 4) 102 /* 103 * Interrupt persist settings: 104 * 0 - Every ADC cycle generates an interrupt 105 * 1..15 - # integration periods outside threshold range 106 */ 107 108 109 /* 0x7 - Reserved */ 110 111 112 /* CRC - Factory test -- not a user register */ 113 #define TSL256x_REG_CRC 0x8 114 115 116 /* 0x9 - Reserved */ 117 118 119 /* ID - Part number / Rev ID */ 120 #define TSL256x_REG_ID 0xa 121 #define ID6x_GET_PARTNO(x) (((x) & 0xf0) >> 4) 122 #define ID6x_PARTNO_TSL2560 0x0 123 #define ID6x_PARTNO_TSL2561 0x1 124 #define ID6x_GET_REVNO(x) ((x) & 0x0f) 125 126 127 /* 0xb - Reserved */ 128 129 130 /* DATA0LOW - Low byte of ADC channel 0 */ 131 #define TSL256x_REG_DATA0LOW 0xc 132 133 134 /* DATA0HIGH - High byte of ADC channel 0 */ 135 #define TSL256x_REG_DATA0HIGH 0xd 136 137 138 /* DATA1LOW - Low byte of ADC channel 1 */ 139 #define TSL256x_REG_DATA1LOW 0xe 140 141 142 /* DATA1HIGH - High byte of ADC channel 1 */ 143 #define TSL256x_REG_DATA1HIGH 0xf 144 145 #endif /* tsl256xreg_h_included */ 146