1 /* $NetBSD: m41st84.c,v 1.32 2021/05/21 21:21:01 macallan Exp $ */
2
3 /*
4 * Copyright (c) 2003 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.32 2021/05/21 21:21:01 macallan Exp $");
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/device.h>
44 #include <sys/kernel.h>
45 #include <sys/fcntl.h>
46 #include <sys/uio.h>
47 #include <sys/conf.h>
48 #include <sys/event.h>
49
50 #include <dev/clock_subr.h>
51
52 #include <dev/i2c/i2cvar.h>
53 #include <dev/i2c/m41st84reg.h>
54 #include <dev/i2c/m41st84var.h>
55
56 #include "ioconf.h"
57
58 struct strtc_model {
59 uint16_t sm_model;
60 uint8_t sm_nvram_start;
61 uint8_t sm_nvram_size;
62 uint32_t sm_flags;
63 };
64
65 #define STRTC_F_HAS_WDOG __BIT(0)
66
67 static const struct strtc_model m41t80_model = {
68 .sm_model = 80,
69 };
70
71 static const struct strtc_model m41t81_model = {
72 .sm_model = 81,
73 .sm_flags = STRTC_F_HAS_WDOG,
74 };
75
76 static const struct strtc_model m48t84_model = {
77 .sm_model = 84,
78 .sm_nvram_start = M41ST84_USER_RAM,
79 .sm_nvram_size = M41ST84_USER_RAM_SIZE,
80 .sm_flags = STRTC_F_HAS_WDOG,
81 };
82
83 static const struct device_compatible_entry compat_data[] = {
84 { .compat = "st,m41t80", .data = &m41t80_model },
85 { .compat = "st,m41t81", .data = &m41t81_model },
86 { .compat = "st,m41t84", .data = &m48t84_model },
87 DEVICE_COMPAT_EOL
88 };
89
90 struct strtc_softc {
91 device_t sc_dev;
92 i2c_tag_t sc_tag;
93 int sc_address;
94 int sc_open;
95 const struct strtc_model *sc_model;
96 struct todr_chip_handle sc_todr;
97 };
98
99 static void strtc_attach(device_t, device_t, void *);
100 static int strtc_match(device_t, cfdata_t, void *);
101
102 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc),
103 strtc_match, strtc_attach, NULL, NULL);
104
105 dev_type_open(strtc_open);
106 dev_type_close(strtc_close);
107 dev_type_read(strtc_read);
108 dev_type_write(strtc_write);
109
110 const struct cdevsw strtc_cdevsw = {
111 .d_open = strtc_open,
112 .d_close = strtc_close,
113 .d_read = strtc_read,
114 .d_write = strtc_write,
115 .d_ioctl = noioctl,
116 .d_stop = nostop,
117 .d_tty = notty,
118 .d_poll = nopoll,
119 .d_mmap = nommap,
120 .d_kqfilter = nokqfilter,
121 .d_discard = nodiscard,
122 .d_flag = D_OTHER
123 };
124
125 static int strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *);
126 static int strtc_gettime_ymdhms(struct todr_chip_handle *,
127 struct clock_ymdhms *);
128 static int strtc_settime_ymdhms(struct todr_chip_handle *,
129 struct clock_ymdhms *);
130
131 static const struct strtc_model *
strtc_model_by_number(u_int model)132 strtc_model_by_number(u_int model)
133 {
134 const struct device_compatible_entry *dce;
135 const struct strtc_model *sm;
136
137 /* no model given; assume it's a 41T80 */
138 if (model == 0)
139 return &m41t80_model;
140
141 for (dce = compat_data; dce->compat != NULL; dce++) {
142 sm = dce->data;
143 if (sm->sm_model == model)
144 return sm;
145 }
146 return NULL;
147 }
148
149 static const struct strtc_model *
strtc_model_by_compat(const struct i2c_attach_args * ia)150 strtc_model_by_compat(const struct i2c_attach_args *ia)
151 {
152 const struct device_compatible_entry *dce;
153 const struct strtc_model *sm = NULL;
154
155 if ((dce = iic_compatible_lookup(ia, compat_data)) != NULL)
156 sm = dce->data;
157
158 return sm;
159 }
160
161 static int
strtc_match(device_t parent,cfdata_t cf,void * arg)162 strtc_match(device_t parent, cfdata_t cf, void *arg)
163 {
164 struct i2c_attach_args *ia = arg;
165 int match_result;
166
167 if (iic_use_direct_match(ia, cf, compat_data, &match_result))
168 return match_result;
169
170 if (strtc_model_by_number(cf->cf_flags & 0xffff) == NULL)
171 return 0;
172
173 /* indirect config - check typical address */
174 if (ia->ia_addr == M41ST84_ADDR)
175 return I2C_MATCH_ADDRESS_ONLY;
176
177 return 0;
178 }
179
180 static void
strtc_attach(device_t parent,device_t self,void * arg)181 strtc_attach(device_t parent, device_t self, void *arg)
182 {
183 struct strtc_softc *sc = device_private(self);
184 struct i2c_attach_args *ia = arg;
185 const struct strtc_model *sm;
186
187 if ((sm = strtc_model_by_compat(ia)) == NULL)
188 sm = strtc_model_by_number(device_cfdata(self)->cf_flags);
189
190 if (sm == NULL) {
191 aprint_error(": unable to determine model!\n");
192 return;
193 }
194
195 aprint_naive(": Real-time Clock%s\n",
196 sm->sm_nvram_size ? "/NVRAM" : "");
197 aprint_normal(": M41T%d Real-time Clock%s\n", sm->sm_model,
198 sm->sm_nvram_size ? "/NVRAM" : "");
199
200 sc->sc_tag = ia->ia_tag;
201 sc->sc_address = ia->ia_addr;
202 sc->sc_model = sm;
203 sc->sc_dev = self;
204 sc->sc_open = 0;
205 sc->sc_todr.cookie = sc;
206 sc->sc_todr.todr_gettime = NULL;
207 sc->sc_todr.todr_settime = NULL;
208 sc->sc_todr.todr_gettime_ymdhms = strtc_gettime_ymdhms;
209 sc->sc_todr.todr_settime_ymdhms = strtc_settime_ymdhms;
210 sc->sc_todr.todr_setwen = NULL;
211
212 todr_attach(&sc->sc_todr);
213 }
214
215 /*ARGSUSED*/
216 int
strtc_open(dev_t dev,int flag,int fmt,struct lwp * l)217 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l)
218 {
219 struct strtc_softc *sc;
220
221 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
222 return (ENXIO);
223
224 /* XXX: Locking */
225
226 if (sc->sc_open)
227 return (EBUSY);
228
229 sc->sc_open = 1;
230 return (0);
231 }
232
233 /*ARGSUSED*/
234 int
strtc_close(dev_t dev,int flag,int fmt,struct lwp * l)235 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l)
236 {
237 struct strtc_softc *sc;
238
239 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
240 return (ENXIO);
241
242 sc->sc_open = 0;
243 return (0);
244 }
245
246 /*ARGSUSED*/
247 int
strtc_read(dev_t dev,struct uio * uio,int flags)248 strtc_read(dev_t dev, struct uio *uio, int flags)
249 {
250 struct strtc_softc *sc;
251 u_int8_t ch, cmdbuf[1];
252 int a, error;
253
254 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
255 return (ENXIO);
256
257 const struct strtc_model * const sm = sc->sc_model;
258
259 if (uio->uio_offset >= sm->sm_nvram_size)
260 return (EINVAL);
261
262 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
263 return (error);
264
265 while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) {
266 a = (int)uio->uio_offset;
267 cmdbuf[0] = a + sm->sm_nvram_start;
268 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
269 sc->sc_address, cmdbuf, 1,
270 &ch, 1, 0)) != 0) {
271 iic_release_bus(sc->sc_tag, 0);
272 aprint_error_dev(sc->sc_dev,
273 "strtc_read: read failed at 0x%x\n", a);
274 return (error);
275 }
276 if ((error = uiomove(&ch, 1, uio)) != 0) {
277 iic_release_bus(sc->sc_tag, 0);
278 return (error);
279 }
280 }
281
282 iic_release_bus(sc->sc_tag, 0);
283
284 return (0);
285 }
286
287 /*ARGSUSED*/
288 int
strtc_write(dev_t dev,struct uio * uio,int flags)289 strtc_write(dev_t dev, struct uio *uio, int flags)
290 {
291 struct strtc_softc *sc;
292 u_int8_t cmdbuf[2];
293 int a, error;
294
295 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
296 return (ENXIO);
297
298 const struct strtc_model * const sm = sc->sc_model;
299
300 if (uio->uio_offset >= sm->sm_nvram_size)
301 return (EINVAL);
302
303 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
304 return (error);
305
306 while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) {
307 a = (int)uio->uio_offset;
308 cmdbuf[0] = a + sm->sm_nvram_start;
309 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0)
310 break;
311
312 if ((error = iic_exec(sc->sc_tag,
313 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP,
314 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
315 aprint_error_dev(sc->sc_dev,
316 "strtc_write: write failed at 0x%x\n", a);
317 break;
318 }
319 }
320
321 iic_release_bus(sc->sc_tag, 0);
322
323 return (error);
324 }
325
326 static int
strtc_gettime_ymdhms(struct todr_chip_handle * ch,struct clock_ymdhms * dt)327 strtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
328 {
329 struct strtc_softc *sc = ch->cookie;
330 struct clock_ymdhms check;
331 int retries, error;
332
333 memset(dt, 0, sizeof(*dt));
334 memset(&check, 0, sizeof(check));
335
336 /*
337 * Since we don't support Burst Read, we have to read the clock twice
338 * until we get two consecutive identical results.
339 */
340 retries = 5;
341 do {
342 if ((error = strtc_clock_read(sc, dt)) == 0)
343 error = strtc_clock_read(sc, &check);
344 if (error)
345 return error;
346 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries);
347
348 return (0);
349 }
350
351 static int
strtc_clock_read(struct strtc_softc * sc,struct clock_ymdhms * dt)352 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt)
353 {
354 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2];
355 int i, error;
356
357 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
358 aprint_error_dev(sc->sc_dev,
359 "strtc_clock_read: failed to acquire I2C bus\n");
360 return (error);
361 }
362
363 /*
364 * Check for the HT bit -- if set, then clock lost power & stopped
365 * If that happened, then clear the bit so that the clock will have
366 * a chance to run again.
367 */
368 cmdbuf[0] = M41ST84_REG_AL_HOUR;
369 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
370 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
371 iic_release_bus(sc->sc_tag, 0);
372 aprint_error_dev(sc->sc_dev,
373 "strtc_clock_read: failed to read HT\n");
374 return (error);
375 }
376 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) {
377 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT;
378 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
379 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
380 iic_release_bus(sc->sc_tag, 0);
381 aprint_error_dev(sc->sc_dev,
382 "strtc_clock_read: failed to reset HT\n");
383 return (error);
384 }
385 }
386
387 /* Read each RTC register in order. */
388 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) {
389 cmdbuf[0] = i;
390
391 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
392 sc->sc_address, cmdbuf, 1,
393 &bcd[i], 1, 0)) != 0) {
394 iic_release_bus(sc->sc_tag, 0);
395 aprint_error_dev(sc->sc_dev,
396 "strtc_clock_read: failed to read rtc "
397 "at 0x%x\n", i);
398 return (error);
399 }
400 }
401
402 /* Done with I2C */
403 iic_release_bus(sc->sc_tag, 0);
404
405 /*
406 * Convert the M41ST84's register values into something useable
407 */
408 dt->dt_sec = bcdtobin(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK);
409 dt->dt_min = bcdtobin(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK);
410 dt->dt_hour = bcdtobin(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK);
411 dt->dt_day = bcdtobin(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK);
412 dt->dt_mon = bcdtobin(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK);
413
414 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */
415 /* XXX: Wait, isn't that what rtc_offset in todr_gettime() is for? */
416 dt->dt_year = bcdtobin(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR;
417
418 return (0);
419 }
420
421 static int
strtc_settime_ymdhms(struct todr_chip_handle * ch,struct clock_ymdhms * dt)422 strtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
423 {
424 struct strtc_softc *sc = ch->cookie;
425 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2];
426 int i, error;
427
428 /*
429 * Convert our time representation into something the M41ST84
430 * can understand.
431 */
432 bcd[M41ST84_REG_CSEC] = bintobcd(0); /* must always write as 0 */
433 bcd[M41ST84_REG_SEC] = bintobcd(dt->dt_sec);
434 bcd[M41ST84_REG_MIN] = bintobcd(dt->dt_min);
435 bcd[M41ST84_REG_CENHR] = bintobcd(dt->dt_hour);
436 bcd[M41ST84_REG_DATE] = bintobcd(dt->dt_day);
437 bcd[M41ST84_REG_DAY] = bintobcd(dt->dt_wday);
438 bcd[M41ST84_REG_MONTH] = bintobcd(dt->dt_mon);
439 bcd[M41ST84_REG_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100);
440
441 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
442 aprint_error_dev(sc->sc_dev,
443 "strtc_clock_write: failed to acquire I2C bus\n");
444 return (error);
445 }
446
447 /* Stop the clock */
448 cmdbuf[0] = M41ST84_REG_SEC;
449 cmdbuf[1] = M41ST84_SEC_ST;
450
451 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
452 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
453 iic_release_bus(sc->sc_tag, 0);
454 aprint_error_dev(sc->sc_dev,
455 "strtc_clock_write: failed to Hold Clock\n");
456 return (error);
457 }
458
459 /*
460 * Check for the HT bit -- if set, then clock lost power & stopped
461 * If that happened, then clear the bit so that the clock will have
462 * a chance to run again.
463 */
464 cmdbuf[0] = M41ST84_REG_AL_HOUR;
465 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
466 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
467 iic_release_bus(sc->sc_tag, 0);
468 aprint_error_dev(sc->sc_dev,
469 "strtc_clock_write: failed to read HT\n");
470 return (error);
471 }
472 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) {
473 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT;
474 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
475 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
476 iic_release_bus(sc->sc_tag, 0);
477 aprint_error_dev(sc->sc_dev,
478 "strtc_clock_write: failed to reset HT\n");
479 return (error);
480 }
481 }
482
483 /*
484 * Write registers in reverse order. The last write (to the Seconds
485 * register) will undo the Clock Hold, above.
486 */
487 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) {
488 cmdbuf[0] = i;
489 if ((error = iic_exec(sc->sc_tag,
490 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP,
491 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0)) != 0) {
492 iic_release_bus(sc->sc_tag, 0);
493 aprint_error_dev(sc->sc_dev,
494 "strtc_clock_write: failed to write rtc "
495 " at 0x%x\n", i);
496 /* XXX: Clock Hold is likely still asserted! */
497 return (error);
498 }
499 }
500
501 iic_release_bus(sc->sc_tag, 0);
502
503 return (0);
504 }
505
506 void
strtc_wdog_config(void * arg,uint8_t wd)507 strtc_wdog_config(void *arg, uint8_t wd)
508 {
509 struct strtc_softc *sc = arg;
510 uint8_t cmdbuf[2];
511
512 if ((sc->sc_model->sm_flags & STRTC_F_HAS_WDOG) == 0) {
513 aprint_error_dev(sc->sc_dev,
514 "strtc_wdog_config: watchdog timer not present\n");
515 return;
516 }
517
518 if (iic_acquire_bus(sc->sc_tag, 0)) {
519 aprint_error_dev(sc->sc_dev,
520 "strtc_wdog_config: failed to acquire I2C bus\n");
521 return;
522 }
523
524 cmdbuf[0] = M41ST84_REG_WATCHDOG;
525 cmdbuf[1] = wd;
526
527 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address,
528 cmdbuf, 1, &cmdbuf[1], 1, 0)) {
529 aprint_error_dev(sc->sc_dev,
530 "strtc_wdog_config: failed to write watchdog\n");
531 return;
532 }
533
534 iic_release_bus(sc->sc_tag, 0);
535 }
536