1 /* $NetBSD: axppmic.c,v 1.26 2019/10/01 23:32:52 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.26 2019/10/01 23:32:52 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 40 #include <dev/i2c/i2cvar.h> 41 42 #include <dev/sysmon/sysmonvar.h> 43 #include <dev/sysmon/sysmon_taskq.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define AXP_POWER_SOURCE_REG 0x00 48 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 49 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 50 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2) 51 52 #define AXP_POWER_MODE_REG 0x01 53 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 54 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 55 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 56 57 #define AXP_CHIP_ID_REG 0x03 58 59 #define AXP_POWER_DISABLE_REG 0x32 60 #define AXP_POWER_DISABLE_CTRL __BIT(7) 61 62 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 63 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 64 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 65 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 66 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 67 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 68 69 #define AXP_BATSENSE_HI_REG 0x78 70 #define AXP_BATSENSE_LO_REG 0x79 71 72 #define AXP_BATTCHG_HI_REG 0x7a 73 #define AXP_BATTCHG_LO_REG 0x7b 74 75 #define AXP_BATTDISCHG_HI_REG 0x7c 76 #define AXP_BATTDISCHG_LO_REG 0x7d 77 78 #define AXP_ADC_RAW(_hi, _lo) \ 79 (((u_int)(_hi) << 4) | ((_lo) & 0xf)) 80 81 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 82 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 83 84 #define AXP_BATT_CAP_REG 0xb9 85 #define AXP_BATT_CAP_VALID __BIT(7) 86 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 87 88 #define AXP_BATT_MAX_CAP_HI_REG 0xe0 89 #define AXP_BATT_MAX_CAP_VALID __BIT(7) 90 #define AXP_BATT_MAX_CAP_LO_REG 0xe1 91 92 #define AXP_BATT_COULOMB_HI_REG 0xe2 93 #define AXP_BATT_COULOMB_VALID __BIT(7) 94 #define AXP_BATT_COULOMB_LO_REG 0xe3 95 96 #define AXP_COULOMB_RAW(_hi, _lo) \ 97 (((u_int)(_hi & ~__BIT(7)) << 8) | (_lo)) 98 99 #define AXP_BATT_CAP_WARN_REG 0xe6 100 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 101 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 102 103 #define AXP_ADDR_EXT_REG 0xff /* AXP806 */ 104 #define AXP_ADDR_EXT_MASTER 0 105 #define AXP_ADDR_EXT_SLAVE __BIT(4) 106 107 struct axppmic_ctrl { 108 device_t c_dev; 109 110 const char * c_name; 111 u_int c_min; 112 u_int c_max; 113 u_int c_step1; 114 u_int c_step1cnt; 115 u_int c_step2; 116 u_int c_step2cnt; 117 u_int c_step2start; 118 119 uint8_t c_enable_reg; 120 uint8_t c_enable_mask; 121 uint8_t c_enable_val; 122 uint8_t c_disable_val; 123 124 uint8_t c_voltage_reg; 125 uint8_t c_voltage_mask; 126 }; 127 128 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 129 { .c_name = (name), .c_min = (min), .c_max = (max), \ 130 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 131 .c_step2 = 0, .c_step2cnt = 0, \ 132 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 133 .c_enable_val = (emask), .c_disable_val = 0, \ 134 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 135 136 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 137 { .c_name = (name), .c_min = (min), .c_max = (max), \ 138 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 139 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 140 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 141 .c_enable_val = (emask), .c_disable_val = 0, \ 142 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 143 144 #define AXP_CTRL2_RANGE(name, min, max, step1, step1cnt, step2start, step2, step2cnt, ereg, emask, vreg, vmask) \ 145 { .c_name = (name), .c_min = (min), .c_max = (max), \ 146 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 147 .c_step2start = (step2start), \ 148 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 149 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 150 .c_enable_val = (emask), .c_disable_val = 0, \ 151 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 152 153 #define AXP_CTRL_IO(name, min, max, step, ereg, emask, eval, dval, vreg, vmask) \ 154 { .c_name = (name), .c_min = (min), .c_max = (max), \ 155 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 156 .c_step2 = 0, .c_step2cnt = 0, \ 157 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 158 .c_enable_val = (eval), .c_disable_val = (dval), \ 159 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 160 161 #define AXP_CTRL_SW(name, ereg, emask) \ 162 { .c_name = (name), \ 163 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 164 .c_enable_val = (emask), .c_disable_val = 0 } 165 166 static const struct axppmic_ctrl axp803_ctrls[] = { 167 AXP_CTRL("dldo1", 700, 3300, 100, 168 0x12, __BIT(3), 0x15, __BITS(4,0)), 169 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 170 0x12, __BIT(4), 0x16, __BITS(4,0)), 171 AXP_CTRL("dldo3", 700, 3300, 100, 172 0x12, __BIT(5), 0x17, __BITS(4,0)), 173 AXP_CTRL("dldo4", 700, 3300, 100, 174 0x12, __BIT(6), 0x18, __BITS(4,0)), 175 AXP_CTRL("eldo1", 700, 1900, 50, 176 0x12, __BIT(0), 0x19, __BITS(4,0)), 177 AXP_CTRL("eldo2", 700, 1900, 50, 178 0x12, __BIT(1), 0x1a, __BITS(4,0)), 179 AXP_CTRL("eldo3", 700, 1900, 50, 180 0x12, __BIT(2), 0x1b, __BITS(4,0)), 181 AXP_CTRL("fldo1", 700, 1450, 50, 182 0x13, __BIT(2), 0x1c, __BITS(3,0)), 183 AXP_CTRL("fldo2", 700, 1450, 50, 184 0x13, __BIT(3), 0x1d, __BITS(3,0)), 185 AXP_CTRL("dcdc1", 1600, 3400, 100, 186 0x10, __BIT(0), 0x20, __BITS(4,0)), 187 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 188 0x10, __BIT(1), 0x21, __BITS(6,0)), 189 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 190 0x10, __BIT(2), 0x22, __BITS(6,0)), 191 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 192 0x10, __BIT(3), 0x23, __BITS(6,0)), 193 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 194 0x10, __BIT(4), 0x24, __BITS(6,0)), 195 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 196 0x10, __BIT(5), 0x25, __BITS(6,0)), 197 AXP_CTRL("aldo1", 700, 3300, 100, 198 0x13, __BIT(5), 0x28, __BITS(4,0)), 199 AXP_CTRL("aldo2", 700, 3300, 100, 200 0x13, __BIT(6), 0x29, __BITS(4,0)), 201 AXP_CTRL("aldo3", 700, 3300, 100, 202 0x13, __BIT(7), 0x2a, __BITS(4,0)), 203 }; 204 205 static const struct axppmic_ctrl axp805_ctrls[] = { 206 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 207 0x10, __BIT(0), 0x12, __BITS(6,0)), 208 AXP_CTRL("dcdcb", 1000, 2550, 50, 209 0x10, __BIT(1), 0x13, __BITS(4,0)), 210 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 211 0x10, __BIT(2), 0x14, __BITS(6,0)), 212 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 213 0x10, __BIT(3), 0x15, __BITS(5,0)), 214 AXP_CTRL("dcdce", 1100, 3400, 100, 215 0x10, __BIT(4), 0x16, __BITS(4,0)), 216 AXP_CTRL("aldo1", 700, 3300, 100, 217 0x10, __BIT(5), 0x17, __BITS(4,0)), 218 AXP_CTRL("aldo2", 700, 3400, 100, 219 0x10, __BIT(6), 0x18, __BITS(4,0)), 220 AXP_CTRL("aldo3", 700, 3300, 100, 221 0x10, __BIT(7), 0x19, __BITS(4,0)), 222 AXP_CTRL("bldo1", 700, 1900, 100, 223 0x11, __BIT(0), 0x20, __BITS(3,0)), 224 AXP_CTRL("bldo2", 700, 1900, 100, 225 0x11, __BIT(1), 0x21, __BITS(3,0)), 226 AXP_CTRL("bldo3", 700, 1900, 100, 227 0x11, __BIT(2), 0x22, __BITS(3,0)), 228 AXP_CTRL("bldo4", 700, 1900, 100, 229 0x11, __BIT(3), 0x23, __BITS(3,0)), 230 AXP_CTRL("cldo1", 700, 3300, 100, 231 0x11, __BIT(4), 0x24, __BITS(4,0)), 232 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 233 0x11, __BIT(5), 0x25, __BITS(4,0)), 234 AXP_CTRL("cldo3", 700, 3300, 100, 235 0x11, __BIT(6), 0x26, __BITS(4,0)), 236 }; 237 238 static const struct axppmic_ctrl axp809_ctrls[] = { 239 AXP_CTRL("dc5ldo", 700, 1400, 100, 240 0x10, __BIT(0), 0x1c, __BITS(2,0)), 241 AXP_CTRL("dcdc1", 1600, 3400, 100, 242 0x10, __BIT(1), 0x21, __BITS(4,0)), 243 AXP_CTRL("dcdc2", 600, 1540, 20, 244 0x10, __BIT(2), 0x22, __BITS(5,0)), 245 AXP_CTRL("dcdc3", 600, 1860, 20, 246 0x10, __BIT(3), 0x23, __BITS(5,0)), 247 AXP_CTRL2_RANGE("dcdc4", 600, 2600, 20, 47, 1800, 100, 9, 248 0x10, __BIT(4), 0x24, __BITS(5,0)), 249 AXP_CTRL("dcdc5", 1000, 2550, 50, 250 0x10, __BIT(5), 0x25, __BITS(4,0)), 251 AXP_CTRL("aldo1", 700, 3300, 100, 252 0x10, __BIT(6), 0x28, __BITS(4,0)), 253 AXP_CTRL("aldo2", 700, 3300, 100, 254 0x10, __BIT(7), 0x29, __BITS(4,0)), 255 AXP_CTRL("eldo1", 700, 3300, 100, 256 0x12, __BIT(0), 0x19, __BITS(4,0)), 257 AXP_CTRL("eldo2", 700, 3300, 100, 258 0x12, __BIT(1), 0x1a, __BITS(4,0)), 259 AXP_CTRL("eldo3", 700, 3300, 100, 260 0x12, __BIT(2), 0x1b, __BITS(4,0)), 261 AXP_CTRL2_RANGE("dldo1", 700, 4000, 100, 26, 3400, 200, 4, 262 0x12, __BIT(3), 0x15, __BITS(4,0)), 263 AXP_CTRL("dldo2", 700, 3300, 100, 264 0x12, __BIT(4), 0x16, __BITS(4,0)), 265 AXP_CTRL("aldo3", 700, 3300, 100, 266 0x12, __BIT(5), 0x2a, __BITS(4,0)), 267 AXP_CTRL_SW("sw", 268 0x12, __BIT(6)), 269 /* dc1sw is another switch for dcdc1 */ 270 AXP_CTRL("dc1sw", 1600, 3400, 100, 271 0x12, __BIT(7), 0x21, __BITS(4,0)), 272 AXP_CTRL_IO("ldo_io0", 700, 3300, 100, 273 0x90, __BITS(3,0), 0x3, 0x7, 0x91, __BITS(4,0)), 274 AXP_CTRL_IO("ldo_io1", 700, 3300, 100, 275 0x92, __BITS(3,0), 0x3, 0x7, 0x93, __BITS(4,0)), 276 }; 277 278 static const struct axppmic_ctrl axp813_ctrls[] = { 279 AXP_CTRL("dldo1", 700, 3300, 100, 280 0x12, __BIT(3), 0x15, __BITS(4,0)), 281 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 282 0x12, __BIT(4), 0x16, __BITS(4,0)), 283 AXP_CTRL("dldo3", 700, 3300, 100, 284 0x12, __BIT(5), 0x17, __BITS(4,0)), 285 AXP_CTRL("dldo4", 700, 3300, 100, 286 0x12, __BIT(6), 0x18, __BITS(4,0)), 287 AXP_CTRL("eldo1", 700, 1900, 50, 288 0x12, __BIT(0), 0x19, __BITS(4,0)), 289 AXP_CTRL("eldo2", 700, 1900, 50, 290 0x12, __BIT(1), 0x1a, __BITS(4,0)), 291 AXP_CTRL("eldo3", 700, 1900, 50, 292 0x12, __BIT(2), 0x1b, __BITS(4,0)), 293 AXP_CTRL("fldo1", 700, 1450, 50, 294 0x13, __BIT(2), 0x1c, __BITS(3,0)), 295 AXP_CTRL("fldo2", 700, 1450, 50, 296 0x13, __BIT(3), 0x1d, __BITS(3,0)), 297 AXP_CTRL("dcdc1", 1600, 3400, 100, 298 0x10, __BIT(0), 0x20, __BITS(4,0)), 299 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 300 0x10, __BIT(1), 0x21, __BITS(6,0)), 301 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 302 0x10, __BIT(2), 0x22, __BITS(6,0)), 303 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 304 0x10, __BIT(3), 0x23, __BITS(6,0)), 305 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 306 0x10, __BIT(4), 0x24, __BITS(6,0)), 307 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 308 0x10, __BIT(5), 0x25, __BITS(6,0)), 309 AXP_CTRL2("dcdc7", 600, 1520, 10, 51, 20, 21, 310 0x10, __BIT(6), 0x26, __BITS(6,0)), 311 AXP_CTRL("aldo1", 700, 3300, 100, 312 0x13, __BIT(5), 0x28, __BITS(4,0)), 313 AXP_CTRL("aldo2", 700, 3300, 100, 314 0x13, __BIT(6), 0x29, __BITS(4,0)), 315 AXP_CTRL("aldo3", 700, 3300, 100, 316 0x13, __BIT(7), 0x2a, __BITS(4,0)), 317 }; 318 319 struct axppmic_irq { 320 u_int reg; 321 uint8_t mask; 322 }; 323 324 #define AXPPMIC_IRQ(_reg, _mask) \ 325 { .reg = (_reg), .mask = (_mask) } 326 327 struct axppmic_config { 328 const char *name; 329 const struct axppmic_ctrl *controls; 330 u_int ncontrols; 331 u_int irq_regs; 332 bool has_battery; 333 bool has_fuel_gauge; 334 bool has_mode_set; 335 struct axppmic_irq poklirq; 336 struct axppmic_irq acinirq; 337 struct axppmic_irq vbusirq; 338 struct axppmic_irq battirq; 339 struct axppmic_irq chargeirq; 340 struct axppmic_irq chargestirq; 341 u_int batsense_step; /* uV */ 342 u_int charge_step; /* uA */ 343 u_int discharge_step; /* uA */ 344 u_int maxcap_step; /* uAh */ 345 u_int coulomb_step; /* uAh */ 346 }; 347 348 enum axppmic_sensor { 349 AXP_SENSOR_ACIN_PRESENT, 350 AXP_SENSOR_VBUS_PRESENT, 351 AXP_SENSOR_BATT_PRESENT, 352 AXP_SENSOR_BATT_CHARGING, 353 AXP_SENSOR_BATT_CHARGE_STATE, 354 AXP_SENSOR_BATT_VOLTAGE, 355 AXP_SENSOR_BATT_CHARGE_CURRENT, 356 AXP_SENSOR_BATT_DISCHARGE_CURRENT, 357 AXP_SENSOR_BATT_CAPACITY_PERCENT, 358 AXP_SENSOR_BATT_MAXIMUM_CAPACITY, 359 AXP_SENSOR_BATT_CURRENT_CAPACITY, 360 AXP_NSENSORS 361 }; 362 363 struct axppmic_softc { 364 device_t sc_dev; 365 i2c_tag_t sc_i2c; 366 i2c_addr_t sc_addr; 367 int sc_phandle; 368 369 const struct axppmic_config *sc_conf; 370 371 struct sysmon_pswitch sc_smpsw; 372 373 struct sysmon_envsys *sc_sme; 374 375 envsys_data_t sc_sensor[AXP_NSENSORS]; 376 377 u_int sc_warn_thres; 378 u_int sc_shut_thres; 379 }; 380 381 struct axpreg_softc { 382 device_t sc_dev; 383 i2c_tag_t sc_i2c; 384 i2c_addr_t sc_addr; 385 const struct axppmic_ctrl *sc_ctrl; 386 }; 387 388 struct axpreg_attach_args { 389 const struct axppmic_ctrl *reg_ctrl; 390 int reg_phandle; 391 i2c_tag_t reg_i2c; 392 i2c_addr_t reg_addr; 393 }; 394 395 static const struct axppmic_config axp803_config = { 396 .name = "AXP803", 397 .controls = axp803_ctrls, 398 .ncontrols = __arraycount(axp803_ctrls), 399 .irq_regs = 6, 400 .has_battery = true, 401 .has_fuel_gauge = true, 402 .batsense_step = 1100, 403 .charge_step = 1000, 404 .discharge_step = 1000, 405 .maxcap_step = 1456, 406 .coulomb_step = 1456, 407 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 408 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 409 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 410 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 411 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 412 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 413 }; 414 415 static const struct axppmic_config axp805_config = { 416 .name = "AXP805", 417 .controls = axp805_ctrls, 418 .ncontrols = __arraycount(axp805_ctrls), 419 .irq_regs = 2, 420 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 421 }; 422 423 static const struct axppmic_config axp806_config = { 424 .name = "AXP806", 425 .controls = axp805_ctrls, 426 .ncontrols = __arraycount(axp805_ctrls), 427 #if notyet 428 .irq_regs = 2, 429 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 430 #endif 431 .has_mode_set = true, 432 }; 433 434 static const struct axppmic_config axp809_config = { 435 .name = "AXP809", 436 .controls = axp809_ctrls, 437 .ncontrols = __arraycount(axp809_ctrls), 438 }; 439 440 static const struct axppmic_config axp813_config = { 441 .name = "AXP813", 442 .controls = axp813_ctrls, 443 .ncontrols = __arraycount(axp813_ctrls), 444 .irq_regs = 6, 445 .has_battery = true, 446 .has_fuel_gauge = true, 447 .batsense_step = 1100, 448 .charge_step = 1000, 449 .discharge_step = 1000, 450 .maxcap_step = 1456, 451 .coulomb_step = 1456, 452 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 453 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 454 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 455 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 456 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 457 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 458 }; 459 460 static const struct device_compatible_entry compat_data[] = { 461 { "x-powers,axp803", (uintptr_t)&axp803_config }, 462 { "x-powers,axp805", (uintptr_t)&axp805_config }, 463 { "x-powers,axp806", (uintptr_t)&axp806_config }, 464 { "x-powers,axp809", (uintptr_t)&axp809_config }, 465 { "x-powers,axp813", (uintptr_t)&axp813_config }, 466 { NULL, 0 } 467 }; 468 469 static int 470 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 471 { 472 return iic_smbus_read_byte(tag, addr, reg, val, flags); 473 } 474 475 static int 476 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 477 { 478 return iic_smbus_write_byte(tag, addr, reg, val, flags); 479 } 480 481 static int 482 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 483 { 484 const int flags = 0; 485 u_int vol, reg_val; 486 int nstep, error; 487 uint8_t val; 488 489 if (!c->c_voltage_mask) 490 return EINVAL; 491 492 if (min < c->c_min || min > c->c_max) 493 return EINVAL; 494 495 reg_val = 0; 496 nstep = 1; 497 vol = c->c_min; 498 499 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 500 ++reg_val; 501 vol += c->c_step1; 502 } 503 504 if (c->c_step2start) 505 vol = c->c_step2start; 506 507 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 508 ++reg_val; 509 vol += c->c_step2; 510 } 511 512 if (vol > max) 513 return EINVAL; 514 515 iic_acquire_bus(tag, flags); 516 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags)) == 0) { 517 val &= ~c->c_voltage_mask; 518 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 519 error = axppmic_write(tag, addr, c->c_voltage_reg, val, flags); 520 } 521 iic_release_bus(tag, flags); 522 523 return error; 524 } 525 526 static int 527 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 528 { 529 const int flags = 0; 530 int reg_val, error; 531 uint8_t val; 532 533 if (!c->c_voltage_mask) 534 return EINVAL; 535 536 iic_acquire_bus(tag, flags); 537 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags); 538 iic_release_bus(tag, flags); 539 if (error) 540 return error; 541 542 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 543 if (reg_val < c->c_step1cnt) { 544 *pvol = c->c_min + reg_val * c->c_step1; 545 } else if (c->c_step2start) { 546 *pvol = c->c_step2start + 547 ((reg_val - c->c_step1cnt) * c->c_step2); 548 } else { 549 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 550 ((reg_val - c->c_step1cnt) * c->c_step2); 551 } 552 553 return 0; 554 } 555 556 static void 557 axppmic_power_poweroff(device_t dev) 558 { 559 struct axppmic_softc *sc = device_private(dev); 560 561 delay(1000000); 562 563 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 564 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, I2C_F_POLL); 565 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 566 } 567 568 static struct fdtbus_power_controller_func axppmic_power_funcs = { 569 .poweroff = axppmic_power_poweroff, 570 }; 571 572 static void 573 axppmic_task_shut(void *priv) 574 { 575 struct axppmic_softc *sc = priv; 576 577 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 578 } 579 580 static void 581 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 582 { 583 struct axppmic_softc *sc = sme->sme_cookie; 584 const struct axppmic_config *c = sc->sc_conf; 585 const int flags = I2C_F_POLL; 586 uint8_t val, lo, hi; 587 588 e->state = ENVSYS_SINVALID; 589 590 const bool battery_present = 591 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID && 592 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1; 593 594 switch (e->private) { 595 case AXP_SENSOR_ACIN_PRESENT: 596 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 597 e->state = ENVSYS_SVALID; 598 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 599 } 600 break; 601 case AXP_SENSOR_VBUS_PRESENT: 602 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 603 e->state = ENVSYS_SVALID; 604 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 605 } 606 break; 607 case AXP_SENSOR_BATT_PRESENT: 608 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 609 if (val & AXP_POWER_MODE_BATT_VALID) { 610 e->state = ENVSYS_SVALID; 611 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 612 } 613 } 614 break; 615 case AXP_SENSOR_BATT_CHARGING: 616 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 617 e->state = ENVSYS_SVALID; 618 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 619 } 620 break; 621 case AXP_SENSOR_BATT_CHARGE_STATE: 622 if (battery_present && 623 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 624 (val & AXP_BATT_CAP_VALID) != 0) { 625 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 626 if (batt_val <= sc->sc_shut_thres) { 627 e->state = ENVSYS_SCRITICAL; 628 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 629 } else if (batt_val <= sc->sc_warn_thres) { 630 e->state = ENVSYS_SWARNUNDER; 631 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 632 } else { 633 e->state = ENVSYS_SVALID; 634 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 635 } 636 } 637 break; 638 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 639 if (battery_present && 640 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 641 (val & AXP_BATT_CAP_VALID) != 0) { 642 e->state = ENVSYS_SVALID; 643 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 644 } 645 break; 646 case AXP_SENSOR_BATT_VOLTAGE: 647 if (battery_present && 648 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, flags) == 0 && 649 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, flags) == 0) { 650 e->state = ENVSYS_SVALID; 651 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step; 652 } 653 break; 654 case AXP_SENSOR_BATT_CHARGE_CURRENT: 655 if (battery_present && 656 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 && 657 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 && 658 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, flags) == 0 && 659 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, flags) == 0) { 660 e->state = ENVSYS_SVALID; 661 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step; 662 } 663 break; 664 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 665 if (battery_present && 666 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 && 667 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 && 668 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, flags) == 0 && 669 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, flags) == 0) { 670 e->state = ENVSYS_SVALID; 671 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step; 672 } 673 break; 674 case AXP_SENSOR_BATT_MAXIMUM_CAPACITY: 675 if (battery_present && 676 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_HI_REG, &hi, flags) == 0 && 677 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_LO_REG, &lo, flags) == 0) { 678 e->state = (hi & AXP_BATT_MAX_CAP_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 679 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->maxcap_step; 680 } 681 break; 682 case AXP_SENSOR_BATT_CURRENT_CAPACITY: 683 if (battery_present && 684 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_HI_REG, &hi, flags) == 0 && 685 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_LO_REG, &lo, flags) == 0) { 686 e->state = (hi & AXP_BATT_COULOMB_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 687 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->coulomb_step; 688 } 689 break; 690 } 691 } 692 693 static void 694 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 695 { 696 struct axppmic_softc *sc = sme->sme_cookie; 697 const int flags = I2C_F_POLL; 698 699 switch (e->private) { 700 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 701 case AXP_SENSOR_BATT_VOLTAGE: 702 case AXP_SENSOR_BATT_CHARGE_CURRENT: 703 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 704 /* Always update battery capacity and ADCs */ 705 iic_acquire_bus(sc->sc_i2c, flags); 706 axppmic_sensor_update(sme, e); 707 iic_release_bus(sc->sc_i2c, flags); 708 break; 709 default: 710 /* Refresh if the sensor is not in valid state */ 711 if (e->state != ENVSYS_SVALID) { 712 iic_acquire_bus(sc->sc_i2c, flags); 713 axppmic_sensor_update(sme, e); 714 iic_release_bus(sc->sc_i2c, flags); 715 } 716 break; 717 } 718 } 719 720 static int 721 axppmic_intr(void *priv) 722 { 723 struct axppmic_softc *sc = priv; 724 const struct axppmic_config *c = sc->sc_conf; 725 const int flags = I2C_F_POLL; 726 uint8_t stat; 727 u_int n; 728 729 iic_acquire_bus(sc->sc_i2c, flags); 730 for (n = 1; n <= c->irq_regs; n++) { 731 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 732 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 733 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 734 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 735 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 736 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 737 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 738 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 739 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 740 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 741 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 742 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 743 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 744 745 if (stat != 0) 746 axppmic_write(sc->sc_i2c, sc->sc_addr, 747 AXP_IRQ_STATUS_REG(n), stat, flags); 748 } 749 } 750 iic_release_bus(sc->sc_i2c, flags); 751 752 return 1; 753 } 754 755 static void 756 axppmic_attach_acadapter(struct axppmic_softc *sc) 757 { 758 envsys_data_t *e; 759 760 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 761 e->private = AXP_SENSOR_ACIN_PRESENT; 762 e->units = ENVSYS_INDICATOR; 763 e->state = ENVSYS_SINVALID; 764 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 765 sysmon_envsys_sensor_attach(sc->sc_sme, e); 766 767 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 768 e->private = AXP_SENSOR_VBUS_PRESENT; 769 e->units = ENVSYS_INDICATOR; 770 e->state = ENVSYS_SINVALID; 771 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 772 sysmon_envsys_sensor_attach(sc->sc_sme, e); 773 } 774 775 static void 776 axppmic_attach_battery(struct axppmic_softc *sc) 777 { 778 const struct axppmic_config *c = sc->sc_conf; 779 envsys_data_t *e; 780 uint8_t val; 781 782 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 783 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, I2C_F_POLL) == 0) { 784 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 785 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 786 } 787 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 788 789 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 790 e->private = AXP_SENSOR_BATT_PRESENT; 791 e->units = ENVSYS_INDICATOR; 792 e->state = ENVSYS_SINVALID; 793 strlcpy(e->desc, "battery present", sizeof(e->desc)); 794 sysmon_envsys_sensor_attach(sc->sc_sme, e); 795 796 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 797 e->private = AXP_SENSOR_BATT_CHARGING; 798 e->units = ENVSYS_BATTERY_CHARGE; 799 e->state = ENVSYS_SINVALID; 800 strlcpy(e->desc, "charging", sizeof(e->desc)); 801 sysmon_envsys_sensor_attach(sc->sc_sme, e); 802 803 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 804 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 805 e->units = ENVSYS_BATTERY_CAPACITY; 806 e->flags = ENVSYS_FMONSTCHANGED; 807 e->state = ENVSYS_SINVALID; 808 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 809 strlcpy(e->desc, "charge state", sizeof(e->desc)); 810 sysmon_envsys_sensor_attach(sc->sc_sme, e); 811 812 if (c->batsense_step) { 813 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE]; 814 e->private = AXP_SENSOR_BATT_VOLTAGE; 815 e->units = ENVSYS_SVOLTS_DC; 816 e->state = ENVSYS_SINVALID; 817 strlcpy(e->desc, "battery voltage", sizeof(e->desc)); 818 sysmon_envsys_sensor_attach(sc->sc_sme, e); 819 } 820 821 if (c->charge_step) { 822 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT]; 823 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT; 824 e->units = ENVSYS_SAMPS; 825 e->state = ENVSYS_SINVALID; 826 strlcpy(e->desc, "battery charge current", sizeof(e->desc)); 827 sysmon_envsys_sensor_attach(sc->sc_sme, e); 828 } 829 830 if (c->discharge_step) { 831 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT]; 832 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT; 833 e->units = ENVSYS_SAMPS; 834 e->state = ENVSYS_SINVALID; 835 strlcpy(e->desc, "battery discharge current", sizeof(e->desc)); 836 sysmon_envsys_sensor_attach(sc->sc_sme, e); 837 } 838 839 if (c->has_fuel_gauge) { 840 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT]; 841 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT; 842 e->units = ENVSYS_INTEGER; 843 e->state = ENVSYS_SINVALID; 844 e->flags = ENVSYS_FPERCENT; 845 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 846 sysmon_envsys_sensor_attach(sc->sc_sme, e); 847 } 848 849 if (c->maxcap_step) { 850 e = &sc->sc_sensor[AXP_SENSOR_BATT_MAXIMUM_CAPACITY]; 851 e->private = AXP_SENSOR_BATT_MAXIMUM_CAPACITY; 852 e->units = ENVSYS_SAMPHOUR; 853 e->state = ENVSYS_SINVALID; 854 strlcpy(e->desc, "battery maximum capacity", sizeof(e->desc)); 855 sysmon_envsys_sensor_attach(sc->sc_sme, e); 856 } 857 858 if (c->coulomb_step) { 859 e = &sc->sc_sensor[AXP_SENSOR_BATT_CURRENT_CAPACITY]; 860 e->private = AXP_SENSOR_BATT_CURRENT_CAPACITY; 861 e->units = ENVSYS_SAMPHOUR; 862 e->state = ENVSYS_SINVALID; 863 strlcpy(e->desc, "battery current capacity", sizeof(e->desc)); 864 sysmon_envsys_sensor_attach(sc->sc_sme, e); 865 } 866 } 867 868 static void 869 axppmic_attach_sensors(struct axppmic_softc *sc) 870 { 871 if (sc->sc_conf->has_battery) { 872 sc->sc_sme = sysmon_envsys_create(); 873 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 874 sc->sc_sme->sme_cookie = sc; 875 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 876 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 877 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 878 879 axppmic_attach_acadapter(sc); 880 axppmic_attach_battery(sc); 881 882 sysmon_envsys_register(sc->sc_sme); 883 } 884 } 885 886 887 static int 888 axppmic_match(device_t parent, cfdata_t match, void *aux) 889 { 890 struct i2c_attach_args *ia = aux; 891 int match_result; 892 893 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 894 return match_result; 895 896 /* This device is direct-config only. */ 897 898 return 0; 899 } 900 901 static void 902 axppmic_attach(device_t parent, device_t self, void *aux) 903 { 904 struct axppmic_softc *sc = device_private(self); 905 const struct device_compatible_entry *dce = NULL; 906 const struct axppmic_config *c; 907 struct axpreg_attach_args aaa; 908 struct i2c_attach_args *ia = aux; 909 int phandle, child, i; 910 uint8_t irq_mask, val; 911 int error; 912 void *ih; 913 914 (void) iic_compatible_match(ia, compat_data, &dce); 915 KASSERT(dce != NULL); 916 c = (void *)dce->data; 917 918 sc->sc_dev = self; 919 sc->sc_i2c = ia->ia_tag; 920 sc->sc_addr = ia->ia_addr; 921 sc->sc_phandle = ia->ia_cookie; 922 sc->sc_conf = c; 923 924 aprint_naive("\n"); 925 aprint_normal(": %s\n", c->name); 926 927 if (c->has_mode_set) { 928 const bool master_mode = of_hasprop(sc->sc_phandle, "x-powers,self-working-mode") || 929 of_hasprop(sc->sc_phandle, "x-powers,master-mode"); 930 931 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 932 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_ADDR_EXT_REG, 933 master_mode ? AXP_ADDR_EXT_MASTER : AXP_ADDR_EXT_SLAVE, I2C_F_POLL); 934 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 935 } 936 937 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 938 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_CHIP_ID_REG, &val, I2C_F_POLL); 939 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 940 if (error != 0) { 941 aprint_error_dev(self, "couldn't read chipid\n"); 942 return; 943 } 944 aprint_debug_dev(self, "chipid %#x\n", val); 945 946 sc->sc_smpsw.smpsw_name = device_xname(self); 947 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 948 sysmon_pswitch_register(&sc->sc_smpsw); 949 950 if (c->irq_regs > 0) { 951 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 952 for (i = 1; i <= c->irq_regs; i++) { 953 irq_mask = 0; 954 if (i == c->poklirq.reg) 955 irq_mask |= c->poklirq.mask; 956 if (i == c->acinirq.reg) 957 irq_mask |= c->acinirq.mask; 958 if (i == c->vbusirq.reg) 959 irq_mask |= c->vbusirq.mask; 960 if (i == c->battirq.reg) 961 irq_mask |= c->battirq.mask; 962 if (i == c->chargeirq.reg) 963 irq_mask |= c->chargeirq.mask; 964 if (i == c->chargestirq.reg) 965 irq_mask |= c->chargestirq.mask; 966 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_IRQ_ENABLE_REG(i), irq_mask, I2C_F_POLL); 967 } 968 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 969 970 ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 971 axppmic_intr, sc); 972 if (ih == NULL) { 973 aprint_error_dev(self, "WARNING: couldn't establish interrupt handler\n"); 974 } 975 } 976 977 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 978 &axppmic_power_funcs); 979 980 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 981 if (phandle > 0) { 982 aaa.reg_i2c = sc->sc_i2c; 983 aaa.reg_addr = sc->sc_addr; 984 for (i = 0; i < c->ncontrols; i++) { 985 const struct axppmic_ctrl *ctrl = &c->controls[i]; 986 child = of_find_firstchild_byname(phandle, ctrl->c_name); 987 if (child <= 0) 988 continue; 989 aaa.reg_ctrl = ctrl; 990 aaa.reg_phandle = child; 991 config_found(sc->sc_dev, &aaa, NULL); 992 } 993 } 994 995 if (c->has_battery) 996 axppmic_attach_sensors(sc); 997 } 998 999 static int 1000 axpreg_acquire(device_t dev) 1001 { 1002 return 0; 1003 } 1004 1005 static void 1006 axpreg_release(device_t dev) 1007 { 1008 } 1009 1010 static int 1011 axpreg_enable(device_t dev, bool enable) 1012 { 1013 struct axpreg_softc *sc = device_private(dev); 1014 const struct axppmic_ctrl *c = sc->sc_ctrl; 1015 const int flags = 0; 1016 uint8_t val; 1017 int error; 1018 1019 if (!c->c_enable_mask) 1020 return EINVAL; 1021 1022 iic_acquire_bus(sc->sc_i2c, flags); 1023 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 1024 val &= ~c->c_enable_mask; 1025 if (enable) 1026 val |= c->c_enable_val; 1027 else 1028 val |= c->c_disable_val; 1029 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 1030 } 1031 iic_release_bus(sc->sc_i2c, flags); 1032 1033 return error; 1034 } 1035 1036 static int 1037 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 1038 { 1039 struct axpreg_softc *sc = device_private(dev); 1040 const struct axppmic_ctrl *c = sc->sc_ctrl; 1041 1042 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 1043 min_uvol / 1000, max_uvol / 1000); 1044 } 1045 1046 static int 1047 axpreg_get_voltage(device_t dev, u_int *puvol) 1048 { 1049 struct axpreg_softc *sc = device_private(dev); 1050 const struct axppmic_ctrl *c = sc->sc_ctrl; 1051 int error; 1052 u_int vol; 1053 1054 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 1055 if (error) 1056 return error; 1057 1058 *puvol = vol * 1000; 1059 return 0; 1060 } 1061 1062 static struct fdtbus_regulator_controller_func axpreg_funcs = { 1063 .acquire = axpreg_acquire, 1064 .release = axpreg_release, 1065 .enable = axpreg_enable, 1066 .set_voltage = axpreg_set_voltage, 1067 .get_voltage = axpreg_get_voltage, 1068 }; 1069 1070 static int 1071 axpreg_match(device_t parent, cfdata_t match, void *aux) 1072 { 1073 return 1; 1074 } 1075 1076 static void 1077 axpreg_attach(device_t parent, device_t self, void *aux) 1078 { 1079 struct axpreg_softc *sc = device_private(self); 1080 struct axpreg_attach_args *aaa = aux; 1081 const int phandle = aaa->reg_phandle; 1082 const char *name; 1083 u_int uvol, min_uvol, max_uvol; 1084 1085 sc->sc_dev = self; 1086 sc->sc_i2c = aaa->reg_i2c; 1087 sc->sc_addr = aaa->reg_addr; 1088 sc->sc_ctrl = aaa->reg_ctrl; 1089 1090 fdtbus_register_regulator_controller(self, phandle, 1091 &axpreg_funcs); 1092 1093 aprint_naive("\n"); 1094 name = fdtbus_get_string(phandle, "regulator-name"); 1095 if (name) 1096 aprint_normal(": %s\n", name); 1097 else 1098 aprint_normal("\n"); 1099 1100 axpreg_get_voltage(self, &uvol); 1101 if (of_getprop_uint32(phandle, "regulator-min-microvolt", &min_uvol) == 0 && 1102 of_getprop_uint32(phandle, "regulator-max-microvolt", &max_uvol) == 0) { 1103 if (uvol < min_uvol || uvol > max_uvol) { 1104 aprint_debug_dev(self, "fix voltage %u uV -> %u/%u uV\n", 1105 uvol, min_uvol, max_uvol); 1106 axpreg_set_voltage(self, min_uvol, max_uvol); 1107 } 1108 } 1109 1110 if (of_hasprop(phandle, "regulator-always-on") || 1111 of_hasprop(phandle, "regulator-boot-on")) { 1112 axpreg_enable(self, true); 1113 } 1114 } 1115 1116 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 1117 axppmic_match, axppmic_attach, NULL, NULL); 1118 1119 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 1120 axpreg_match, axpreg_attach, NULL, NULL); 1121