1 /* $NetBSD: axppmic.c,v 1.37 2022/10/30 11:51:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.37 2022/10/30 11:51:19 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 #include <sys/workqueue.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 #include <dev/sysmon/sysmon_taskq.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define AXP_POWER_SOURCE_REG 0x00 49 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 50 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 51 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2) 52 53 #define AXP_POWER_MODE_REG 0x01 54 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 55 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 56 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 57 58 #define AXP_CHIP_ID_REG 0x03 59 60 #define AXP_POWER_DISABLE_REG 0x32 61 #define AXP_POWER_DISABLE_CTRL __BIT(7) 62 63 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 64 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 65 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 66 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 67 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 68 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 69 70 #define AXP_BATSENSE_HI_REG 0x78 71 #define AXP_BATSENSE_LO_REG 0x79 72 73 #define AXP_BATTCHG_HI_REG 0x7a 74 #define AXP_BATTCHG_LO_REG 0x7b 75 76 #define AXP_BATTDISCHG_HI_REG 0x7c 77 #define AXP_BATTDISCHG_LO_REG 0x7d 78 79 #define AXP_ADC_RAW(_hi, _lo) \ 80 (((u_int)(_hi) << 4) | ((_lo) & 0xf)) 81 82 #define AXP_GPIO_CTRL_REG(pin) (0x90 + (pin) * 2) 83 #define AXP_GPIO_CTRL_FUNC_MASK __BITS(2,0) 84 #define AXP_GPIO_CTRL_FUNC_LOW 0 85 #define AXP_GPIO_CTRL_FUNC_HIGH 1 86 #define AXP_GPIO_CTRL_FUNC_INPUT 2 87 #define AXP_GPIO_SIGNAL_REG 0x94 88 89 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 90 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 91 92 #define AXP_BATT_CAP_REG 0xb9 93 #define AXP_BATT_CAP_VALID __BIT(7) 94 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 95 96 #define AXP_BATT_MAX_CAP_HI_REG 0xe0 97 #define AXP_BATT_MAX_CAP_VALID __BIT(7) 98 #define AXP_BATT_MAX_CAP_LO_REG 0xe1 99 100 #define AXP_BATT_COULOMB_HI_REG 0xe2 101 #define AXP_BATT_COULOMB_VALID __BIT(7) 102 #define AXP_BATT_COULOMB_LO_REG 0xe3 103 104 #define AXP_COULOMB_RAW(_hi, _lo) \ 105 (((u_int)(_hi & ~__BIT(7)) << 8) | (_lo)) 106 107 #define AXP_BATT_CAP_WARN_REG 0xe6 108 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 109 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 110 111 #define AXP_ADDR_EXT_REG 0xff /* AXP806 */ 112 #define AXP_ADDR_EXT_MASTER 0 113 #define AXP_ADDR_EXT_SLAVE __BIT(4) 114 115 struct axppmic_ctrl { 116 device_t c_dev; 117 118 const char * c_name; 119 u_int c_min; 120 u_int c_max; 121 u_int c_step1; 122 u_int c_step1cnt; 123 u_int c_step2; 124 u_int c_step2cnt; 125 u_int c_step2start; 126 127 uint8_t c_enable_reg; 128 uint8_t c_enable_mask; 129 uint8_t c_enable_val; 130 uint8_t c_disable_val; 131 132 uint8_t c_voltage_reg; 133 uint8_t c_voltage_mask; 134 }; 135 136 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 137 { .c_name = (name), .c_min = (min), .c_max = (max), \ 138 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 139 .c_step2 = 0, .c_step2cnt = 0, \ 140 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 141 .c_enable_val = (emask), .c_disable_val = 0, \ 142 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 143 144 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 145 { .c_name = (name), .c_min = (min), .c_max = (max), \ 146 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 147 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 148 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 149 .c_enable_val = (emask), .c_disable_val = 0, \ 150 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 151 152 #define AXP_CTRL2_RANGE(name, min, max, step1, step1cnt, step2start, step2, step2cnt, ereg, emask, vreg, vmask) \ 153 { .c_name = (name), .c_min = (min), .c_max = (max), \ 154 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 155 .c_step2start = (step2start), \ 156 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 157 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 158 .c_enable_val = (emask), .c_disable_val = 0, \ 159 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 160 161 #define AXP_CTRL_IO(name, min, max, step, ereg, emask, eval, dval, vreg, vmask) \ 162 { .c_name = (name), .c_min = (min), .c_max = (max), \ 163 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 164 .c_step2 = 0, .c_step2cnt = 0, \ 165 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 166 .c_enable_val = (eval), .c_disable_val = (dval), \ 167 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 168 169 #define AXP_CTRL_SW(name, ereg, emask) \ 170 { .c_name = (name), \ 171 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 172 .c_enable_val = (emask), .c_disable_val = 0 } 173 174 static const struct axppmic_ctrl axp803_ctrls[] = { 175 AXP_CTRL("dldo1", 700, 3300, 100, 176 0x12, __BIT(3), 0x15, __BITS(4,0)), 177 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 178 0x12, __BIT(4), 0x16, __BITS(4,0)), 179 AXP_CTRL("dldo3", 700, 3300, 100, 180 0x12, __BIT(5), 0x17, __BITS(4,0)), 181 AXP_CTRL("dldo4", 700, 3300, 100, 182 0x12, __BIT(6), 0x18, __BITS(4,0)), 183 AXP_CTRL("eldo1", 700, 1900, 50, 184 0x12, __BIT(0), 0x19, __BITS(4,0)), 185 AXP_CTRL("eldo2", 700, 1900, 50, 186 0x12, __BIT(1), 0x1a, __BITS(4,0)), 187 AXP_CTRL("eldo3", 700, 1900, 50, 188 0x12, __BIT(2), 0x1b, __BITS(4,0)), 189 AXP_CTRL("fldo1", 700, 1450, 50, 190 0x13, __BIT(2), 0x1c, __BITS(3,0)), 191 AXP_CTRL("fldo2", 700, 1450, 50, 192 0x13, __BIT(3), 0x1d, __BITS(3,0)), 193 AXP_CTRL("dcdc1", 1600, 3400, 100, 194 0x10, __BIT(0), 0x20, __BITS(4,0)), 195 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 196 0x10, __BIT(1), 0x21, __BITS(6,0)), 197 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 198 0x10, __BIT(2), 0x22, __BITS(6,0)), 199 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 200 0x10, __BIT(3), 0x23, __BITS(6,0)), 201 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 202 0x10, __BIT(4), 0x24, __BITS(6,0)), 203 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 204 0x10, __BIT(5), 0x25, __BITS(6,0)), 205 AXP_CTRL("aldo1", 700, 3300, 100, 206 0x13, __BIT(5), 0x28, __BITS(4,0)), 207 AXP_CTRL("aldo2", 700, 3300, 100, 208 0x13, __BIT(6), 0x29, __BITS(4,0)), 209 AXP_CTRL("aldo3", 700, 3300, 100, 210 0x13, __BIT(7), 0x2a, __BITS(4,0)), 211 }; 212 213 static const struct axppmic_ctrl axp805_ctrls[] = { 214 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 215 0x10, __BIT(0), 0x12, __BITS(6,0)), 216 AXP_CTRL("dcdcb", 1000, 2550, 50, 217 0x10, __BIT(1), 0x13, __BITS(4,0)), 218 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 219 0x10, __BIT(2), 0x14, __BITS(6,0)), 220 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 221 0x10, __BIT(3), 0x15, __BITS(5,0)), 222 AXP_CTRL("dcdce", 1100, 3400, 100, 223 0x10, __BIT(4), 0x16, __BITS(4,0)), 224 AXP_CTRL("aldo1", 700, 3300, 100, 225 0x10, __BIT(5), 0x17, __BITS(4,0)), 226 AXP_CTRL("aldo2", 700, 3400, 100, 227 0x10, __BIT(6), 0x18, __BITS(4,0)), 228 AXP_CTRL("aldo3", 700, 3300, 100, 229 0x10, __BIT(7), 0x19, __BITS(4,0)), 230 AXP_CTRL("bldo1", 700, 1900, 100, 231 0x11, __BIT(0), 0x20, __BITS(3,0)), 232 AXP_CTRL("bldo2", 700, 1900, 100, 233 0x11, __BIT(1), 0x21, __BITS(3,0)), 234 AXP_CTRL("bldo3", 700, 1900, 100, 235 0x11, __BIT(2), 0x22, __BITS(3,0)), 236 AXP_CTRL("bldo4", 700, 1900, 100, 237 0x11, __BIT(3), 0x23, __BITS(3,0)), 238 AXP_CTRL("cldo1", 700, 3300, 100, 239 0x11, __BIT(4), 0x24, __BITS(4,0)), 240 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 241 0x11, __BIT(5), 0x25, __BITS(4,0)), 242 AXP_CTRL("cldo3", 700, 3300, 100, 243 0x11, __BIT(6), 0x26, __BITS(4,0)), 244 }; 245 246 static const struct axppmic_ctrl axp809_ctrls[] = { 247 AXP_CTRL("dc5ldo", 700, 1400, 100, 248 0x10, __BIT(0), 0x1c, __BITS(2,0)), 249 AXP_CTRL("dcdc1", 1600, 3400, 100, 250 0x10, __BIT(1), 0x21, __BITS(4,0)), 251 AXP_CTRL("dcdc2", 600, 1540, 20, 252 0x10, __BIT(2), 0x22, __BITS(5,0)), 253 AXP_CTRL("dcdc3", 600, 1860, 20, 254 0x10, __BIT(3), 0x23, __BITS(5,0)), 255 AXP_CTRL2_RANGE("dcdc4", 600, 2600, 20, 47, 1800, 100, 9, 256 0x10, __BIT(4), 0x24, __BITS(5,0)), 257 AXP_CTRL("dcdc5", 1000, 2550, 50, 258 0x10, __BIT(5), 0x25, __BITS(4,0)), 259 AXP_CTRL("aldo1", 700, 3300, 100, 260 0x10, __BIT(6), 0x28, __BITS(4,0)), 261 AXP_CTRL("aldo2", 700, 3300, 100, 262 0x10, __BIT(7), 0x29, __BITS(4,0)), 263 AXP_CTRL("eldo1", 700, 3300, 100, 264 0x12, __BIT(0), 0x19, __BITS(4,0)), 265 AXP_CTRL("eldo2", 700, 3300, 100, 266 0x12, __BIT(1), 0x1a, __BITS(4,0)), 267 AXP_CTRL("eldo3", 700, 3300, 100, 268 0x12, __BIT(2), 0x1b, __BITS(4,0)), 269 AXP_CTRL2_RANGE("dldo1", 700, 4000, 100, 26, 3400, 200, 4, 270 0x12, __BIT(3), 0x15, __BITS(4,0)), 271 AXP_CTRL("dldo2", 700, 3300, 100, 272 0x12, __BIT(4), 0x16, __BITS(4,0)), 273 AXP_CTRL("aldo3", 700, 3300, 100, 274 0x12, __BIT(5), 0x2a, __BITS(4,0)), 275 AXP_CTRL_SW("sw", 276 0x12, __BIT(6)), 277 /* dc1sw is another switch for dcdc1 */ 278 AXP_CTRL("dc1sw", 1600, 3400, 100, 279 0x12, __BIT(7), 0x21, __BITS(4,0)), 280 AXP_CTRL_IO("ldo_io0", 700, 3300, 100, 281 0x90, __BITS(3,0), 0x3, 0x7, 0x91, __BITS(4,0)), 282 AXP_CTRL_IO("ldo_io1", 700, 3300, 100, 283 0x92, __BITS(3,0), 0x3, 0x7, 0x93, __BITS(4,0)), 284 }; 285 286 static const struct axppmic_ctrl axp813_ctrls[] = { 287 AXP_CTRL("dldo1", 700, 3300, 100, 288 0x12, __BIT(3), 0x15, __BITS(4,0)), 289 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 290 0x12, __BIT(4), 0x16, __BITS(4,0)), 291 AXP_CTRL("dldo3", 700, 3300, 100, 292 0x12, __BIT(5), 0x17, __BITS(4,0)), 293 AXP_CTRL("dldo4", 700, 3300, 100, 294 0x12, __BIT(6), 0x18, __BITS(4,0)), 295 AXP_CTRL("eldo1", 700, 1900, 50, 296 0x12, __BIT(0), 0x19, __BITS(4,0)), 297 AXP_CTRL("eldo2", 700, 1900, 50, 298 0x12, __BIT(1), 0x1a, __BITS(4,0)), 299 AXP_CTRL("eldo3", 700, 1900, 50, 300 0x12, __BIT(2), 0x1b, __BITS(4,0)), 301 AXP_CTRL("fldo1", 700, 1450, 50, 302 0x13, __BIT(2), 0x1c, __BITS(3,0)), 303 AXP_CTRL("fldo2", 700, 1450, 50, 304 0x13, __BIT(3), 0x1d, __BITS(3,0)), 305 AXP_CTRL("dcdc1", 1600, 3400, 100, 306 0x10, __BIT(0), 0x20, __BITS(4,0)), 307 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 308 0x10, __BIT(1), 0x21, __BITS(6,0)), 309 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 310 0x10, __BIT(2), 0x22, __BITS(6,0)), 311 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 312 0x10, __BIT(3), 0x23, __BITS(6,0)), 313 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 314 0x10, __BIT(4), 0x24, __BITS(6,0)), 315 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 316 0x10, __BIT(5), 0x25, __BITS(6,0)), 317 AXP_CTRL2("dcdc7", 600, 1520, 10, 51, 20, 21, 318 0x10, __BIT(6), 0x26, __BITS(6,0)), 319 AXP_CTRL("aldo1", 700, 3300, 100, 320 0x13, __BIT(5), 0x28, __BITS(4,0)), 321 AXP_CTRL("aldo2", 700, 3300, 100, 322 0x13, __BIT(6), 0x29, __BITS(4,0)), 323 AXP_CTRL("aldo3", 700, 3300, 100, 324 0x13, __BIT(7), 0x2a, __BITS(4,0)), 325 }; 326 327 struct axppmic_irq { 328 u_int reg; 329 uint8_t mask; 330 }; 331 332 #define AXPPMIC_IRQ(_reg, _mask) \ 333 { .reg = (_reg), .mask = (_mask) } 334 335 struct axppmic_config { 336 const char *name; 337 const char *gpio_compat; 338 u_int gpio_npins; 339 const struct axppmic_ctrl *controls; 340 u_int ncontrols; 341 u_int irq_regs; 342 bool has_battery; 343 bool has_fuel_gauge; 344 bool has_mode_set; 345 struct axppmic_irq poklirq; 346 struct axppmic_irq acinirq; 347 struct axppmic_irq vbusirq; 348 struct axppmic_irq battirq; 349 struct axppmic_irq chargeirq; 350 struct axppmic_irq chargestirq; 351 u_int batsense_step; /* uV */ 352 u_int charge_step; /* uA */ 353 u_int discharge_step; /* uA */ 354 u_int maxcap_step; /* uAh */ 355 u_int coulomb_step; /* uAh */ 356 }; 357 358 enum axppmic_sensor { 359 AXP_SENSOR_ACIN_PRESENT, 360 AXP_SENSOR_VBUS_PRESENT, 361 AXP_SENSOR_BATT_PRESENT, 362 AXP_SENSOR_BATT_CHARGING, 363 AXP_SENSOR_BATT_CHARGE_STATE, 364 AXP_SENSOR_BATT_VOLTAGE, 365 AXP_SENSOR_BATT_CHARGE_CURRENT, 366 AXP_SENSOR_BATT_DISCHARGE_CURRENT, 367 AXP_SENSOR_BATT_CAPACITY_PERCENT, 368 AXP_SENSOR_BATT_MAXIMUM_CAPACITY, 369 AXP_SENSOR_BATT_CURRENT_CAPACITY, 370 AXP_NSENSORS 371 }; 372 373 struct axppmic_softc { 374 device_t sc_dev; 375 i2c_tag_t sc_i2c; 376 i2c_addr_t sc_addr; 377 int sc_phandle; 378 379 void *sc_ih; 380 struct workqueue *sc_wq; 381 382 kmutex_t sc_intr_lock; 383 struct work sc_work; 384 bool sc_work_scheduled; 385 386 const struct axppmic_config *sc_conf; 387 388 struct sysmon_pswitch sc_smpsw; 389 390 struct sysmon_envsys *sc_sme; 391 392 envsys_data_t sc_sensor[AXP_NSENSORS]; 393 394 u_int sc_warn_thres; 395 u_int sc_shut_thres; 396 }; 397 398 struct axppmic_gpio_pin { 399 struct axppmic_softc *pin_sc; 400 u_int pin_nr; 401 int pin_flags; 402 bool pin_actlo; 403 }; 404 405 struct axpreg_softc { 406 device_t sc_dev; 407 i2c_tag_t sc_i2c; 408 i2c_addr_t sc_addr; 409 const struct axppmic_ctrl *sc_ctrl; 410 }; 411 412 struct axpreg_attach_args { 413 const struct axppmic_ctrl *reg_ctrl; 414 int reg_phandle; 415 i2c_tag_t reg_i2c; 416 i2c_addr_t reg_addr; 417 }; 418 419 static const struct axppmic_config axp803_config = { 420 .name = "AXP803", 421 .gpio_compat = "x-powers,axp803-gpio", 422 .gpio_npins = 2, 423 .controls = axp803_ctrls, 424 .ncontrols = __arraycount(axp803_ctrls), 425 .irq_regs = 6, 426 .has_battery = true, 427 .has_fuel_gauge = true, 428 .batsense_step = 1100, 429 .charge_step = 1000, 430 .discharge_step = 1000, 431 .maxcap_step = 1456, 432 .coulomb_step = 1456, 433 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 434 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 435 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 436 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 437 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 438 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 439 }; 440 441 static const struct axppmic_config axp805_config = { 442 .name = "AXP805", 443 .controls = axp805_ctrls, 444 .ncontrols = __arraycount(axp805_ctrls), 445 .irq_regs = 2, 446 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 447 }; 448 449 static const struct axppmic_config axp806_config = { 450 .name = "AXP806", 451 .controls = axp805_ctrls, 452 .ncontrols = __arraycount(axp805_ctrls), 453 #if notyet 454 .irq_regs = 2, 455 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 456 #endif 457 .has_mode_set = true, 458 }; 459 460 static const struct axppmic_config axp809_config = { 461 .name = "AXP809", 462 .controls = axp809_ctrls, 463 .ncontrols = __arraycount(axp809_ctrls), 464 }; 465 466 static const struct axppmic_config axp813_config = { 467 .name = "AXP813", 468 .gpio_compat = "x-powers,axp813-gpio", 469 .gpio_npins = 2, 470 .controls = axp813_ctrls, 471 .ncontrols = __arraycount(axp813_ctrls), 472 .irq_regs = 6, 473 .has_battery = true, 474 .has_fuel_gauge = true, 475 .batsense_step = 1100, 476 .charge_step = 1000, 477 .discharge_step = 1000, 478 .maxcap_step = 1456, 479 .coulomb_step = 1456, 480 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 481 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 482 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 483 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 484 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 485 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 486 }; 487 488 static const struct device_compatible_entry compat_data[] = { 489 { .compat = "x-powers,axp803", .data = &axp803_config }, 490 { .compat = "x-powers,axp805", .data = &axp805_config }, 491 { .compat = "x-powers,axp806", .data = &axp806_config }, 492 { .compat = "x-powers,axp809", .data = &axp809_config }, 493 { .compat = "x-powers,axp813", .data = &axp813_config }, 494 DEVICE_COMPAT_EOL 495 }; 496 497 static int 498 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 499 { 500 return iic_smbus_read_byte(tag, addr, reg, val, flags); 501 } 502 503 static int 504 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 505 { 506 return iic_smbus_write_byte(tag, addr, reg, val, flags); 507 } 508 509 static int 510 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 511 { 512 u_int vol, reg_val; 513 int nstep, error; 514 uint8_t val; 515 516 if (!c->c_voltage_mask) 517 return EINVAL; 518 519 if (min < c->c_min || min > c->c_max) 520 return EINVAL; 521 522 reg_val = 0; 523 nstep = 1; 524 vol = c->c_min; 525 526 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 527 ++reg_val; 528 vol += c->c_step1; 529 } 530 531 if (c->c_step2start) 532 vol = c->c_step2start; 533 534 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 535 ++reg_val; 536 vol += c->c_step2; 537 } 538 539 if (vol > max) 540 return EINVAL; 541 542 iic_acquire_bus(tag, 0); 543 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0)) == 0) { 544 val &= ~c->c_voltage_mask; 545 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 546 error = axppmic_write(tag, addr, c->c_voltage_reg, val, 0); 547 } 548 iic_release_bus(tag, 0); 549 550 return error; 551 } 552 553 static int 554 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 555 { 556 int reg_val, error; 557 uint8_t val; 558 559 if (!c->c_voltage_mask) 560 return EINVAL; 561 562 iic_acquire_bus(tag, 0); 563 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0); 564 iic_release_bus(tag, 0); 565 if (error) 566 return error; 567 568 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 569 if (reg_val < c->c_step1cnt) { 570 *pvol = c->c_min + reg_val * c->c_step1; 571 } else if (c->c_step2start) { 572 *pvol = c->c_step2start + 573 ((reg_val - c->c_step1cnt) * c->c_step2); 574 } else { 575 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 576 ((reg_val - c->c_step1cnt) * c->c_step2); 577 } 578 579 return 0; 580 } 581 582 static void 583 axppmic_power_poweroff(device_t dev) 584 { 585 struct axppmic_softc *sc = device_private(dev); 586 int error; 587 588 delay(1000000); 589 590 error = iic_acquire_bus(sc->sc_i2c, 0); 591 if (error == 0) { 592 error = axppmic_write(sc->sc_i2c, sc->sc_addr, 593 AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, 0); 594 iic_release_bus(sc->sc_i2c, 0); 595 } 596 if (error) { 597 device_printf(dev, "WARNING: unable to power off, error %d\n", 598 error); 599 } 600 } 601 602 static struct fdtbus_power_controller_func axppmic_power_funcs = { 603 .poweroff = axppmic_power_poweroff, 604 }; 605 606 static int 607 axppmic_gpio_ctl(struct axppmic_softc *sc, uint8_t pin, uint8_t func) 608 { 609 uint8_t val; 610 int error; 611 612 KASSERT(pin < sc->sc_conf->gpio_npins); 613 KASSERT((func & ~AXP_GPIO_CTRL_FUNC_MASK) == 0); 614 615 iic_acquire_bus(sc->sc_i2c, 0); 616 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_GPIO_CTRL_REG(pin), 617 &val, 0); 618 if (error == 0) { 619 val &= ~AXP_GPIO_CTRL_FUNC_MASK; 620 val |= func; 621 error = axppmic_write(sc->sc_i2c, sc->sc_addr, 622 AXP_GPIO_CTRL_REG(pin), val, 0); 623 } 624 iic_release_bus(sc->sc_i2c, 0); 625 626 return error; 627 } 628 629 static void * 630 axppmic_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 631 { 632 struct axppmic_softc *sc = device_private(dev); 633 struct axppmic_gpio_pin *gpin; 634 const u_int *gpio = data; 635 int error; 636 637 if (len != 12) { 638 return NULL; 639 } 640 641 const uint8_t pin = be32toh(gpio[1]) & 0xff; 642 const bool actlo = be32toh(gpio[2]) & 1; 643 644 if (pin >= sc->sc_conf->gpio_npins) { 645 return NULL; 646 } 647 648 if ((flags & GPIO_PIN_INPUT) != 0) { 649 error = axppmic_gpio_ctl(sc, pin, AXP_GPIO_CTRL_FUNC_INPUT); 650 if (error != 0) { 651 return NULL; 652 } 653 } 654 655 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 656 gpin->pin_sc = sc; 657 gpin->pin_nr = pin; 658 gpin->pin_flags = flags; 659 gpin->pin_actlo = actlo; 660 661 return gpin; 662 } 663 664 static void 665 axppmic_gpio_release(device_t dev, void *priv) 666 { 667 struct axppmic_softc *sc = device_private(dev); 668 struct axppmic_gpio_pin *gpin = priv; 669 670 axppmic_gpio_ctl(sc, gpin->pin_nr, AXP_GPIO_CTRL_FUNC_INPUT); 671 672 kmem_free(gpin, sizeof(*gpin)); 673 } 674 675 static int 676 axppmic_gpio_read(device_t dev, void *priv, bool raw) 677 { 678 struct axppmic_softc *sc = device_private(dev); 679 struct axppmic_gpio_pin *gpin = priv; 680 uint8_t data; 681 int error, val; 682 683 KASSERT(sc == gpin->pin_sc); 684 685 const uint8_t data_mask = __BIT(gpin->pin_nr); 686 687 iic_acquire_bus(sc->sc_i2c, 0); 688 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_GPIO_SIGNAL_REG, 689 &data, 0); 690 iic_release_bus(sc->sc_i2c, 0); 691 692 if (error != 0) { 693 device_printf(dev, "WARNING: failed to read pin %d: %d\n", 694 gpin->pin_nr, error); 695 val = 0; 696 } else { 697 val = __SHIFTOUT(data, data_mask); 698 } 699 if (!raw && gpin->pin_actlo) { 700 val = !val; 701 } 702 703 return val; 704 } 705 706 static void 707 axppmic_gpio_write(device_t dev, void *priv, int val, bool raw) 708 { 709 struct axppmic_softc *sc = device_private(dev); 710 struct axppmic_gpio_pin *gpin = priv; 711 int error; 712 713 if (!raw && gpin->pin_actlo) { 714 val = !val; 715 } 716 717 error = axppmic_gpio_ctl(sc, gpin->pin_nr, 718 val == 0 ? AXP_GPIO_CTRL_FUNC_LOW : AXP_GPIO_CTRL_FUNC_HIGH); 719 if (error != 0) { 720 device_printf(dev, "WARNING: failed to write pin %d: %d\n", 721 gpin->pin_nr, error); 722 } 723 } 724 725 static struct fdtbus_gpio_controller_func axppmic_gpio_funcs = { 726 .acquire = axppmic_gpio_acquire, 727 .release = axppmic_gpio_release, 728 .read = axppmic_gpio_read, 729 .write = axppmic_gpio_write, 730 }; 731 732 static void 733 axppmic_task_shut(void *priv) 734 { 735 struct axppmic_softc *sc = priv; 736 737 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 738 } 739 740 static void 741 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 742 { 743 struct axppmic_softc *sc = sme->sme_cookie; 744 const struct axppmic_config *c = sc->sc_conf; 745 uint8_t val, lo, hi; 746 747 e->state = ENVSYS_SINVALID; 748 749 const bool battery_present = 750 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID && 751 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1; 752 753 switch (e->private) { 754 case AXP_SENSOR_ACIN_PRESENT: 755 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 756 e->state = ENVSYS_SVALID; 757 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 758 } 759 break; 760 case AXP_SENSOR_VBUS_PRESENT: 761 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 762 e->state = ENVSYS_SVALID; 763 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 764 } 765 break; 766 case AXP_SENSOR_BATT_PRESENT: 767 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 768 if (val & AXP_POWER_MODE_BATT_VALID) { 769 e->state = ENVSYS_SVALID; 770 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 771 } 772 } 773 break; 774 case AXP_SENSOR_BATT_CHARGING: 775 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 776 e->state = ENVSYS_SVALID; 777 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 778 } 779 break; 780 case AXP_SENSOR_BATT_CHARGE_STATE: 781 if (battery_present && 782 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 783 (val & AXP_BATT_CAP_VALID) != 0) { 784 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 785 if (batt_val <= sc->sc_shut_thres) { 786 e->state = ENVSYS_SCRITICAL; 787 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 788 } else if (batt_val <= sc->sc_warn_thres) { 789 e->state = ENVSYS_SWARNUNDER; 790 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 791 } else { 792 e->state = ENVSYS_SVALID; 793 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 794 } 795 } 796 break; 797 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 798 if (battery_present && 799 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 800 (val & AXP_BATT_CAP_VALID) != 0) { 801 e->state = ENVSYS_SVALID; 802 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 803 } 804 break; 805 case AXP_SENSOR_BATT_VOLTAGE: 806 if (battery_present && 807 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, 0) == 0 && 808 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, 0) == 0) { 809 e->state = ENVSYS_SVALID; 810 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step; 811 } 812 break; 813 case AXP_SENSOR_BATT_CHARGE_CURRENT: 814 if (battery_present && 815 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 816 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 && 817 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, 0) == 0 && 818 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, 0) == 0) { 819 e->state = ENVSYS_SVALID; 820 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step; 821 } 822 break; 823 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 824 if (battery_present && 825 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 826 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 && 827 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, 0) == 0 && 828 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, 0) == 0) { 829 e->state = ENVSYS_SVALID; 830 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step; 831 } 832 break; 833 case AXP_SENSOR_BATT_MAXIMUM_CAPACITY: 834 if (battery_present && 835 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_HI_REG, &hi, 0) == 0 && 836 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_LO_REG, &lo, 0) == 0) { 837 e->state = (hi & AXP_BATT_MAX_CAP_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 838 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->maxcap_step; 839 } 840 break; 841 case AXP_SENSOR_BATT_CURRENT_CAPACITY: 842 if (battery_present && 843 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_HI_REG, &hi, 0) == 0 && 844 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_LO_REG, &lo, 0) == 0) { 845 e->state = (hi & AXP_BATT_COULOMB_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 846 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->coulomb_step; 847 } 848 break; 849 } 850 } 851 852 static void 853 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 854 { 855 struct axppmic_softc *sc = sme->sme_cookie; 856 857 switch (e->private) { 858 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 859 case AXP_SENSOR_BATT_VOLTAGE: 860 case AXP_SENSOR_BATT_CHARGE_CURRENT: 861 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 862 /* Always update battery capacity and ADCs */ 863 iic_acquire_bus(sc->sc_i2c, 0); 864 axppmic_sensor_update(sme, e); 865 iic_release_bus(sc->sc_i2c, 0); 866 break; 867 default: 868 /* Refresh if the sensor is not in valid state */ 869 if (e->state != ENVSYS_SVALID) { 870 iic_acquire_bus(sc->sc_i2c, 0); 871 axppmic_sensor_update(sme, e); 872 iic_release_bus(sc->sc_i2c, 0); 873 } 874 break; 875 } 876 } 877 878 static int 879 axppmic_intr(void *priv) 880 { 881 struct axppmic_softc * const sc = priv; 882 883 mutex_enter(&sc->sc_intr_lock); 884 885 fdtbus_intr_mask(sc->sc_phandle, sc->sc_ih); 886 887 /* Interrupt is always masked when work is scheduled! */ 888 KASSERT(!sc->sc_work_scheduled); 889 sc->sc_work_scheduled = true; 890 workqueue_enqueue(sc->sc_wq, &sc->sc_work, NULL); 891 892 mutex_exit(&sc->sc_intr_lock); 893 894 return 1; 895 } 896 897 static void 898 axppmic_work(struct work *work, void *arg) 899 { 900 struct axppmic_softc * const sc = 901 container_of(work, struct axppmic_softc, sc_work); 902 const struct axppmic_config * const c = sc->sc_conf; 903 const int flags = 0; 904 uint8_t stat; 905 u_int n; 906 907 KASSERT(sc->sc_work_scheduled); 908 909 iic_acquire_bus(sc->sc_i2c, flags); 910 for (n = 1; n <= c->irq_regs; n++) { 911 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 912 if (stat != 0) { 913 axppmic_write(sc->sc_i2c, sc->sc_addr, 914 AXP_IRQ_STATUS_REG(n), stat, flags); 915 } 916 917 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 918 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 919 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 920 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 921 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 922 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 923 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 924 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 925 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 926 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 927 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 928 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 929 } 930 } 931 iic_release_bus(sc->sc_i2c, flags); 932 933 mutex_enter(&sc->sc_intr_lock); 934 sc->sc_work_scheduled = false; 935 fdtbus_intr_unmask(sc->sc_phandle, sc->sc_ih); 936 mutex_exit(&sc->sc_intr_lock); 937 } 938 939 static void 940 axppmic_attach_acadapter(struct axppmic_softc *sc) 941 { 942 envsys_data_t *e; 943 944 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 945 e->private = AXP_SENSOR_ACIN_PRESENT; 946 e->units = ENVSYS_INDICATOR; 947 e->state = ENVSYS_SINVALID; 948 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 949 sysmon_envsys_sensor_attach(sc->sc_sme, e); 950 951 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 952 e->private = AXP_SENSOR_VBUS_PRESENT; 953 e->units = ENVSYS_INDICATOR; 954 e->state = ENVSYS_SINVALID; 955 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 956 sysmon_envsys_sensor_attach(sc->sc_sme, e); 957 } 958 959 static void 960 axppmic_attach_battery(struct axppmic_softc *sc) 961 { 962 const struct axppmic_config *c = sc->sc_conf; 963 envsys_data_t *e; 964 uint8_t val; 965 966 iic_acquire_bus(sc->sc_i2c, 0); 967 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, 0) == 0) { 968 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 969 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 970 } 971 iic_release_bus(sc->sc_i2c, 0); 972 973 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 974 e->private = AXP_SENSOR_BATT_PRESENT; 975 e->units = ENVSYS_INDICATOR; 976 e->state = ENVSYS_SINVALID; 977 strlcpy(e->desc, "battery present", sizeof(e->desc)); 978 sysmon_envsys_sensor_attach(sc->sc_sme, e); 979 980 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 981 e->private = AXP_SENSOR_BATT_CHARGING; 982 e->units = ENVSYS_BATTERY_CHARGE; 983 e->state = ENVSYS_SINVALID; 984 strlcpy(e->desc, "charging", sizeof(e->desc)); 985 sysmon_envsys_sensor_attach(sc->sc_sme, e); 986 987 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 988 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 989 e->units = ENVSYS_BATTERY_CAPACITY; 990 e->flags = ENVSYS_FMONSTCHANGED; 991 e->state = ENVSYS_SINVALID; 992 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 993 strlcpy(e->desc, "charge state", sizeof(e->desc)); 994 sysmon_envsys_sensor_attach(sc->sc_sme, e); 995 996 if (c->batsense_step) { 997 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE]; 998 e->private = AXP_SENSOR_BATT_VOLTAGE; 999 e->units = ENVSYS_SVOLTS_DC; 1000 e->state = ENVSYS_SINVALID; 1001 strlcpy(e->desc, "battery voltage", sizeof(e->desc)); 1002 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1003 } 1004 1005 if (c->charge_step) { 1006 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT]; 1007 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT; 1008 e->units = ENVSYS_SAMPS; 1009 e->state = ENVSYS_SINVALID; 1010 strlcpy(e->desc, "battery charge current", sizeof(e->desc)); 1011 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1012 } 1013 1014 if (c->discharge_step) { 1015 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT]; 1016 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT; 1017 e->units = ENVSYS_SAMPS; 1018 e->state = ENVSYS_SINVALID; 1019 strlcpy(e->desc, "battery discharge current", sizeof(e->desc)); 1020 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1021 } 1022 1023 if (c->has_fuel_gauge) { 1024 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT]; 1025 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT; 1026 e->units = ENVSYS_INTEGER; 1027 e->state = ENVSYS_SINVALID; 1028 e->flags = ENVSYS_FPERCENT; 1029 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 1030 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1031 } 1032 1033 if (c->maxcap_step) { 1034 e = &sc->sc_sensor[AXP_SENSOR_BATT_MAXIMUM_CAPACITY]; 1035 e->private = AXP_SENSOR_BATT_MAXIMUM_CAPACITY; 1036 e->units = ENVSYS_SAMPHOUR; 1037 e->state = ENVSYS_SINVALID; 1038 strlcpy(e->desc, "battery maximum capacity", sizeof(e->desc)); 1039 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1040 } 1041 1042 if (c->coulomb_step) { 1043 e = &sc->sc_sensor[AXP_SENSOR_BATT_CURRENT_CAPACITY]; 1044 e->private = AXP_SENSOR_BATT_CURRENT_CAPACITY; 1045 e->units = ENVSYS_SAMPHOUR; 1046 e->state = ENVSYS_SINVALID; 1047 strlcpy(e->desc, "battery current capacity", sizeof(e->desc)); 1048 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1049 } 1050 } 1051 1052 static void 1053 axppmic_attach_sensors(struct axppmic_softc *sc) 1054 { 1055 if (sc->sc_conf->has_battery) { 1056 sc->sc_sme = sysmon_envsys_create(); 1057 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 1058 sc->sc_sme->sme_cookie = sc; 1059 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 1060 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 1061 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 1062 1063 axppmic_attach_acadapter(sc); 1064 axppmic_attach_battery(sc); 1065 1066 sysmon_envsys_register(sc->sc_sme); 1067 } 1068 } 1069 1070 1071 static int 1072 axppmic_match(device_t parent, cfdata_t match, void *aux) 1073 { 1074 struct i2c_attach_args *ia = aux; 1075 int match_result; 1076 1077 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 1078 return match_result; 1079 1080 /* This device is direct-config only. */ 1081 1082 return 0; 1083 } 1084 1085 static void 1086 axppmic_attach(device_t parent, device_t self, void *aux) 1087 { 1088 struct axppmic_softc *sc = device_private(self); 1089 const struct device_compatible_entry *dce = NULL; 1090 const struct axppmic_config *c; 1091 struct axpreg_attach_args aaa; 1092 struct i2c_attach_args *ia = aux; 1093 int phandle, child, i; 1094 uint8_t irq_mask, val; 1095 int error; 1096 1097 dce = iic_compatible_lookup(ia, compat_data); 1098 KASSERT(dce != NULL); 1099 c = dce->data; 1100 1101 sc->sc_dev = self; 1102 sc->sc_i2c = ia->ia_tag; 1103 sc->sc_addr = ia->ia_addr; 1104 sc->sc_phandle = ia->ia_cookie; 1105 sc->sc_conf = c; 1106 1107 aprint_naive("\n"); 1108 aprint_normal(": %s\n", c->name); 1109 1110 if (c->has_mode_set) { 1111 const bool master_mode = of_hasprop(sc->sc_phandle, "x-powers,self-working-mode") || 1112 of_hasprop(sc->sc_phandle, "x-powers,master-mode"); 1113 1114 iic_acquire_bus(sc->sc_i2c, 0); 1115 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_ADDR_EXT_REG, 1116 master_mode ? AXP_ADDR_EXT_MASTER : AXP_ADDR_EXT_SLAVE, 0); 1117 iic_release_bus(sc->sc_i2c, 0); 1118 } 1119 1120 iic_acquire_bus(sc->sc_i2c, 0); 1121 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_CHIP_ID_REG, &val, 0); 1122 iic_release_bus(sc->sc_i2c, 0); 1123 if (error != 0) { 1124 aprint_error_dev(self, "couldn't read chipid\n"); 1125 return; 1126 } 1127 aprint_debug_dev(self, "chipid %#x\n", val); 1128 1129 sc->sc_smpsw.smpsw_name = device_xname(self); 1130 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 1131 sysmon_pswitch_register(&sc->sc_smpsw); 1132 1133 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 1134 1135 if (c->irq_regs > 0) { 1136 char intrstr[128]; 1137 1138 if (!fdtbus_intr_str(sc->sc_phandle, 0, 1139 intrstr, sizeof(intrstr))) { 1140 aprint_error_dev(self, 1141 "WARNING: failed to decode interrupt\n"); 1142 } 1143 1144 sc->sc_ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, 1145 FDT_INTR_MPSAFE, 1146 axppmic_intr, sc); 1147 if (sc->sc_ih == NULL) { 1148 aprint_error_dev(self, 1149 "WARNING: couldn't establish interrupt handler\n"); 1150 } 1151 1152 error = workqueue_create(&sc->sc_wq, device_xname(self), 1153 axppmic_work, NULL, 1154 PRI_SOFTSERIAL, IPL_VM, 1155 WQ_MPSAFE); 1156 if (error) { 1157 sc->sc_wq = NULL; 1158 aprint_error_dev(self, 1159 "WARNING: couldn't create work queue: error %d\n", 1160 error); 1161 } 1162 1163 if (sc->sc_ih != NULL && sc->sc_wq != NULL) { 1164 iic_acquire_bus(sc->sc_i2c, 0); 1165 for (i = 1; i <= c->irq_regs; i++) { 1166 irq_mask = 0; 1167 if (i == c->poklirq.reg) 1168 irq_mask |= c->poklirq.mask; 1169 if (i == c->acinirq.reg) 1170 irq_mask |= c->acinirq.mask; 1171 if (i == c->vbusirq.reg) 1172 irq_mask |= c->vbusirq.mask; 1173 if (i == c->battirq.reg) 1174 irq_mask |= c->battirq.mask; 1175 if (i == c->chargeirq.reg) 1176 irq_mask |= c->chargeirq.mask; 1177 if (i == c->chargestirq.reg) 1178 irq_mask |= c->chargestirq.mask; 1179 axppmic_write(sc->sc_i2c, sc->sc_addr, 1180 AXP_IRQ_ENABLE_REG(i), 1181 irq_mask, 0); 1182 } 1183 iic_release_bus(sc->sc_i2c, 0); 1184 } 1185 } 1186 1187 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 1188 &axppmic_power_funcs); 1189 1190 if (c->gpio_compat != NULL) { 1191 phandle = of_find_bycompat(sc->sc_phandle, c->gpio_compat); 1192 if (phandle > 0) { 1193 fdtbus_register_gpio_controller(self, phandle, 1194 &axppmic_gpio_funcs); 1195 } 1196 } 1197 1198 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 1199 if (phandle > 0) { 1200 aaa.reg_i2c = sc->sc_i2c; 1201 aaa.reg_addr = sc->sc_addr; 1202 for (i = 0; i < c->ncontrols; i++) { 1203 const struct axppmic_ctrl *ctrl = &c->controls[i]; 1204 child = of_find_firstchild_byname(phandle, ctrl->c_name); 1205 if (child <= 0) 1206 continue; 1207 aaa.reg_ctrl = ctrl; 1208 aaa.reg_phandle = child; 1209 config_found(sc->sc_dev, &aaa, NULL, CFARGS_NONE); 1210 } 1211 } 1212 1213 if (c->has_battery) 1214 axppmic_attach_sensors(sc); 1215 } 1216 1217 static int 1218 axpreg_acquire(device_t dev) 1219 { 1220 return 0; 1221 } 1222 1223 static void 1224 axpreg_release(device_t dev) 1225 { 1226 } 1227 1228 static int 1229 axpreg_enable(device_t dev, bool enable) 1230 { 1231 struct axpreg_softc *sc = device_private(dev); 1232 const struct axppmic_ctrl *c = sc->sc_ctrl; 1233 const int flags = 0; 1234 uint8_t val; 1235 int error; 1236 1237 if (!c->c_enable_mask) 1238 return EINVAL; 1239 1240 iic_acquire_bus(sc->sc_i2c, flags); 1241 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 1242 val &= ~c->c_enable_mask; 1243 if (enable) 1244 val |= c->c_enable_val; 1245 else 1246 val |= c->c_disable_val; 1247 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 1248 } 1249 iic_release_bus(sc->sc_i2c, flags); 1250 1251 return error; 1252 } 1253 1254 static int 1255 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 1256 { 1257 struct axpreg_softc *sc = device_private(dev); 1258 const struct axppmic_ctrl *c = sc->sc_ctrl; 1259 1260 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 1261 min_uvol / 1000, max_uvol / 1000); 1262 } 1263 1264 static int 1265 axpreg_get_voltage(device_t dev, u_int *puvol) 1266 { 1267 struct axpreg_softc *sc = device_private(dev); 1268 const struct axppmic_ctrl *c = sc->sc_ctrl; 1269 int error; 1270 u_int vol; 1271 1272 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 1273 if (error) 1274 return error; 1275 1276 *puvol = vol * 1000; 1277 return 0; 1278 } 1279 1280 static struct fdtbus_regulator_controller_func axpreg_funcs = { 1281 .acquire = axpreg_acquire, 1282 .release = axpreg_release, 1283 .enable = axpreg_enable, 1284 .set_voltage = axpreg_set_voltage, 1285 .get_voltage = axpreg_get_voltage, 1286 }; 1287 1288 static int 1289 axpreg_match(device_t parent, cfdata_t match, void *aux) 1290 { 1291 return 1; 1292 } 1293 1294 static void 1295 axpreg_attach(device_t parent, device_t self, void *aux) 1296 { 1297 struct axpreg_softc *sc = device_private(self); 1298 struct axpreg_attach_args *aaa = aux; 1299 const int phandle = aaa->reg_phandle; 1300 const char *name; 1301 u_int uvol, min_uvol, max_uvol; 1302 1303 sc->sc_dev = self; 1304 sc->sc_i2c = aaa->reg_i2c; 1305 sc->sc_addr = aaa->reg_addr; 1306 sc->sc_ctrl = aaa->reg_ctrl; 1307 1308 fdtbus_register_regulator_controller(self, phandle, 1309 &axpreg_funcs); 1310 1311 aprint_naive("\n"); 1312 name = fdtbus_get_string(phandle, "regulator-name"); 1313 if (name) 1314 aprint_normal(": %s\n", name); 1315 else 1316 aprint_normal("\n"); 1317 1318 int error = axpreg_get_voltage(self, &uvol); 1319 if (error) 1320 return; 1321 1322 if (of_getprop_uint32(phandle, "regulator-min-microvolt", &min_uvol) == 0 && 1323 of_getprop_uint32(phandle, "regulator-max-microvolt", &max_uvol) == 0) { 1324 if (uvol < min_uvol || uvol > max_uvol) { 1325 aprint_debug_dev(self, "fix voltage %u uV -> %u/%u uV\n", 1326 uvol, min_uvol, max_uvol); 1327 axpreg_set_voltage(self, min_uvol, max_uvol); 1328 } 1329 } 1330 1331 if (of_hasprop(phandle, "regulator-always-on") || 1332 of_hasprop(phandle, "regulator-boot-on")) { 1333 axpreg_enable(self, true); 1334 } 1335 } 1336 1337 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 1338 axppmic_match, axppmic_attach, NULL, NULL); 1339 1340 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 1341 axpreg_match, axpreg_attach, NULL, NULL); 1342