1 /* $NetBSD: axppmic.c,v 1.29 2020/02/16 20:32:29 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.29 2020/02/16 20:32:29 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 #include <sys/workqueue.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 #include <dev/sysmon/sysmon_taskq.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define AXP_POWER_SOURCE_REG 0x00 49 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 50 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 51 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2) 52 53 #define AXP_POWER_MODE_REG 0x01 54 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 55 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 56 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 57 58 #define AXP_CHIP_ID_REG 0x03 59 60 #define AXP_POWER_DISABLE_REG 0x32 61 #define AXP_POWER_DISABLE_CTRL __BIT(7) 62 63 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 64 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 65 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 66 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 67 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 68 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 69 70 #define AXP_BATSENSE_HI_REG 0x78 71 #define AXP_BATSENSE_LO_REG 0x79 72 73 #define AXP_BATTCHG_HI_REG 0x7a 74 #define AXP_BATTCHG_LO_REG 0x7b 75 76 #define AXP_BATTDISCHG_HI_REG 0x7c 77 #define AXP_BATTDISCHG_LO_REG 0x7d 78 79 #define AXP_ADC_RAW(_hi, _lo) \ 80 (((u_int)(_hi) << 4) | ((_lo) & 0xf)) 81 82 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 83 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 84 85 #define AXP_BATT_CAP_REG 0xb9 86 #define AXP_BATT_CAP_VALID __BIT(7) 87 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 88 89 #define AXP_BATT_MAX_CAP_HI_REG 0xe0 90 #define AXP_BATT_MAX_CAP_VALID __BIT(7) 91 #define AXP_BATT_MAX_CAP_LO_REG 0xe1 92 93 #define AXP_BATT_COULOMB_HI_REG 0xe2 94 #define AXP_BATT_COULOMB_VALID __BIT(7) 95 #define AXP_BATT_COULOMB_LO_REG 0xe3 96 97 #define AXP_COULOMB_RAW(_hi, _lo) \ 98 (((u_int)(_hi & ~__BIT(7)) << 8) | (_lo)) 99 100 #define AXP_BATT_CAP_WARN_REG 0xe6 101 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 102 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 103 104 #define AXP_ADDR_EXT_REG 0xff /* AXP806 */ 105 #define AXP_ADDR_EXT_MASTER 0 106 #define AXP_ADDR_EXT_SLAVE __BIT(4) 107 108 struct axppmic_ctrl { 109 device_t c_dev; 110 111 const char * c_name; 112 u_int c_min; 113 u_int c_max; 114 u_int c_step1; 115 u_int c_step1cnt; 116 u_int c_step2; 117 u_int c_step2cnt; 118 u_int c_step2start; 119 120 uint8_t c_enable_reg; 121 uint8_t c_enable_mask; 122 uint8_t c_enable_val; 123 uint8_t c_disable_val; 124 125 uint8_t c_voltage_reg; 126 uint8_t c_voltage_mask; 127 }; 128 129 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 130 { .c_name = (name), .c_min = (min), .c_max = (max), \ 131 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 132 .c_step2 = 0, .c_step2cnt = 0, \ 133 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 134 .c_enable_val = (emask), .c_disable_val = 0, \ 135 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 136 137 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 138 { .c_name = (name), .c_min = (min), .c_max = (max), \ 139 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 140 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 141 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 142 .c_enable_val = (emask), .c_disable_val = 0, \ 143 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 144 145 #define AXP_CTRL2_RANGE(name, min, max, step1, step1cnt, step2start, step2, step2cnt, ereg, emask, vreg, vmask) \ 146 { .c_name = (name), .c_min = (min), .c_max = (max), \ 147 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 148 .c_step2start = (step2start), \ 149 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 150 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 151 .c_enable_val = (emask), .c_disable_val = 0, \ 152 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 153 154 #define AXP_CTRL_IO(name, min, max, step, ereg, emask, eval, dval, vreg, vmask) \ 155 { .c_name = (name), .c_min = (min), .c_max = (max), \ 156 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 157 .c_step2 = 0, .c_step2cnt = 0, \ 158 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 159 .c_enable_val = (eval), .c_disable_val = (dval), \ 160 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 161 162 #define AXP_CTRL_SW(name, ereg, emask) \ 163 { .c_name = (name), \ 164 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 165 .c_enable_val = (emask), .c_disable_val = 0 } 166 167 static const struct axppmic_ctrl axp803_ctrls[] = { 168 AXP_CTRL("dldo1", 700, 3300, 100, 169 0x12, __BIT(3), 0x15, __BITS(4,0)), 170 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 171 0x12, __BIT(4), 0x16, __BITS(4,0)), 172 AXP_CTRL("dldo3", 700, 3300, 100, 173 0x12, __BIT(5), 0x17, __BITS(4,0)), 174 AXP_CTRL("dldo4", 700, 3300, 100, 175 0x12, __BIT(6), 0x18, __BITS(4,0)), 176 AXP_CTRL("eldo1", 700, 1900, 50, 177 0x12, __BIT(0), 0x19, __BITS(4,0)), 178 AXP_CTRL("eldo2", 700, 1900, 50, 179 0x12, __BIT(1), 0x1a, __BITS(4,0)), 180 AXP_CTRL("eldo3", 700, 1900, 50, 181 0x12, __BIT(2), 0x1b, __BITS(4,0)), 182 AXP_CTRL("fldo1", 700, 1450, 50, 183 0x13, __BIT(2), 0x1c, __BITS(3,0)), 184 AXP_CTRL("fldo2", 700, 1450, 50, 185 0x13, __BIT(3), 0x1d, __BITS(3,0)), 186 AXP_CTRL("dcdc1", 1600, 3400, 100, 187 0x10, __BIT(0), 0x20, __BITS(4,0)), 188 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 189 0x10, __BIT(1), 0x21, __BITS(6,0)), 190 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 191 0x10, __BIT(2), 0x22, __BITS(6,0)), 192 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 193 0x10, __BIT(3), 0x23, __BITS(6,0)), 194 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 195 0x10, __BIT(4), 0x24, __BITS(6,0)), 196 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 197 0x10, __BIT(5), 0x25, __BITS(6,0)), 198 AXP_CTRL("aldo1", 700, 3300, 100, 199 0x13, __BIT(5), 0x28, __BITS(4,0)), 200 AXP_CTRL("aldo2", 700, 3300, 100, 201 0x13, __BIT(6), 0x29, __BITS(4,0)), 202 AXP_CTRL("aldo3", 700, 3300, 100, 203 0x13, __BIT(7), 0x2a, __BITS(4,0)), 204 }; 205 206 static const struct axppmic_ctrl axp805_ctrls[] = { 207 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 208 0x10, __BIT(0), 0x12, __BITS(6,0)), 209 AXP_CTRL("dcdcb", 1000, 2550, 50, 210 0x10, __BIT(1), 0x13, __BITS(4,0)), 211 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 212 0x10, __BIT(2), 0x14, __BITS(6,0)), 213 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 214 0x10, __BIT(3), 0x15, __BITS(5,0)), 215 AXP_CTRL("dcdce", 1100, 3400, 100, 216 0x10, __BIT(4), 0x16, __BITS(4,0)), 217 AXP_CTRL("aldo1", 700, 3300, 100, 218 0x10, __BIT(5), 0x17, __BITS(4,0)), 219 AXP_CTRL("aldo2", 700, 3400, 100, 220 0x10, __BIT(6), 0x18, __BITS(4,0)), 221 AXP_CTRL("aldo3", 700, 3300, 100, 222 0x10, __BIT(7), 0x19, __BITS(4,0)), 223 AXP_CTRL("bldo1", 700, 1900, 100, 224 0x11, __BIT(0), 0x20, __BITS(3,0)), 225 AXP_CTRL("bldo2", 700, 1900, 100, 226 0x11, __BIT(1), 0x21, __BITS(3,0)), 227 AXP_CTRL("bldo3", 700, 1900, 100, 228 0x11, __BIT(2), 0x22, __BITS(3,0)), 229 AXP_CTRL("bldo4", 700, 1900, 100, 230 0x11, __BIT(3), 0x23, __BITS(3,0)), 231 AXP_CTRL("cldo1", 700, 3300, 100, 232 0x11, __BIT(4), 0x24, __BITS(4,0)), 233 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 234 0x11, __BIT(5), 0x25, __BITS(4,0)), 235 AXP_CTRL("cldo3", 700, 3300, 100, 236 0x11, __BIT(6), 0x26, __BITS(4,0)), 237 }; 238 239 static const struct axppmic_ctrl axp809_ctrls[] = { 240 AXP_CTRL("dc5ldo", 700, 1400, 100, 241 0x10, __BIT(0), 0x1c, __BITS(2,0)), 242 AXP_CTRL("dcdc1", 1600, 3400, 100, 243 0x10, __BIT(1), 0x21, __BITS(4,0)), 244 AXP_CTRL("dcdc2", 600, 1540, 20, 245 0x10, __BIT(2), 0x22, __BITS(5,0)), 246 AXP_CTRL("dcdc3", 600, 1860, 20, 247 0x10, __BIT(3), 0x23, __BITS(5,0)), 248 AXP_CTRL2_RANGE("dcdc4", 600, 2600, 20, 47, 1800, 100, 9, 249 0x10, __BIT(4), 0x24, __BITS(5,0)), 250 AXP_CTRL("dcdc5", 1000, 2550, 50, 251 0x10, __BIT(5), 0x25, __BITS(4,0)), 252 AXP_CTRL("aldo1", 700, 3300, 100, 253 0x10, __BIT(6), 0x28, __BITS(4,0)), 254 AXP_CTRL("aldo2", 700, 3300, 100, 255 0x10, __BIT(7), 0x29, __BITS(4,0)), 256 AXP_CTRL("eldo1", 700, 3300, 100, 257 0x12, __BIT(0), 0x19, __BITS(4,0)), 258 AXP_CTRL("eldo2", 700, 3300, 100, 259 0x12, __BIT(1), 0x1a, __BITS(4,0)), 260 AXP_CTRL("eldo3", 700, 3300, 100, 261 0x12, __BIT(2), 0x1b, __BITS(4,0)), 262 AXP_CTRL2_RANGE("dldo1", 700, 4000, 100, 26, 3400, 200, 4, 263 0x12, __BIT(3), 0x15, __BITS(4,0)), 264 AXP_CTRL("dldo2", 700, 3300, 100, 265 0x12, __BIT(4), 0x16, __BITS(4,0)), 266 AXP_CTRL("aldo3", 700, 3300, 100, 267 0x12, __BIT(5), 0x2a, __BITS(4,0)), 268 AXP_CTRL_SW("sw", 269 0x12, __BIT(6)), 270 /* dc1sw is another switch for dcdc1 */ 271 AXP_CTRL("dc1sw", 1600, 3400, 100, 272 0x12, __BIT(7), 0x21, __BITS(4,0)), 273 AXP_CTRL_IO("ldo_io0", 700, 3300, 100, 274 0x90, __BITS(3,0), 0x3, 0x7, 0x91, __BITS(4,0)), 275 AXP_CTRL_IO("ldo_io1", 700, 3300, 100, 276 0x92, __BITS(3,0), 0x3, 0x7, 0x93, __BITS(4,0)), 277 }; 278 279 static const struct axppmic_ctrl axp813_ctrls[] = { 280 AXP_CTRL("dldo1", 700, 3300, 100, 281 0x12, __BIT(3), 0x15, __BITS(4,0)), 282 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 283 0x12, __BIT(4), 0x16, __BITS(4,0)), 284 AXP_CTRL("dldo3", 700, 3300, 100, 285 0x12, __BIT(5), 0x17, __BITS(4,0)), 286 AXP_CTRL("dldo4", 700, 3300, 100, 287 0x12, __BIT(6), 0x18, __BITS(4,0)), 288 AXP_CTRL("eldo1", 700, 1900, 50, 289 0x12, __BIT(0), 0x19, __BITS(4,0)), 290 AXP_CTRL("eldo2", 700, 1900, 50, 291 0x12, __BIT(1), 0x1a, __BITS(4,0)), 292 AXP_CTRL("eldo3", 700, 1900, 50, 293 0x12, __BIT(2), 0x1b, __BITS(4,0)), 294 AXP_CTRL("fldo1", 700, 1450, 50, 295 0x13, __BIT(2), 0x1c, __BITS(3,0)), 296 AXP_CTRL("fldo2", 700, 1450, 50, 297 0x13, __BIT(3), 0x1d, __BITS(3,0)), 298 AXP_CTRL("dcdc1", 1600, 3400, 100, 299 0x10, __BIT(0), 0x20, __BITS(4,0)), 300 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 301 0x10, __BIT(1), 0x21, __BITS(6,0)), 302 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 303 0x10, __BIT(2), 0x22, __BITS(6,0)), 304 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 305 0x10, __BIT(3), 0x23, __BITS(6,0)), 306 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 307 0x10, __BIT(4), 0x24, __BITS(6,0)), 308 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 309 0x10, __BIT(5), 0x25, __BITS(6,0)), 310 AXP_CTRL2("dcdc7", 600, 1520, 10, 51, 20, 21, 311 0x10, __BIT(6), 0x26, __BITS(6,0)), 312 AXP_CTRL("aldo1", 700, 3300, 100, 313 0x13, __BIT(5), 0x28, __BITS(4,0)), 314 AXP_CTRL("aldo2", 700, 3300, 100, 315 0x13, __BIT(6), 0x29, __BITS(4,0)), 316 AXP_CTRL("aldo3", 700, 3300, 100, 317 0x13, __BIT(7), 0x2a, __BITS(4,0)), 318 }; 319 320 struct axppmic_irq { 321 u_int reg; 322 uint8_t mask; 323 }; 324 325 #define AXPPMIC_IRQ(_reg, _mask) \ 326 { .reg = (_reg), .mask = (_mask) } 327 328 struct axppmic_config { 329 const char *name; 330 const struct axppmic_ctrl *controls; 331 u_int ncontrols; 332 u_int irq_regs; 333 bool has_battery; 334 bool has_fuel_gauge; 335 bool has_mode_set; 336 struct axppmic_irq poklirq; 337 struct axppmic_irq acinirq; 338 struct axppmic_irq vbusirq; 339 struct axppmic_irq battirq; 340 struct axppmic_irq chargeirq; 341 struct axppmic_irq chargestirq; 342 u_int batsense_step; /* uV */ 343 u_int charge_step; /* uA */ 344 u_int discharge_step; /* uA */ 345 u_int maxcap_step; /* uAh */ 346 u_int coulomb_step; /* uAh */ 347 }; 348 349 enum axppmic_sensor { 350 AXP_SENSOR_ACIN_PRESENT, 351 AXP_SENSOR_VBUS_PRESENT, 352 AXP_SENSOR_BATT_PRESENT, 353 AXP_SENSOR_BATT_CHARGING, 354 AXP_SENSOR_BATT_CHARGE_STATE, 355 AXP_SENSOR_BATT_VOLTAGE, 356 AXP_SENSOR_BATT_CHARGE_CURRENT, 357 AXP_SENSOR_BATT_DISCHARGE_CURRENT, 358 AXP_SENSOR_BATT_CAPACITY_PERCENT, 359 AXP_SENSOR_BATT_MAXIMUM_CAPACITY, 360 AXP_SENSOR_BATT_CURRENT_CAPACITY, 361 AXP_NSENSORS 362 }; 363 364 struct axppmic_softc { 365 device_t sc_dev; 366 i2c_tag_t sc_i2c; 367 i2c_addr_t sc_addr; 368 int sc_phandle; 369 370 void *sc_ih; 371 struct workqueue *sc_wq; 372 373 kmutex_t sc_intr_lock; 374 struct work sc_work; 375 bool sc_work_scheduled; 376 377 const struct axppmic_config *sc_conf; 378 379 struct sysmon_pswitch sc_smpsw; 380 381 struct sysmon_envsys *sc_sme; 382 383 envsys_data_t sc_sensor[AXP_NSENSORS]; 384 385 u_int sc_warn_thres; 386 u_int sc_shut_thres; 387 }; 388 389 struct axpreg_softc { 390 device_t sc_dev; 391 i2c_tag_t sc_i2c; 392 i2c_addr_t sc_addr; 393 const struct axppmic_ctrl *sc_ctrl; 394 }; 395 396 struct axpreg_attach_args { 397 const struct axppmic_ctrl *reg_ctrl; 398 int reg_phandle; 399 i2c_tag_t reg_i2c; 400 i2c_addr_t reg_addr; 401 }; 402 403 static const struct axppmic_config axp803_config = { 404 .name = "AXP803", 405 .controls = axp803_ctrls, 406 .ncontrols = __arraycount(axp803_ctrls), 407 .irq_regs = 6, 408 .has_battery = true, 409 .has_fuel_gauge = true, 410 .batsense_step = 1100, 411 .charge_step = 1000, 412 .discharge_step = 1000, 413 .maxcap_step = 1456, 414 .coulomb_step = 1456, 415 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 416 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 417 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 418 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 419 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 420 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 421 }; 422 423 static const struct axppmic_config axp805_config = { 424 .name = "AXP805", 425 .controls = axp805_ctrls, 426 .ncontrols = __arraycount(axp805_ctrls), 427 .irq_regs = 2, 428 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 429 }; 430 431 static const struct axppmic_config axp806_config = { 432 .name = "AXP806", 433 .controls = axp805_ctrls, 434 .ncontrols = __arraycount(axp805_ctrls), 435 #if notyet 436 .irq_regs = 2, 437 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 438 #endif 439 .has_mode_set = true, 440 }; 441 442 static const struct axppmic_config axp809_config = { 443 .name = "AXP809", 444 .controls = axp809_ctrls, 445 .ncontrols = __arraycount(axp809_ctrls), 446 }; 447 448 static const struct axppmic_config axp813_config = { 449 .name = "AXP813", 450 .controls = axp813_ctrls, 451 .ncontrols = __arraycount(axp813_ctrls), 452 .irq_regs = 6, 453 .has_battery = true, 454 .has_fuel_gauge = true, 455 .batsense_step = 1100, 456 .charge_step = 1000, 457 .discharge_step = 1000, 458 .maxcap_step = 1456, 459 .coulomb_step = 1456, 460 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 461 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 462 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 463 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 464 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 465 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 466 }; 467 468 static const struct device_compatible_entry compat_data[] = { 469 { "x-powers,axp803", (uintptr_t)&axp803_config }, 470 { "x-powers,axp805", (uintptr_t)&axp805_config }, 471 { "x-powers,axp806", (uintptr_t)&axp806_config }, 472 { "x-powers,axp809", (uintptr_t)&axp809_config }, 473 { "x-powers,axp813", (uintptr_t)&axp813_config }, 474 { NULL, 0 } 475 }; 476 477 static int 478 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 479 { 480 return iic_smbus_read_byte(tag, addr, reg, val, flags); 481 } 482 483 static int 484 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 485 { 486 return iic_smbus_write_byte(tag, addr, reg, val, flags); 487 } 488 489 static int 490 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 491 { 492 u_int vol, reg_val; 493 int nstep, error; 494 uint8_t val; 495 496 if (!c->c_voltage_mask) 497 return EINVAL; 498 499 if (min < c->c_min || min > c->c_max) 500 return EINVAL; 501 502 reg_val = 0; 503 nstep = 1; 504 vol = c->c_min; 505 506 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 507 ++reg_val; 508 vol += c->c_step1; 509 } 510 511 if (c->c_step2start) 512 vol = c->c_step2start; 513 514 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 515 ++reg_val; 516 vol += c->c_step2; 517 } 518 519 if (vol > max) 520 return EINVAL; 521 522 iic_acquire_bus(tag, 0); 523 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0)) == 0) { 524 val &= ~c->c_voltage_mask; 525 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 526 error = axppmic_write(tag, addr, c->c_voltage_reg, val, 0); 527 } 528 iic_release_bus(tag, 0); 529 530 return error; 531 } 532 533 static int 534 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 535 { 536 int reg_val, error; 537 uint8_t val; 538 539 if (!c->c_voltage_mask) 540 return EINVAL; 541 542 iic_acquire_bus(tag, 0); 543 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0); 544 iic_release_bus(tag, 0); 545 if (error) 546 return error; 547 548 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 549 if (reg_val < c->c_step1cnt) { 550 *pvol = c->c_min + reg_val * c->c_step1; 551 } else if (c->c_step2start) { 552 *pvol = c->c_step2start + 553 ((reg_val - c->c_step1cnt) * c->c_step2); 554 } else { 555 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 556 ((reg_val - c->c_step1cnt) * c->c_step2); 557 } 558 559 return 0; 560 } 561 562 static void 563 axppmic_power_poweroff(device_t dev) 564 { 565 struct axppmic_softc *sc = device_private(dev); 566 int error; 567 568 delay(1000000); 569 570 error = iic_acquire_bus(sc->sc_i2c, 0); 571 if (error == 0) { 572 error = axppmic_write(sc->sc_i2c, sc->sc_addr, 573 AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, 0); 574 iic_release_bus(sc->sc_i2c, 0); 575 } 576 if (error) { 577 device_printf(dev, "WARNING: unable to power off, error %d\n", 578 error); 579 } 580 } 581 582 static struct fdtbus_power_controller_func axppmic_power_funcs = { 583 .poweroff = axppmic_power_poweroff, 584 }; 585 586 static void 587 axppmic_task_shut(void *priv) 588 { 589 struct axppmic_softc *sc = priv; 590 591 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 592 } 593 594 static void 595 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 596 { 597 struct axppmic_softc *sc = sme->sme_cookie; 598 const struct axppmic_config *c = sc->sc_conf; 599 uint8_t val, lo, hi; 600 601 e->state = ENVSYS_SINVALID; 602 603 const bool battery_present = 604 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID && 605 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1; 606 607 switch (e->private) { 608 case AXP_SENSOR_ACIN_PRESENT: 609 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 610 e->state = ENVSYS_SVALID; 611 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 612 } 613 break; 614 case AXP_SENSOR_VBUS_PRESENT: 615 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 616 e->state = ENVSYS_SVALID; 617 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 618 } 619 break; 620 case AXP_SENSOR_BATT_PRESENT: 621 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 622 if (val & AXP_POWER_MODE_BATT_VALID) { 623 e->state = ENVSYS_SVALID; 624 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 625 } 626 } 627 break; 628 case AXP_SENSOR_BATT_CHARGING: 629 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 630 e->state = ENVSYS_SVALID; 631 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 632 } 633 break; 634 case AXP_SENSOR_BATT_CHARGE_STATE: 635 if (battery_present && 636 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 637 (val & AXP_BATT_CAP_VALID) != 0) { 638 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 639 if (batt_val <= sc->sc_shut_thres) { 640 e->state = ENVSYS_SCRITICAL; 641 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 642 } else if (batt_val <= sc->sc_warn_thres) { 643 e->state = ENVSYS_SWARNUNDER; 644 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 645 } else { 646 e->state = ENVSYS_SVALID; 647 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 648 } 649 } 650 break; 651 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 652 if (battery_present && 653 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 654 (val & AXP_BATT_CAP_VALID) != 0) { 655 e->state = ENVSYS_SVALID; 656 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 657 } 658 break; 659 case AXP_SENSOR_BATT_VOLTAGE: 660 if (battery_present && 661 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, 0) == 0 && 662 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, 0) == 0) { 663 e->state = ENVSYS_SVALID; 664 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step; 665 } 666 break; 667 case AXP_SENSOR_BATT_CHARGE_CURRENT: 668 if (battery_present && 669 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 670 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 && 671 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, 0) == 0 && 672 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, 0) == 0) { 673 e->state = ENVSYS_SVALID; 674 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step; 675 } 676 break; 677 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 678 if (battery_present && 679 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 680 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 && 681 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, 0) == 0 && 682 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, 0) == 0) { 683 e->state = ENVSYS_SVALID; 684 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step; 685 } 686 break; 687 case AXP_SENSOR_BATT_MAXIMUM_CAPACITY: 688 if (battery_present && 689 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_HI_REG, &hi, 0) == 0 && 690 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_LO_REG, &lo, 0) == 0) { 691 e->state = (hi & AXP_BATT_MAX_CAP_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 692 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->maxcap_step; 693 } 694 break; 695 case AXP_SENSOR_BATT_CURRENT_CAPACITY: 696 if (battery_present && 697 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_HI_REG, &hi, 0) == 0 && 698 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_LO_REG, &lo, 0) == 0) { 699 e->state = (hi & AXP_BATT_COULOMB_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 700 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->coulomb_step; 701 } 702 break; 703 } 704 } 705 706 static void 707 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 708 { 709 struct axppmic_softc *sc = sme->sme_cookie; 710 711 switch (e->private) { 712 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 713 case AXP_SENSOR_BATT_VOLTAGE: 714 case AXP_SENSOR_BATT_CHARGE_CURRENT: 715 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 716 /* Always update battery capacity and ADCs */ 717 iic_acquire_bus(sc->sc_i2c, 0); 718 axppmic_sensor_update(sme, e); 719 iic_release_bus(sc->sc_i2c, 0); 720 break; 721 default: 722 /* Refresh if the sensor is not in valid state */ 723 if (e->state != ENVSYS_SVALID) { 724 iic_acquire_bus(sc->sc_i2c, 0); 725 axppmic_sensor_update(sme, e); 726 iic_release_bus(sc->sc_i2c, 0); 727 } 728 break; 729 } 730 } 731 732 static int 733 axppmic_intr(void *priv) 734 { 735 struct axppmic_softc * const sc = priv; 736 737 mutex_enter(&sc->sc_intr_lock); 738 739 fdtbus_intr_mask(sc->sc_phandle, sc->sc_ih); 740 741 /* Interrupt is always masked when work is scheduled! */ 742 KASSERT(!sc->sc_work_scheduled); 743 sc->sc_work_scheduled = true; 744 workqueue_enqueue(sc->sc_wq, &sc->sc_work, NULL); 745 746 mutex_exit(&sc->sc_intr_lock); 747 748 return 1; 749 } 750 751 static void 752 axppmic_work(struct work *work, void *arg) 753 { 754 struct axppmic_softc * const sc = 755 container_of(work, struct axppmic_softc, sc_work); 756 const struct axppmic_config * const c = sc->sc_conf; 757 const int flags = 0; 758 uint8_t stat; 759 u_int n; 760 761 KASSERT(sc->sc_work_scheduled); 762 763 iic_acquire_bus(sc->sc_i2c, flags); 764 for (n = 1; n <= c->irq_regs; n++) { 765 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 766 if (stat != 0) { 767 axppmic_write(sc->sc_i2c, sc->sc_addr, 768 AXP_IRQ_STATUS_REG(n), stat, flags); 769 } 770 771 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 772 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 773 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 774 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 775 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 776 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 777 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 778 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 779 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 780 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 781 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 782 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 783 } 784 } 785 iic_release_bus(sc->sc_i2c, flags); 786 787 mutex_enter(&sc->sc_intr_lock); 788 sc->sc_work_scheduled = false; 789 fdtbus_intr_unmask(sc->sc_phandle, sc->sc_ih); 790 mutex_exit(&sc->sc_intr_lock); 791 } 792 793 static void 794 axppmic_attach_acadapter(struct axppmic_softc *sc) 795 { 796 envsys_data_t *e; 797 798 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 799 e->private = AXP_SENSOR_ACIN_PRESENT; 800 e->units = ENVSYS_INDICATOR; 801 e->state = ENVSYS_SINVALID; 802 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 803 sysmon_envsys_sensor_attach(sc->sc_sme, e); 804 805 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 806 e->private = AXP_SENSOR_VBUS_PRESENT; 807 e->units = ENVSYS_INDICATOR; 808 e->state = ENVSYS_SINVALID; 809 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 810 sysmon_envsys_sensor_attach(sc->sc_sme, e); 811 } 812 813 static void 814 axppmic_attach_battery(struct axppmic_softc *sc) 815 { 816 const struct axppmic_config *c = sc->sc_conf; 817 envsys_data_t *e; 818 uint8_t val; 819 820 iic_acquire_bus(sc->sc_i2c, 0); 821 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, 0) == 0) { 822 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 823 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 824 } 825 iic_release_bus(sc->sc_i2c, 0); 826 827 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 828 e->private = AXP_SENSOR_BATT_PRESENT; 829 e->units = ENVSYS_INDICATOR; 830 e->state = ENVSYS_SINVALID; 831 strlcpy(e->desc, "battery present", sizeof(e->desc)); 832 sysmon_envsys_sensor_attach(sc->sc_sme, e); 833 834 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 835 e->private = AXP_SENSOR_BATT_CHARGING; 836 e->units = ENVSYS_BATTERY_CHARGE; 837 e->state = ENVSYS_SINVALID; 838 strlcpy(e->desc, "charging", sizeof(e->desc)); 839 sysmon_envsys_sensor_attach(sc->sc_sme, e); 840 841 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 842 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 843 e->units = ENVSYS_BATTERY_CAPACITY; 844 e->flags = ENVSYS_FMONSTCHANGED; 845 e->state = ENVSYS_SINVALID; 846 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 847 strlcpy(e->desc, "charge state", sizeof(e->desc)); 848 sysmon_envsys_sensor_attach(sc->sc_sme, e); 849 850 if (c->batsense_step) { 851 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE]; 852 e->private = AXP_SENSOR_BATT_VOLTAGE; 853 e->units = ENVSYS_SVOLTS_DC; 854 e->state = ENVSYS_SINVALID; 855 strlcpy(e->desc, "battery voltage", sizeof(e->desc)); 856 sysmon_envsys_sensor_attach(sc->sc_sme, e); 857 } 858 859 if (c->charge_step) { 860 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT]; 861 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT; 862 e->units = ENVSYS_SAMPS; 863 e->state = ENVSYS_SINVALID; 864 strlcpy(e->desc, "battery charge current", sizeof(e->desc)); 865 sysmon_envsys_sensor_attach(sc->sc_sme, e); 866 } 867 868 if (c->discharge_step) { 869 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT]; 870 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT; 871 e->units = ENVSYS_SAMPS; 872 e->state = ENVSYS_SINVALID; 873 strlcpy(e->desc, "battery discharge current", sizeof(e->desc)); 874 sysmon_envsys_sensor_attach(sc->sc_sme, e); 875 } 876 877 if (c->has_fuel_gauge) { 878 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT]; 879 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT; 880 e->units = ENVSYS_INTEGER; 881 e->state = ENVSYS_SINVALID; 882 e->flags = ENVSYS_FPERCENT; 883 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 884 sysmon_envsys_sensor_attach(sc->sc_sme, e); 885 } 886 887 if (c->maxcap_step) { 888 e = &sc->sc_sensor[AXP_SENSOR_BATT_MAXIMUM_CAPACITY]; 889 e->private = AXP_SENSOR_BATT_MAXIMUM_CAPACITY; 890 e->units = ENVSYS_SAMPHOUR; 891 e->state = ENVSYS_SINVALID; 892 strlcpy(e->desc, "battery maximum capacity", sizeof(e->desc)); 893 sysmon_envsys_sensor_attach(sc->sc_sme, e); 894 } 895 896 if (c->coulomb_step) { 897 e = &sc->sc_sensor[AXP_SENSOR_BATT_CURRENT_CAPACITY]; 898 e->private = AXP_SENSOR_BATT_CURRENT_CAPACITY; 899 e->units = ENVSYS_SAMPHOUR; 900 e->state = ENVSYS_SINVALID; 901 strlcpy(e->desc, "battery current capacity", sizeof(e->desc)); 902 sysmon_envsys_sensor_attach(sc->sc_sme, e); 903 } 904 } 905 906 static void 907 axppmic_attach_sensors(struct axppmic_softc *sc) 908 { 909 if (sc->sc_conf->has_battery) { 910 sc->sc_sme = sysmon_envsys_create(); 911 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 912 sc->sc_sme->sme_cookie = sc; 913 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 914 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 915 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 916 917 axppmic_attach_acadapter(sc); 918 axppmic_attach_battery(sc); 919 920 sysmon_envsys_register(sc->sc_sme); 921 } 922 } 923 924 925 static int 926 axppmic_match(device_t parent, cfdata_t match, void *aux) 927 { 928 struct i2c_attach_args *ia = aux; 929 int match_result; 930 931 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 932 return match_result; 933 934 /* This device is direct-config only. */ 935 936 return 0; 937 } 938 939 static void 940 axppmic_attach(device_t parent, device_t self, void *aux) 941 { 942 struct axppmic_softc *sc = device_private(self); 943 const struct device_compatible_entry *dce = NULL; 944 const struct axppmic_config *c; 945 struct axpreg_attach_args aaa; 946 struct i2c_attach_args *ia = aux; 947 int phandle, child, i; 948 uint8_t irq_mask, val; 949 int error; 950 951 (void) iic_compatible_match(ia, compat_data, &dce); 952 KASSERT(dce != NULL); 953 c = (void *)dce->data; 954 955 sc->sc_dev = self; 956 sc->sc_i2c = ia->ia_tag; 957 sc->sc_addr = ia->ia_addr; 958 sc->sc_phandle = ia->ia_cookie; 959 sc->sc_conf = c; 960 961 aprint_naive("\n"); 962 aprint_normal(": %s\n", c->name); 963 964 if (c->has_mode_set) { 965 const bool master_mode = of_hasprop(sc->sc_phandle, "x-powers,self-working-mode") || 966 of_hasprop(sc->sc_phandle, "x-powers,master-mode"); 967 968 iic_acquire_bus(sc->sc_i2c, 0); 969 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_ADDR_EXT_REG, 970 master_mode ? AXP_ADDR_EXT_MASTER : AXP_ADDR_EXT_SLAVE, 0); 971 iic_release_bus(sc->sc_i2c, 0); 972 } 973 974 iic_acquire_bus(sc->sc_i2c, 0); 975 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_CHIP_ID_REG, &val, 0); 976 iic_release_bus(sc->sc_i2c, 0); 977 if (error != 0) { 978 aprint_error_dev(self, "couldn't read chipid\n"); 979 return; 980 } 981 aprint_debug_dev(self, "chipid %#x\n", val); 982 983 sc->sc_smpsw.smpsw_name = device_xname(self); 984 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 985 sysmon_pswitch_register(&sc->sc_smpsw); 986 987 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 988 989 if (c->irq_regs > 0) { 990 char intrstr[128]; 991 992 if (!fdtbus_intr_str(sc->sc_phandle, 0, 993 intrstr, sizeof(intrstr))) { 994 aprint_error_dev(self, 995 "WARNING: failed to decode interrupt\n"); 996 } 997 998 sc->sc_ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, 999 FDT_INTR_MPSAFE, 1000 axppmic_intr, sc); 1001 if (sc->sc_ih == NULL) { 1002 aprint_error_dev(self, 1003 "WARNING: couldn't establish interrupt handler\n"); 1004 } 1005 1006 error = workqueue_create(&sc->sc_wq, device_xname(self), 1007 axppmic_work, NULL, 1008 PRI_SOFTSERIAL, IPL_VM, 1009 WQ_MPSAFE); 1010 if (error) { 1011 sc->sc_wq = NULL; 1012 aprint_error_dev(self, 1013 "WARNING: couldn't create work queue: error %d\n", 1014 error); 1015 } 1016 1017 if (sc->sc_ih != NULL && sc->sc_wq != NULL) { 1018 iic_acquire_bus(sc->sc_i2c, 0); 1019 for (i = 1; i <= c->irq_regs; i++) { 1020 irq_mask = 0; 1021 if (i == c->poklirq.reg) 1022 irq_mask |= c->poklirq.mask; 1023 if (i == c->acinirq.reg) 1024 irq_mask |= c->acinirq.mask; 1025 if (i == c->vbusirq.reg) 1026 irq_mask |= c->vbusirq.mask; 1027 if (i == c->battirq.reg) 1028 irq_mask |= c->battirq.mask; 1029 if (i == c->chargeirq.reg) 1030 irq_mask |= c->chargeirq.mask; 1031 if (i == c->chargestirq.reg) 1032 irq_mask |= c->chargestirq.mask; 1033 axppmic_write(sc->sc_i2c, sc->sc_addr, 1034 AXP_IRQ_ENABLE_REG(i), 1035 irq_mask, 0); 1036 } 1037 iic_release_bus(sc->sc_i2c, 0); 1038 } 1039 } 1040 1041 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 1042 &axppmic_power_funcs); 1043 1044 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 1045 if (phandle > 0) { 1046 aaa.reg_i2c = sc->sc_i2c; 1047 aaa.reg_addr = sc->sc_addr; 1048 for (i = 0; i < c->ncontrols; i++) { 1049 const struct axppmic_ctrl *ctrl = &c->controls[i]; 1050 child = of_find_firstchild_byname(phandle, ctrl->c_name); 1051 if (child <= 0) 1052 continue; 1053 aaa.reg_ctrl = ctrl; 1054 aaa.reg_phandle = child; 1055 config_found(sc->sc_dev, &aaa, NULL); 1056 } 1057 } 1058 1059 if (c->has_battery) 1060 axppmic_attach_sensors(sc); 1061 } 1062 1063 static int 1064 axpreg_acquire(device_t dev) 1065 { 1066 return 0; 1067 } 1068 1069 static void 1070 axpreg_release(device_t dev) 1071 { 1072 } 1073 1074 static int 1075 axpreg_enable(device_t dev, bool enable) 1076 { 1077 struct axpreg_softc *sc = device_private(dev); 1078 const struct axppmic_ctrl *c = sc->sc_ctrl; 1079 const int flags = 0; 1080 uint8_t val; 1081 int error; 1082 1083 if (!c->c_enable_mask) 1084 return EINVAL; 1085 1086 iic_acquire_bus(sc->sc_i2c, flags); 1087 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 1088 val &= ~c->c_enable_mask; 1089 if (enable) 1090 val |= c->c_enable_val; 1091 else 1092 val |= c->c_disable_val; 1093 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 1094 } 1095 iic_release_bus(sc->sc_i2c, flags); 1096 1097 return error; 1098 } 1099 1100 static int 1101 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 1102 { 1103 struct axpreg_softc *sc = device_private(dev); 1104 const struct axppmic_ctrl *c = sc->sc_ctrl; 1105 1106 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 1107 min_uvol / 1000, max_uvol / 1000); 1108 } 1109 1110 static int 1111 axpreg_get_voltage(device_t dev, u_int *puvol) 1112 { 1113 struct axpreg_softc *sc = device_private(dev); 1114 const struct axppmic_ctrl *c = sc->sc_ctrl; 1115 int error; 1116 u_int vol; 1117 1118 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 1119 if (error) 1120 return error; 1121 1122 *puvol = vol * 1000; 1123 return 0; 1124 } 1125 1126 static struct fdtbus_regulator_controller_func axpreg_funcs = { 1127 .acquire = axpreg_acquire, 1128 .release = axpreg_release, 1129 .enable = axpreg_enable, 1130 .set_voltage = axpreg_set_voltage, 1131 .get_voltage = axpreg_get_voltage, 1132 }; 1133 1134 static int 1135 axpreg_match(device_t parent, cfdata_t match, void *aux) 1136 { 1137 return 1; 1138 } 1139 1140 static void 1141 axpreg_attach(device_t parent, device_t self, void *aux) 1142 { 1143 struct axpreg_softc *sc = device_private(self); 1144 struct axpreg_attach_args *aaa = aux; 1145 const int phandle = aaa->reg_phandle; 1146 const char *name; 1147 u_int uvol, min_uvol, max_uvol; 1148 1149 sc->sc_dev = self; 1150 sc->sc_i2c = aaa->reg_i2c; 1151 sc->sc_addr = aaa->reg_addr; 1152 sc->sc_ctrl = aaa->reg_ctrl; 1153 1154 fdtbus_register_regulator_controller(self, phandle, 1155 &axpreg_funcs); 1156 1157 aprint_naive("\n"); 1158 name = fdtbus_get_string(phandle, "regulator-name"); 1159 if (name) 1160 aprint_normal(": %s\n", name); 1161 else 1162 aprint_normal("\n"); 1163 1164 axpreg_get_voltage(self, &uvol); 1165 if (of_getprop_uint32(phandle, "regulator-min-microvolt", &min_uvol) == 0 && 1166 of_getprop_uint32(phandle, "regulator-max-microvolt", &max_uvol) == 0) { 1167 if (uvol < min_uvol || uvol > max_uvol) { 1168 aprint_debug_dev(self, "fix voltage %u uV -> %u/%u uV\n", 1169 uvol, min_uvol, max_uvol); 1170 axpreg_set_voltage(self, min_uvol, max_uvol); 1171 } 1172 } 1173 1174 if (of_hasprop(phandle, "regulator-always-on") || 1175 of_hasprop(phandle, "regulator-boot-on")) { 1176 axpreg_enable(self, true); 1177 } 1178 } 1179 1180 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 1181 axppmic_match, axppmic_attach, NULL, NULL); 1182 1183 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 1184 axpreg_match, axpreg_attach, NULL, NULL); 1185