1 /* $NetBSD: if_rtk_cardbus.c,v 1.46 2011/08/01 11:20:27 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Masanori Kanaoka 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * if_rtk_cardbus.c: 32 * Cardbus specific routines for Realtek 8139 ethernet adapter. 33 * Tested for 34 * - elecom-Laneed LD-10/100CBA (Accton MPX5030) 35 * - MELCO LPC3-TX-CB (Realtek 8139) 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_rtk_cardbus.c,v 1.46 2011/08/01 11:20:27 drochner Exp $"); 40 41 #include "opt_inet.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/device.h> 48 #include <sys/sockio.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/if_ether.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #if NRND > 0 65 #include <sys/rnd.h> 66 #endif 67 68 #include <sys/bus.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/cardbus/cardbusvar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 /* 81 * Default to using PIO access for this driver. On SMP systems, 82 * there appear to be problems with memory mapped mode: it looks like 83 * doing too many memory mapped access back to back in rapid succession 84 * can hang the bus. I'm inclined to blame this on crummy design/construction 85 * on the part of Realtek. Memory mapped mode does appear to work on 86 * uniprocessor systems though. 87 */ 88 #define RTK_USEIOSPACE 89 90 #include <dev/ic/rtl81x9reg.h> 91 #include <dev/ic/rtl81x9var.h> 92 93 /* 94 * Various supported device vendors/types and their names. 95 */ 96 static const struct rtk_type rtk_cardbus_devs[] = { 97 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030, 98 RTK_8139, "Accton MPX 5030/5038 10/100BaseTX" }, 99 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD, 100 RTK_8139, "D-Link DFE-690TXD 10/100BaseTX" }, 101 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8138, 102 RTK_8139, "Realtek 8138 10/100BaseTX" }, 103 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 104 RTK_8139, "Realtek 8139 10/100BaseTX" }, 105 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD, 106 RTK_8139, "Corega FEther CB-TXD 10/100BaseTX" }, 107 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD, 108 RTK_8139, "Corega FEther II CB-TXD 10/100BaseTX" }, 109 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3603_TX, 110 RTK_8139, "Planex FNW-3603 10/100BaseTX" }, 111 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX, 112 RTK_8139, "Planex 10/100BaseTX FNW-3800-TX" }, 113 { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2000VX, 114 RTK_8139, "AboCom FE2000VX 10/100BaseTX" }, 115 116 { 0, 0, 0, NULL } 117 }; 118 119 static int rtk_cardbus_match(device_t, cfdata_t, void *); 120 static void rtk_cardbus_attach(device_t, device_t, void *); 121 static int rtk_cardbus_detach(device_t, int); 122 123 struct rtk_cardbus_softc { 124 struct rtk_softc sc_rtk; /* real rtk softc */ 125 126 /* CardBus-specific goo. */ 127 void *sc_ih; 128 cardbus_devfunc_t sc_ct; 129 pcitag_t sc_tag; 130 pcireg_t sc_csr; 131 int sc_bar_reg; 132 pcireg_t sc_bar_val; 133 }; 134 135 CFATTACH_DECL_NEW(rtk_cardbus, sizeof(struct rtk_cardbus_softc), 136 rtk_cardbus_match, rtk_cardbus_attach, rtk_cardbus_detach, rtk_activate); 137 138 const struct rtk_type *rtk_cardbus_lookup(const struct cardbus_attach_args *); 139 140 void rtk_cardbus_setup(struct rtk_cardbus_softc *); 141 142 int rtk_cardbus_enable(struct rtk_softc *); 143 void rtk_cardbus_disable(struct rtk_softc *); 144 void rtk_cardbus_power(struct rtk_softc *, int); 145 146 const struct rtk_type * 147 rtk_cardbus_lookup(const struct cardbus_attach_args *ca) 148 { 149 const struct rtk_type *t; 150 151 for (t = rtk_cardbus_devs; t->rtk_name != NULL; t++){ 152 if (PCI_VENDOR(ca->ca_id) == t->rtk_vid && 153 PCI_PRODUCT(ca->ca_id) == t->rtk_did) { 154 return t; 155 } 156 } 157 return NULL; 158 } 159 160 int 161 rtk_cardbus_match(device_t parent, cfdata_t cf, void *aux) 162 { 163 struct cardbus_attach_args *ca = aux; 164 165 if (rtk_cardbus_lookup(ca) != NULL) 166 return 1; 167 168 return 0; 169 } 170 171 172 void 173 rtk_cardbus_attach(device_t parent, device_t self, void *aux) 174 { 175 struct rtk_cardbus_softc *csc = device_private(self); 176 struct rtk_softc *sc = &csc->sc_rtk; 177 struct cardbus_attach_args *ca = aux; 178 cardbus_devfunc_t ct = ca->ca_ct; 179 const struct rtk_type *t; 180 bus_addr_t adr; 181 182 sc->sc_dev = self; 183 sc->sc_dmat = ca->ca_dmat; 184 csc->sc_ct = ct; 185 csc->sc_tag = ca->ca_tag; 186 187 t = rtk_cardbus_lookup(ca); 188 if (t == NULL) { 189 aprint_error("\n"); 190 panic("%s: impossible", __func__); 191 } 192 aprint_normal(": %s\n", t->rtk_name); 193 194 /* 195 * Power management hooks. 196 */ 197 sc->sc_enable = rtk_cardbus_enable; 198 sc->sc_disable = rtk_cardbus_disable; 199 200 /* 201 * Map control/status registers. 202 */ 203 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE; 204 #ifdef RTK_USEIOSPACE 205 if (Cardbus_mapreg_map(ct, RTK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 206 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) { 207 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 208 csc->sc_bar_reg = RTK_PCI_LOIO; 209 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO; 210 } 211 #else 212 if (Cardbus_mapreg_map(ct, RTK_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 213 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) { 214 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 215 csc->sc_bar_reg = RTK_PCI_LOMEM; 216 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; 217 } 218 #endif 219 else { 220 aprint_error_dev(self, " unable to map deviceregisters\n"); 221 return; 222 } 223 /* 224 * Handle power management nonsense and initialize the 225 * configuration registers. 226 */ 227 rtk_cardbus_setup(csc); 228 229 rtk_attach(sc); 230 231 if (pmf_device_register(self, NULL, NULL)) 232 pmf_class_network_register(self, &sc->ethercom.ec_if); 233 else 234 aprint_error_dev(self, "couldn't establish power handler\n"); 235 236 /* 237 * Power down the socket. 238 */ 239 Cardbus_function_disable(csc->sc_ct); 240 } 241 242 int 243 rtk_cardbus_detach(device_t self, int flags) 244 { 245 struct rtk_cardbus_softc *csc = device_private(self); 246 struct rtk_softc *sc = &csc->sc_rtk; 247 struct cardbus_devfunc *ct = csc->sc_ct; 248 int rv; 249 250 #ifdef DIAGNOSTIC 251 if (ct == NULL) 252 panic("%s: data structure lacks", device_xname(self)); 253 #endif 254 rv = rtk_detach(sc); 255 if (rv) 256 return rv; 257 /* 258 * Unhook the interrupt handler. 259 */ 260 if (csc->sc_ih != NULL) 261 Cardbus_intr_disestablish(ct, csc->sc_ih); 262 263 /* 264 * Release bus space and close window. 265 */ 266 if (csc->sc_bar_reg != 0) 267 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, 268 sc->rtk_btag, sc->rtk_bhandle, sc->rtk_bsize); 269 270 return 0; 271 } 272 273 void 274 rtk_cardbus_setup(struct rtk_cardbus_softc *csc) 275 { 276 struct rtk_softc *sc = &csc->sc_rtk; 277 cardbus_devfunc_t ct = csc->sc_ct; 278 cardbus_chipset_tag_t cc = ct->ct_cc; 279 cardbus_function_tag_t cf = ct->ct_cf; 280 pcireg_t reg, command; 281 int pmreg; 282 283 /* 284 * Handle power management nonsense. 285 */ 286 if (cardbus_get_capability(cc, cf, csc->sc_tag, 287 PCI_CAP_PWRMGMT, &pmreg, 0)) { 288 command = Cardbus_conf_read(ct, csc->sc_tag, 289 pmreg + PCI_PMCSR); 290 if (command & PCI_PMCSR_STATE_MASK) { 291 pcireg_t iobase, membase, irq; 292 293 /* Save important PCI config data. */ 294 iobase = Cardbus_conf_read(ct, csc->sc_tag, 295 RTK_PCI_LOIO); 296 membase = Cardbus_conf_read(ct, csc->sc_tag, 297 RTK_PCI_LOMEM); 298 irq = Cardbus_conf_read(ct, csc->sc_tag, 299 PCI_INTERRUPT_REG); 300 301 /* Reset the power state. */ 302 aprint_normal_dev(sc->sc_dev, 303 "chip is in D%d power mode -- setting to D0\n", 304 command & PCI_PMCSR_STATE_MASK); 305 command &= ~PCI_PMCSR_STATE_MASK; 306 Cardbus_conf_write(ct, csc->sc_tag, 307 pmreg + PCI_PMCSR, command); 308 309 /* Restore PCI config data. */ 310 Cardbus_conf_write(ct, csc->sc_tag, 311 RTK_PCI_LOIO, iobase); 312 Cardbus_conf_write(ct, csc->sc_tag, 313 RTK_PCI_LOMEM, membase); 314 Cardbus_conf_write(ct, csc->sc_tag, 315 PCI_INTERRUPT_REG, irq); 316 } 317 } 318 319 /* Program the BAR */ 320 Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val); 321 322 /* Enable the appropriate bits in the CARDBUS CSR. */ 323 reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG); 324 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 325 reg |= csc->sc_csr; 326 Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg); 327 328 /* 329 * Make sure the latency timer is set to some reasonable 330 * value. 331 */ 332 reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG); 333 if (PCI_LATTIMER(reg) < 0x20) { 334 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 335 reg |= (0x20 << PCI_LATTIMER_SHIFT); 336 Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg); 337 } 338 } 339 340 int 341 rtk_cardbus_enable(struct rtk_softc *sc) 342 { 343 struct rtk_cardbus_softc *csc = (struct rtk_cardbus_softc *)sc; 344 cardbus_devfunc_t ct = csc->sc_ct; 345 346 /* 347 * Power on the socket. 348 */ 349 Cardbus_function_enable(ct); 350 351 /* 352 * Set up the PCI configuration registers. 353 */ 354 rtk_cardbus_setup(csc); 355 356 /* 357 * Map and establish the interrupt. 358 */ 359 csc->sc_ih = Cardbus_intr_establish(ct, IPL_NET, rtk_intr, sc); 360 if (csc->sc_ih == NULL) { 361 aprint_error_dev(sc->sc_dev, 362 "unable to establish interrupt\n"); 363 Cardbus_function_disable(csc->sc_ct); 364 return 1; 365 } 366 return 0; 367 } 368 369 void 370 rtk_cardbus_disable(struct rtk_softc *sc) 371 { 372 struct rtk_cardbus_softc *csc = (struct rtk_cardbus_softc *)sc; 373 cardbus_devfunc_t ct = csc->sc_ct; 374 375 /* Unhook the interrupt handler. */ 376 Cardbus_intr_disestablish(ct, csc->sc_ih); 377 csc->sc_ih = NULL; 378 379 /* Power down the socket. */ 380 Cardbus_function_disable(ct); 381 } 382