1 /* $NetBSD: if_rtk_cardbus.c,v 1.49 2022/09/25 17:33:19 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2000 Masanori Kanaoka
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * if_rtk_cardbus.c:
32 * Cardbus specific routines for Realtek 8139 ethernet adapter.
33 * Tested for
34 * - elecom-Laneed LD-10/100CBA (Accton MPX5030)
35 * - MELCO LPC3-TX-CB (Realtek 8139)
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: if_rtk_cardbus.c,v 1.49 2022/09/25 17:33:19 thorpej Exp $");
40
41 #include "opt_inet.h"
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/callout.h>
46 #include <sys/device.h>
47 #include <sys/sockio.h>
48 #include <sys/mbuf.h>
49 #include <sys/kernel.h>
50 #include <sys/socket.h>
51
52 #include <net/if.h>
53 #include <net/if_arp.h>
54 #include <net/if_ether.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #ifdef INET
58 #include <netinet/in.h>
59 #include <netinet/if_inarp.h>
60 #endif
61
62 #include <sys/bus.h>
63
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66 #include <dev/pci/pcidevs.h>
67
68 #include <dev/cardbus/cardbusvar.h>
69 #include <dev/pci/pcidevs.h>
70
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
73
74 /*
75 * Default to using PIO access for this driver. On SMP systems,
76 * there appear to be problems with memory mapped mode: it looks like
77 * doing too many memory mapped access back to back in rapid succession
78 * can hang the bus. I'm inclined to blame this on crummy design/construction
79 * on the part of Realtek. Memory mapped mode does appear to work on
80 * uniprocessor systems though.
81 */
82 #define RTK_USEIOSPACE
83
84 #include <dev/ic/rtl81x9reg.h>
85 #include <dev/ic/rtl81x9var.h>
86
87 /*
88 * Various supported device vendors/types and their names.
89 */
90 static const struct rtk_type rtk_cardbus_devs[] = {
91 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030,
92 RTK_8139, "Accton MPX 5030/5038 10/100BaseTX" },
93 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD,
94 RTK_8139, "D-Link DFE-690TXD 10/100BaseTX" },
95 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8138,
96 RTK_8139, "Realtek 8138 10/100BaseTX" },
97 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
98 RTK_8139, "Realtek 8139 10/100BaseTX" },
99 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD,
100 RTK_8139, "Corega FEther CB-TXD 10/100BaseTX" },
101 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD,
102 RTK_8139, "Corega FEther II CB-TXD 10/100BaseTX" },
103 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3603_TX,
104 RTK_8139, "Planex FNW-3603 10/100BaseTX" },
105 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX,
106 RTK_8139, "Planex 10/100BaseTX FNW-3800-TX" },
107 { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2000VX,
108 RTK_8139, "AboCom FE2000VX 10/100BaseTX" },
109
110 { 0, 0, 0, NULL }
111 };
112
113 static int rtk_cardbus_match(device_t, cfdata_t, void *);
114 static void rtk_cardbus_attach(device_t, device_t, void *);
115 static int rtk_cardbus_detach(device_t, int);
116
117 struct rtk_cardbus_softc {
118 struct rtk_softc sc_rtk; /* real rtk softc */
119
120 /* CardBus-specific goo. */
121 void *sc_ih;
122 cardbus_devfunc_t sc_ct;
123 pcitag_t sc_tag;
124 pcireg_t sc_csr;
125 int sc_bar_reg;
126 pcireg_t sc_bar_val;
127 };
128
129 CFATTACH_DECL_NEW(rtk_cardbus, sizeof(struct rtk_cardbus_softc),
130 rtk_cardbus_match, rtk_cardbus_attach, rtk_cardbus_detach, rtk_activate);
131
132 const struct rtk_type *rtk_cardbus_lookup(const struct cardbus_attach_args *);
133
134 void rtk_cardbus_setup(struct rtk_cardbus_softc *);
135
136 int rtk_cardbus_enable(struct rtk_softc *);
137 void rtk_cardbus_disable(struct rtk_softc *);
138 void rtk_cardbus_power(struct rtk_softc *, int);
139
140 const struct rtk_type *
rtk_cardbus_lookup(const struct cardbus_attach_args * ca)141 rtk_cardbus_lookup(const struct cardbus_attach_args *ca)
142 {
143 const struct rtk_type *t;
144
145 for (t = rtk_cardbus_devs; t->rtk_name != NULL; t++){
146 if (PCI_VENDOR(ca->ca_id) == t->rtk_vid &&
147 PCI_PRODUCT(ca->ca_id) == t->rtk_did) {
148 return t;
149 }
150 }
151 return NULL;
152 }
153
154 int
rtk_cardbus_match(device_t parent,cfdata_t cf,void * aux)155 rtk_cardbus_match(device_t parent, cfdata_t cf, void *aux)
156 {
157 struct cardbus_attach_args *ca = aux;
158
159 if (rtk_cardbus_lookup(ca) != NULL)
160 return 1;
161
162 return 0;
163 }
164
165
166 void
rtk_cardbus_attach(device_t parent,device_t self,void * aux)167 rtk_cardbus_attach(device_t parent, device_t self, void *aux)
168 {
169 struct rtk_cardbus_softc *csc = device_private(self);
170 struct rtk_softc *sc = &csc->sc_rtk;
171 struct cardbus_attach_args *ca = aux;
172 cardbus_devfunc_t ct = ca->ca_ct;
173 const struct rtk_type *t;
174 bus_addr_t adr;
175
176 sc->sc_dev = self;
177 sc->sc_dmat = ca->ca_dmat;
178 csc->sc_ct = ct;
179 csc->sc_tag = ca->ca_tag;
180
181 t = rtk_cardbus_lookup(ca);
182 if (t == NULL) {
183 aprint_error("\n");
184 panic("%s: impossible", __func__);
185 }
186 aprint_normal(": %s\n", t->rtk_name);
187
188 /*
189 * Power management hooks.
190 */
191 sc->sc_enable = rtk_cardbus_enable;
192 sc->sc_disable = rtk_cardbus_disable;
193
194 /*
195 * Map control/status registers.
196 */
197 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
198 #ifdef RTK_USEIOSPACE
199 if (Cardbus_mapreg_map(ct, RTK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
200 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) {
201 csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
202 csc->sc_bar_reg = RTK_PCI_LOIO;
203 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
204 }
205 #else
206 if (Cardbus_mapreg_map(ct, RTK_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
207 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) {
208 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
209 csc->sc_bar_reg = RTK_PCI_LOMEM;
210 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
211 }
212 #endif
213 else {
214 aprint_error_dev(self, " unable to map deviceregisters\n");
215 return;
216 }
217 /*
218 * Handle power management nonsense and initialize the
219 * configuration registers.
220 */
221 rtk_cardbus_setup(csc);
222
223 rtk_attach(sc);
224
225 if (pmf_device_register(self, NULL, NULL))
226 pmf_class_network_register(self, &sc->ethercom.ec_if);
227 else
228 aprint_error_dev(self, "couldn't establish power handler\n");
229
230 /*
231 * Power down the socket.
232 */
233 Cardbus_function_disable(csc->sc_ct);
234 }
235
236 int
rtk_cardbus_detach(device_t self,int flags)237 rtk_cardbus_detach(device_t self, int flags)
238 {
239 struct rtk_cardbus_softc *csc = device_private(self);
240 struct rtk_softc *sc = &csc->sc_rtk;
241 struct cardbus_devfunc *ct = csc->sc_ct;
242 int rv;
243
244 #ifdef DIAGNOSTIC
245 if (ct == NULL)
246 panic("%s: data structure lacks", device_xname(self));
247 #endif
248 rv = rtk_detach(sc);
249 if (rv)
250 return rv;
251 /*
252 * Unhook the interrupt handler.
253 */
254 if (csc->sc_ih != NULL)
255 Cardbus_intr_disestablish(ct, csc->sc_ih);
256
257 /*
258 * Release bus space and close window.
259 */
260 if (csc->sc_bar_reg != 0)
261 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
262 sc->rtk_btag, sc->rtk_bhandle, sc->rtk_bsize);
263
264 return 0;
265 }
266
267 void
rtk_cardbus_setup(struct rtk_cardbus_softc * csc)268 rtk_cardbus_setup(struct rtk_cardbus_softc *csc)
269 {
270 struct rtk_softc *sc = &csc->sc_rtk;
271 cardbus_devfunc_t ct = csc->sc_ct;
272 cardbus_chipset_tag_t cc = ct->ct_cc;
273 cardbus_function_tag_t cf = ct->ct_cf;
274 pcireg_t reg, command;
275 int pmreg;
276
277 /*
278 * Handle power management nonsense.
279 */
280 if (cardbus_get_capability(cc, cf, csc->sc_tag,
281 PCI_CAP_PWRMGMT, &pmreg, 0)) {
282 command = Cardbus_conf_read(ct, csc->sc_tag,
283 pmreg + PCI_PMCSR);
284 if (command & PCI_PMCSR_STATE_MASK) {
285 pcireg_t iobase, membase, irq;
286
287 /* Save important PCI config data. */
288 iobase = Cardbus_conf_read(ct, csc->sc_tag,
289 RTK_PCI_LOIO);
290 membase = Cardbus_conf_read(ct, csc->sc_tag,
291 RTK_PCI_LOMEM);
292 irq = Cardbus_conf_read(ct, csc->sc_tag,
293 PCI_INTERRUPT_REG);
294
295 /* Reset the power state. */
296 aprint_normal_dev(sc->sc_dev,
297 "chip is in D%d power mode -- setting to D0\n",
298 command & PCI_PMCSR_STATE_MASK);
299 command &= ~PCI_PMCSR_STATE_MASK;
300 Cardbus_conf_write(ct, csc->sc_tag,
301 pmreg + PCI_PMCSR, command);
302
303 /* Restore PCI config data. */
304 Cardbus_conf_write(ct, csc->sc_tag,
305 RTK_PCI_LOIO, iobase);
306 Cardbus_conf_write(ct, csc->sc_tag,
307 RTK_PCI_LOMEM, membase);
308 Cardbus_conf_write(ct, csc->sc_tag,
309 PCI_INTERRUPT_REG, irq);
310 }
311 }
312
313 /* Program the BAR */
314 Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val);
315
316 /* Enable the appropriate bits in the CARDBUS CSR. */
317 reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
318 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
319 reg |= csc->sc_csr;
320 Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
321
322 /*
323 * Make sure the latency timer is set to some reasonable
324 * value.
325 */
326 reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);
327 if (PCI_LATTIMER(reg) < 0x20) {
328 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
329 reg |= (0x20 << PCI_LATTIMER_SHIFT);
330 Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);
331 }
332 }
333
334 int
rtk_cardbus_enable(struct rtk_softc * sc)335 rtk_cardbus_enable(struct rtk_softc *sc)
336 {
337 struct rtk_cardbus_softc *csc = (struct rtk_cardbus_softc *)sc;
338 cardbus_devfunc_t ct = csc->sc_ct;
339
340 /*
341 * Power on the socket.
342 */
343 Cardbus_function_enable(ct);
344
345 /*
346 * Set up the PCI configuration registers.
347 */
348 rtk_cardbus_setup(csc);
349
350 /*
351 * Map and establish the interrupt.
352 */
353 csc->sc_ih = Cardbus_intr_establish(ct, IPL_NET, rtk_intr, sc);
354 if (csc->sc_ih == NULL) {
355 aprint_error_dev(sc->sc_dev,
356 "unable to establish interrupt\n");
357 Cardbus_function_disable(csc->sc_ct);
358 return 1;
359 }
360 return 0;
361 }
362
363 void
rtk_cardbus_disable(struct rtk_softc * sc)364 rtk_cardbus_disable(struct rtk_softc *sc)
365 {
366 struct rtk_cardbus_softc *csc = (struct rtk_cardbus_softc *)sc;
367 cardbus_devfunc_t ct = csc->sc_ct;
368
369 /* Unhook the interrupt handler. */
370 Cardbus_intr_disestablish(ct, csc->sc_ih);
371 csc->sc_ih = NULL;
372
373 /* Power down the socket. */
374 Cardbus_function_disable(ct);
375 }
376