xref: /netbsd-src/sys/arch/sh3/dev/shpcicvar.h (revision 2388feef6162e5f55bc0fbaaa9d32d8dfc8354a3)
1 /*	$NetBSD: shpcicvar.h,v 1.9 2012/01/21 19:44:30 nonaka Exp $	*/
2 
3 /*-
4  * Copyright (C) 2005 NONAKA Kimihiro <nonaka@netbsd.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #ifndef	_SH3_SHPCICVAR_H_
29 #define	_SH3_SHPCICVAR_H_
30 
31 #include <sys/bus.h>
32 
33 bus_space_tag_t shpcic_get_bus_io_tag(void);
34 bus_space_tag_t shpcic_get_bus_mem_tag(void);
35 bus_dma_tag_t shpcic_get_bus_dma_tag(void);
36 
37 int shpcic_bus_maxdevs(void *v, int busno);
38 pcitag_t shpcic_make_tag(void *v, int bus, int device, int function);
39 void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp);
40 pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg);
41 void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data);
42 
43 int shpcic_set_intr_priority(int intr, int level);
44 void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg);
45 void shpcic_intr_disestablish(void *ih);
46 
47 /*
48  * shpcic io/mem bus space
49  */
50 int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags,
51     bus_space_handle_t *bshp);
52 void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size);
53 int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset,
54     bus_size_t size, bus_space_handle_t *nbshp);
55 int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
56     bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
57     bus_addr_t *bpap, bus_space_handle_t *bshp);
58 void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size);
59 paddr_t shpcic_iomem_mmap(void *v, bus_addr_t addr, off_t off, int prot,
60     int flags);
61 
62 /* read single */
63 uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
64 uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
65 uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
66 uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
67 uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
68 uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
69 
70 /* read multi */
71 void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh,
72     bus_size_t offset, uint8_t *addr, bus_size_t count);
73 void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh,
74     bus_size_t offset, uint16_t *addr, bus_size_t count);
75 void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh,
76     bus_size_t offset, uint32_t *addr, bus_size_t count);
77 void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh,
78     bus_size_t offset, uint8_t *addr, bus_size_t count);
79 void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
80     bus_size_t offset, uint16_t *addr, bus_size_t count);
81 void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
82     bus_size_t offset, uint32_t *addr, bus_size_t count);
83 
84 /* read region */
85 void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
86     bus_size_t offset, uint8_t *addr, bus_size_t count);
87 void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh,
88     bus_size_t offset, uint16_t *addr, bus_size_t count);
89 void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh,
90     bus_size_t offset, uint32_t *addr, bus_size_t count);
91 void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh,
92     bus_size_t offset, uint8_t *addr, bus_size_t count);
93 void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
94     bus_size_t offset, uint16_t *addr, bus_size_t count);
95 void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
96     bus_size_t offset, uint32_t *addr, bus_size_t count);
97 
98 /* write single */
99 void shpcic_io_write_1(void *v, bus_space_handle_t bsh,
100     bus_size_t offset, uint8_t data);
101 void shpcic_io_write_2(void *v, bus_space_handle_t bsh,
102     bus_size_t offset, uint16_t data);
103 void shpcic_io_write_4(void *v, bus_space_handle_t bsh,
104     bus_size_t offset, uint32_t data);
105 void shpcic_mem_write_1(void *v, bus_space_handle_t bsh,
106     bus_size_t offset, uint8_t data);
107 void shpcic_mem_write_2(void *v, bus_space_handle_t bsh,
108     bus_size_t offset, uint16_t data);
109 void shpcic_mem_write_4(void *v, bus_space_handle_t bsh,
110     bus_size_t offset, uint32_t data);
111 
112 /* write multi */
113 void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh,
114     bus_size_t offset, const uint8_t *addr, bus_size_t count);
115 void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh,
116     bus_size_t offset, const uint16_t *addr, bus_size_t count);
117 void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh,
118     bus_size_t offset, const uint32_t *addr, bus_size_t count);
119 void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh,
120     bus_size_t offset, const uint8_t *addr, bus_size_t count);
121 void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
122     bus_size_t offset, const uint16_t *addr, bus_size_t count);
123 void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
124     bus_size_t offset, const uint32_t *addr, bus_size_t count);
125 
126 /* write region */
127 void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
128     bus_size_t offset, const uint8_t *addr, bus_size_t count);
129 void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh,
130     bus_size_t offset, const uint16_t *addr, bus_size_t count);
131 void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh,
132     bus_size_t offset, const uint32_t *addr, bus_size_t count);
133 void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh,
134     bus_size_t offset, const uint8_t *addr, bus_size_t count);
135 void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
136     bus_size_t offset, const uint16_t *addr, bus_size_t count);
137 void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
138     bus_size_t offset, const uint32_t *addr, bus_size_t count);
139 
140 /* set multi */
141 void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
142     bus_size_t offset, uint8_t val, bus_size_t count);
143 void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh,
144     bus_size_t offset, uint16_t val, bus_size_t count);
145 void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh,
146     bus_size_t offset, uint32_t val, bus_size_t count);
147 void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh,
148     bus_size_t offset, uint8_t val, bus_size_t count);
149 void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh,
150     bus_size_t offset, uint16_t val, bus_size_t count);
151 void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh,
152     bus_size_t offset, uint32_t val, bus_size_t count);
153 
154 /* set region */
155 void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh,
156     bus_size_t offset, uint8_t val, bus_size_t count);
157 void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh,
158     bus_size_t offset, uint16_t val, bus_size_t count);
159 void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh,
160     bus_size_t offset, uint32_t val, bus_size_t count);
161 void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh,
162     bus_size_t offset, uint8_t val, bus_size_t count);
163 void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh,
164     bus_size_t offset, uint16_t val, bus_size_t count);
165 void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh,
166     bus_size_t offset, uint32_t val, bus_size_t count);
167 
168 /* copy region */
169 void shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1,
170     bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
171     bus_size_t count);
172 void shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1,
173     bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
174     bus_size_t count);
175 void shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1,
176     bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
177     bus_size_t count);
178 void shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1,
179     bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
180     bus_size_t count);
181 void shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1,
182     bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
183     bus_size_t count);
184 void shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1,
185     bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
186     bus_size_t count);
187 
188 #endif	/* _SH3_SHPCICVAR_H_ */
189