xref: /netbsd-src/sys/arch/sandpoint/pci/pci_machdep.c (revision e5548b402ae4c44fb816de42c7bba9581ce23ef5)
1 /*	$NetBSD: pci_machdep.c,v 1.12 2005/12/11 12:18:51 christos Exp $	*/
2 
3 /*
4  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
5  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Charles M. Hannum.
18  * 4. The name of the author may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Machine-specific functions for PCI autoconfiguration.
35  *
36  * On PCs, there are two methods of generating PCI configuration cycles.
37  * We try to detect the appropriate mechanism for this machine and set
38  * up a few function pointers to access the correct method directly.
39  *
40  * The configuration method can be hard-coded in the config file by
41  * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
42  * as defined section 3.6.4.1, `Generating Configuration Cycles'.
43  */
44 
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.12 2005/12/11 12:18:51 christos Exp $");
47 
48 #include "opt_openpic.h"
49 
50 #include <sys/types.h>
51 #include <sys/param.h>
52 #include <sys/device.h>
53 #include <sys/errno.h>
54 #include <sys/extent.h>
55 #include <sys/malloc.h>
56 #include <sys/queue.h>
57 #include <sys/systm.h>
58 #include <sys/time.h>
59 
60 #include <uvm/uvm.h>
61 
62 #define _POWERPC_BUS_DMA_PRIVATE
63 #include <machine/bus.h>
64 #include <machine/pio.h>
65 #include <machine/intr.h>
66 #include <machine/openpicreg.h>
67 
68 #include <dev/isa/isavar.h>
69 #include <dev/pci/pcivar.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pciconf.h>
72 
73 #include <sandpoint/isa/icu.h>
74 
75 struct powerpc_bus_dma_tag pci_bus_dma_tag = {
76 	0,			/* _bounce_thresh */
77 	_bus_dmamap_create,
78 	_bus_dmamap_destroy,
79 	_bus_dmamap_load,
80 	_bus_dmamap_load_mbuf,
81 	_bus_dmamap_load_uio,
82 	_bus_dmamap_load_raw,
83 	_bus_dmamap_unload,
84 	NULL,			/* _dmamap_sync */
85 	_bus_dmamem_alloc,
86 	_bus_dmamem_free,
87 	_bus_dmamem_map,
88 	_bus_dmamem_unmap,
89 	_bus_dmamem_mmap,
90 };
91 
92 #define	PCI_CONFIG_ENABLE	0x80000000UL
93 
94 void
95 pci_attach_hook(parent, self, pba)
96 	struct device *parent, *self;
97 	struct pcibus_attach_args *pba;
98 {
99 }
100 
101 int
102 pci_bus_maxdevs(pc, busno)
103 	pci_chipset_tag_t pc;
104 	int busno;
105 {
106 
107 	/*
108 	 * Bus number is irrelevant.  Configuration Mechanism 1 is in
109 	 * use, can have devices 0-32 (i.e. the `normal' range).
110 	 */
111 	return (32);
112 }
113 
114 pcitag_t
115 pci_make_tag(pc, bus, device, function)
116 	pci_chipset_tag_t pc;
117 	int bus, device, function;
118 {
119 	pcitag_t tag;
120 
121 	if (bus >= 256 || device >= 32 || function >= 8)
122 		panic("pci_make_tag: bad request");
123 
124 	tag = PCI_CONFIG_ENABLE |
125 		    (bus << 16) | (device << 11) | (function << 8);
126 	return tag;
127 }
128 
129 void
130 pci_decompose_tag(pc, tag, bp, dp, fp)
131 	pci_chipset_tag_t pc;
132 	pcitag_t tag;
133 	int *bp, *dp, *fp;
134 {
135 
136 	if (bp != NULL)
137 		*bp = (tag >> 16) & 0xff;
138 	if (dp != NULL)
139 		*dp = (tag >> 11) & 0x1f;
140 	if (fp != NULL)
141 		*fp = (tag >> 8) & 0x7;
142 	return;
143 }
144 
145 /*
146  * The Kahlua documentation says that "reg" should be left-shifted by two
147  * and be in bits 2-7.  Apparently not.  It doesn't work that way, and the
148  * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running
149  * the DINK32 "pcf" command).
150  */
151 #define SP_PCI(tag, reg) ((tag) | (reg))
152 
153 pcireg_t
154 pci_conf_read(pc, tag, reg)
155 	pci_chipset_tag_t pc;
156 	pcitag_t tag;
157 	int reg;
158 {
159 	pcireg_t data;
160 
161 	out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag,reg));
162 	data = in32rb(SANDPOINT_PCI_CONFIG_DATA);
163 	out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
164 	return data;
165 }
166 
167 void
168 pci_conf_write(pc, tag, reg, data)
169 	pci_chipset_tag_t pc;
170 	pcitag_t tag;
171 	int reg;
172 	pcireg_t data;
173 {
174 	out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag, reg));
175 	out32rb(SANDPOINT_PCI_CONFIG_DATA, data);
176 	out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
177 }
178 
179 int
180 pci_intr_map(pa, ihp)
181 	struct pci_attach_args *pa;
182 	pci_intr_handle_t *ihp;
183 {
184 	int	pin = pa->pa_intrpin;
185 	int	line = pa->pa_intrline;
186 
187 	if (pin == 0) {
188 		/* No IRQ used. */
189 		goto bad;
190 	}
191 
192 	if (pin > 4) {
193 		printf("pci_intr_map: bad interrupt pin %d\n", pin);
194 		goto bad;
195 	}
196 
197 	/*
198 	 * Section 6.2.4, `Miscellaneous Functions', says that 255 means
199 	 * `unknown' or `no connection' on a PC.  We assume that a device with
200 	 * `no connection' either doesn't have an interrupt (in which case the
201 	 * pin number should be 0, and would have been noticed above), or
202 	 * wasn't configured by the BIOS (in which case we punt, since there's
203 	 * no real way we can know how the interrupt lines are mapped in the
204 	 * hardware).
205 	 *
206 	 * XXX
207 	 * Since IRQ 0 is only used by the clock, and we can't actually be sure
208 	 * that the BIOS did its job, we also recognize that as meaning that
209 	 * the BIOS has not configured the device.
210 	 */
211 	if (line == 255) {
212 		printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
213 		goto bad;
214 	}
215 #if defined(OPENPIC_SERIAL_MODE)
216 	if (line == 11) {
217 		switch (pin) {
218 		case PCI_INTERRUPT_PIN_A:
219 			*ihp = SANDPOINT_INTR_WINBOND_A;
220 			break;
221 		case PCI_INTERRUPT_PIN_B:
222 			*ihp = SANDPOINT_INTR_WINBOND_B;
223 			break;
224 		case PCI_INTERRUPT_PIN_C:
225 			*ihp = SANDPOINT_INTR_WINBOND_C;
226 			break;
227 		case PCI_INTERRUPT_PIN_D:
228 			*ihp = SANDPOINT_INTR_WINBOND_D;
229 			break;
230 		default:
231 			printf("pci_intr_map: bad interrupt line %d,%c\n",
232 				line, pin + '@');
233 			goto bad;
234 			break;
235 		}
236 			*ihp = SANDPOINT_INTR_WINBOND_C;
237 	} else {
238 #else
239 	if (1) {
240 #endif
241 		/*
242 		 * Sandpoint has 4 PCI slots.
243 		 * Sandpoint rev. X2 has them in a weird order.  Counting
244 		 * from center out toward the edge, we have:
245 		 * 	Slot 1 (dev 14?) (labelled 1)
246 		 * 	Slot 0 (dev 13?) (labelled 2)
247 		 * 	Slot 3 (dev 16)  (labelled 3)
248 		 * 	Slot 2 (dev 15)  (labelled 4)
249 		 * To keep things confusing, we will consistently use a zero-
250 		 * based numbering scheme where Motorola's is usually 1-based.
251 		 */
252 		if (line < 13 || line > 16) {
253 			printf("pci_intr_map: bad interrupt line %d,%c\n",
254 				line, pin + '@');
255 			goto bad;
256 		}
257 
258 		/*
259 		 * In the PCI configuration code, we simply assign the dev
260 		 * number to the interrupt line.  We extract it here for the
261 		 * interrupt, but subtract off the lowest dev (13) to get
262 		 * the IRQ.
263 		 */
264 #if defined(OPENPIC_SERIAL_MODE)
265 		*ihp = line - 11;
266 #else
267 		*ihp = line - 13;
268 #endif
269 	}
270 	return 0;
271 
272 bad:
273 	*ihp = -1;
274 	return 1;
275 }
276 
277 const char *
278 pci_intr_string(pc, ih)
279 	pci_chipset_tag_t pc;
280 	pci_intr_handle_t ih;
281 {
282 	static char irqstr[8];		/* 4 + 2 + NULL + sanity */
283 
284 	if (ih < 0 || ih >= ICU_LEN)
285 		panic("pci_intr_string: bogus handle 0x%x", ih);
286 
287 	sprintf(irqstr, "irq %d", ih);
288 	return (irqstr);
289 
290 }
291 
292 const struct evcnt *
293 pci_intr_evcnt(pc, ih)
294 	pci_chipset_tag_t pc;
295 	pci_intr_handle_t ih;
296 {
297 
298 	/* XXX for now, no evcnt parent reported */
299 	return NULL;
300 }
301 
302 void *
303 pci_intr_establish(pc, ih, level, func, arg)
304 	pci_chipset_tag_t pc;
305 	pci_intr_handle_t ih;
306 	int level, (*func) __P((void *));
307 	void *arg;
308 {
309 #if 0
310 	if (ih < SANDPOINT_INTR_PCI0 || ih > SANDPOINT_INTR_PCI3)
311 		panic("pci_intr_establish: bogus handle 0x%x", ih);
312 #endif
313 
314 	/*
315 	 * ih is the value assigned in pci_intr_map(), above.
316 	 * For the Sandpoint, this is the zero-based slot #,
317 	 * configured when the bus is set up.
318 	 */
319 	return intr_establish(ih, IST_LEVEL, level, func, arg);
320 }
321 
322 void
323 pci_intr_disestablish(pc, cookie)
324 	pci_chipset_tag_t pc;
325 	void *cookie;
326 {
327 	intr_disestablish(cookie);
328 }
329 
330 void
331 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
332     int *iline)
333 {
334 	if (bus == 0) {
335 		*iline = dev;
336 	} else {
337 		/*
338 		 * If we are not on bus zero, we're behind a bridge, so we
339 		 * swizzle.
340 		 *
341 		 * The documentation lies about this.  In slot 3 (numbering
342 		 * from 0) aka device 16, INTD# becomes an interrupt for
343 		 * slot 2.  INTC# becomes an interrupt for slot 1, etc.
344 		 * In slot 2 aka device 16, INTD# becomes an interrupt for
345 		 * slot 1, etc.
346 		 *
347 		 * Verified for INTD# on device 16, INTC# on device 16,
348 		 * INTD# on device 15, INTD# on device 13, and INTC# on
349 		 * device 14.  I presume that the rest follow the same
350 		 * pattern.
351 		 *
352 		 * Slot 0 is device 13, and is the base for the rest.
353 		 */
354 		*iline = 13 + ((swiz + dev + 3) & 3);
355 	}
356 }
357