1 /* $NetBSD: pci_machdep.c,v 1.38 2023/12/20 15:29:06 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Machine-specific functions for PCI autoconfiguration.
35 *
36 * On PCs, there are two methods of generating PCI configuration cycles.
37 * We try to detect the appropriate mechanism for this machine and set
38 * up a few function pointers to access the correct method directly.
39 *
40 * The configuration method can be hard-coded in the config file by
41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
42 * as defined section 3.6.4.1, `Generating Configuration Cycles'.
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.38 2023/12/20 15:29:06 thorpej Exp $");
47
48 #include "opt_pci.h"
49
50 #include <sys/types.h>
51 #include <sys/param.h>
52 #include <sys/device.h>
53 #include <sys/errno.h>
54 #include <sys/extent.h>
55 #include <sys/kmem.h>
56 #include <sys/queue.h>
57 #include <sys/systm.h>
58 #include <sys/time.h>
59
60 #define _POWERPC_BUS_DMA_PRIVATE
61 #include <sys/bus.h>
62 #include <machine/intr.h>
63 #include <machine/pio.h>
64
65 #include <dev/isa/isavar.h>
66 #include <dev/pci/pcivar.h>
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pciconf.h>
69 #include <dev/pci/pcidevs.h>
70
71 struct powerpc_bus_dma_tag pci_bus_dma_tag = {
72 0, /* _bounce_thresh */
73 _bus_dmamap_create,
74 _bus_dmamap_destroy,
75 _bus_dmamap_load,
76 _bus_dmamap_load_mbuf,
77 _bus_dmamap_load_uio,
78 _bus_dmamap_load_raw,
79 _bus_dmamap_unload,
80 NULL, /* _dmamap_sync */
81 _bus_dmamem_alloc,
82 _bus_dmamem_free,
83 _bus_dmamem_map,
84 _bus_dmamem_unmap,
85 _bus_dmamem_mmap,
86 };
87
88 /*#define EPIC_DEBUGIRQ*/
89
90 static int brdtype;
91 #define BRD_SANDPOINTX2 2
92 #define BRD_SANDPOINTX3 3
93 #define BRD_ENCOREPP1 10
94 #define BRD_KUROBOX 100
95 #define BRD_QNAPTS 101
96 #define BRD_SYNOLOGY 102
97 #define BRD_STORCENTER 103
98 #define BRD_DLINKDSM 104
99 #define BRD_NH230NAS 105
100 #define BRD_UNKNOWN -1
101
102 #define PCI_CONFIG_ENABLE 0x80000000UL
103
104 void
pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)105 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba)
106 {
107 pcitag_t tag;
108 pcireg_t dev11, dev22, dev15, dev13, dev16;
109
110 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0);
111 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG);
112 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) {
113 /* WinBond/Symphony Lab 83C553 at dev 11 */
114 /*
115 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6.
116 * XXX SP3 #7 output values loopback to #6 input.
117 */
118 brdtype = BRD_SANDPOINTX3;
119 return;
120 }
121 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0);
122 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG);
123 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) {
124 /* VIA 82C686B at dev 22 */
125 brdtype = BRD_ENCOREPP1;
126 return;
127 }
128 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0);
129 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG);
130 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) {
131 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */
132 brdtype = BRD_KUROBOX;
133 return;
134 }
135 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0);
136 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG);
137 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) {
138 /* Marvell GbE at dev 15 */
139 brdtype = BRD_SYNOLOGY;
140 return;
141 }
142 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 13, 0);
143 dev13 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG);
144 if (PCI_VENDOR(dev13) == PCI_VENDOR_VIATECH) {
145 /* VIA 6410 PCIIDE at dev 13 */
146 brdtype = BRD_STORCENTER;
147 return;
148 }
149 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 16, 0);
150 dev16 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG);
151 if (PCI_VENDOR(dev16) == PCI_VENDOR_ACARD) {
152 /* ACARD ATP865 at dev 16 */
153 brdtype = BRD_DLINKDSM;
154 return;
155 }
156 if (PCI_VENDOR(dev16) == PCI_VENDOR_ITE
157 || PCI_VENDOR(dev16) == PCI_VENDOR_CMDTECH) {
158 brdtype = BRD_NH230NAS;
159 return;
160 }
161 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL
162 || PCI_VENDOR(dev15) == PCI_VENDOR_REALTEK) {
163 /* Intel or Realtek GbE at dev 15 */
164 brdtype = BRD_QNAPTS;
165 return;
166 }
167
168 brdtype = BRD_UNKNOWN;
169 }
170
171 int
pci_bus_maxdevs(pci_chipset_tag_t pc,int busno)172 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
173 {
174
175 return 32;
176 }
177
178 pcitag_t
pci_make_tag(pci_chipset_tag_t pc,int bus,int device,int function)179 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
180 {
181 pcitag_t tag;
182
183 if (bus >= 256 || device >= 32 || function >= 8)
184 panic("pci_make_tag: bad request");
185
186 tag = PCI_CONFIG_ENABLE |
187 (bus << 16) | (device << 11) | (function << 8);
188 return tag;
189 }
190
191 void
pci_decompose_tag(pci_chipset_tag_t pc,pcitag_t tag,int * bp,int * dp,int * fp)192 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
193 int *bp, int *dp, int *fp)
194 {
195
196 if (bp != NULL)
197 *bp = (tag >> 16) & 0xff;
198 if (dp != NULL)
199 *dp = (tag >> 11) & 0x1f;
200 if (fp != NULL)
201 *fp = (tag >> 8) & 0x7;
202 return;
203 }
204
205 /*
206 * The Kahlua documentation says that "reg" should be left-shifted by two
207 * and be in bits 2-7. Apparently not. It doesn't work that way, and the
208 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running
209 * the DINK32 "pcf" command).
210 */
211 pcireg_t
pci_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)212 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
213 {
214 pcireg_t data;
215
216 if ((unsigned int)reg >= PCI_CONF_SIZE)
217 return (pcireg_t) -1;
218
219 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);
220 data = in32rb(SANDPOINT_PCI_CONFIG_DATA);
221 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
222 return data;
223 }
224
225 void
pci_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)226 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
227 {
228
229 if ((unsigned int)reg >= PCI_CONF_SIZE)
230 return;
231
232 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);
233 out32rb(SANDPOINT_PCI_CONFIG_DATA, data);
234 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
235 }
236
237 int
pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)238 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
239 {
240 int pin = pa->pa_intrpin;
241 int line = pa->pa_intrline;
242
243 /* No IRQ used. */
244 if (pin == 0)
245 goto bad;
246 if (pin > 4) {
247 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin);
248 goto bad;
249 }
250
251 /*
252 * Section 6.2.4, `Miscellaneous Functions', says that 255 means
253 * `unknown' or `no connection' on a PC. We assume that a device with
254 * `no connection' either doesn't have an interrupt (in which case the
255 * pin number should be 0, and would have been noticed above), or
256 * wasn't configured by the BIOS (in which case we punt, since there's
257 * no real way we can know how the interrupt lines are mapped in the
258 * hardware).
259 *
260 * XXX
261 * Since IRQ 0 is only used by the clock, and we can't actually be sure
262 * that the BIOS did its job, we also recognize that as meaning that
263 * the BIOS has not configured the device.
264 */
265 if (line == 255) {
266 aprint_error("pci_intr_map: no mapping for pin %c\n",
267 '@' + pin);
268 goto bad;
269 }
270 #ifdef EPIC_DEBUGIRQ
271 printf("line %d, pin %c", line, pin + '@');
272 #endif
273 switch (brdtype) {
274 /* Sandpoint has 4 PCI slots in a weird order.
275 * From next to MPMC mezzanine card toward the board edge,
276 * 64bit slot PCI AD14
277 * 64bit slot PCI AD13
278 * 32bit slot PCI AD16
279 * 32bit slot PCI AD15
280 * Don't believe identifying labels printed on PCB and
281 * documents confusing as well since Moto names the slots
282 * as number 1 origin.
283 */
284 case BRD_SANDPOINTX3:
285 /*
286 * Sandpoint X3 brd uses EPIC serial mode IRQ.
287 * - i8259 PIC interrupt to EPIC IRQ0.
288 * - WinBond IDE PCI C/D to EPIC IRQ8/9.
289 * - PCI AD13 pin A to EPIC IRQ2.
290 * - PCI AD14 pin A to EPIC IRQ3.
291 * - PCI AD15 pin A to EPIC IRQ4.
292 * - PCI AD16 pin A to EPIC IRQ5.
293 */
294 if (line == 11
295 && pa->pa_function == 1 && pa->pa_bus == 0) {
296 /* X3 wires 83c553 pin C,D to EPIC IRQ8,9 */
297 *ihp = 8; /* pin C only, indeed */
298 break;
299 }
300 if (line < 13 || line > 16) {
301 aprint_error("pci_intr_map: bad interrupt line %d,%c\n",
302 line, pin + '@');
303 goto bad;
304 }
305 line -= 13; /* B/C/D is not available */
306 *ihp = 2 + line;
307 break;
308 case BRD_SANDPOINTX2:
309 /*
310 * Sandpoint X2 brd uses EPIC direct mode IRQ.
311 * - i8259 PIC interrupt EPIC IRQ2.
312 * - PCI AD13 pin A,B,C,D to EPIC IRQ0,1,2,3.
313 * - PCI AD14 pin A,B,C,D to EPIC IRQ1,2,3,0.
314 * - PCI AD15 pin A,B,C,D to EPIC IRQ2,3,0,1.
315 * - PCI AD16 pin A,B,C,D to EPIC IRQ3,0,1,2.
316 * - PCI AD12 is wired to PMPC device itself.
317 */
318 if (line == 11
319 && pa->pa_function == 1 && pa->pa_bus == 0) {
320 /* 83C553 PCI IDE comes thru EPIC IRQ2 */
321 *ihp = 2;
322 break;
323 }
324 if (line < 13 || line > 16) {
325 aprint_error("pci_intr_map: bad interrupt line %d,%c\n",
326 line, pin + '@');
327 goto bad;
328 }
329 line -= 13; pin -= 1;
330 *ihp = (line + pin) & 03;
331 break;
332 case BRD_ENCOREPP1:
333 /*
334 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ.
335 * PDF says VIA 686B SB i8259 interrupt goes through EPC IRQ0,
336 * while PCI pin A-D are tied with EPIC IRQ1-4.
337 *
338 * It mentions i82559 is at AD24, however, found at AD25 instead.
339 * Heuristics show that i82559 responds to EPIC 2 (!). Then we
340 * decided to return EPIC 2 here since i82559 is the only one PCI
341 * device ENCPP1 can have;
342 */
343 if (pa->pa_device != 25)
344 goto bad; /* eeh !? */
345 *ihp = 2;
346 break;
347 case BRD_KUROBOX:
348 /* map line 11,12,13,14 to EPIC IRQ 0,1,4,3 */
349 *ihp = (line == 13) ? 4 : line - 11;
350 break;
351 case BRD_QNAPTS:
352 /* map line 13-16 to EPIC IRQ0-3 */
353 *ihp = line - 13;
354 break;
355 case BRD_SYNOLOGY:
356 /* map line 12,13-15 to EPIC IRQ 4,0-2 */
357 *ihp = (line == 12) ? 4 : line - 13;
358 break;
359 case BRD_DLINKDSM:
360 /* map line 13,14A,14B,14C,15,16 to EPIC IRQ 0,1,1,2,3,4 */
361 *ihp = (line < 15) ? line - 13 : line - 12;
362 if (line == 14 && pin == 3)
363 *ihp += 1; /* USB pin C (EHCI) uses next IRQ */
364 break;
365 case BRD_NH230NAS:
366 /* map line 13,14,15,16 to EPIC IRQ0,3,1,2 */
367 *ihp = (line == 16) ? 2 :
368 (line == 15) ? 1 :
369 (line == 14) ? 3 : 0;
370 break;
371 case BRD_STORCENTER:
372 /* map line 13,14A,14B,14C,15 to EPIC IRQ 1,2,3,4,0 */
373 *ihp = (line == 15) ? 0 :
374 (line == 13) ? 1 : 1 + pin;
375 break;
376 default:
377 /* simply map line 12-15 to EPIC IRQ0-3 */
378 *ihp = line - 12;
379 #if defined(DIAGNOSTIC) || defined(DEBUG)
380 printf("pci_intr_map: line %d, pin %c for unknown board"
381 " mapped to irq %d\n", line, pin + '@', *ihp);
382 #endif
383 break;
384 }
385 #ifdef EPIC_DEBUGIRQ
386 printf(" = EPIC %d\n", *ihp);
387 #endif
388 return 0;
389 bad:
390 *ihp = -1;
391 return 1;
392 }
393
394 const char *
pci_intr_string(pci_chipset_tag_t pc,pci_intr_handle_t ih,char * buf,size_t len)395 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf,
396 size_t len)
397 {
398 if (ih < 0 || ih >= OPENPIC_ICU)
399 panic("pci_intr_string: bogus handle 0x%x", ih);
400
401 snprintf(buf, len, "irq %d", ih + I8259_ICU);
402 return buf;
403
404 }
405
406 const struct evcnt *
pci_intr_evcnt(pci_chipset_tag_t pc,pci_intr_handle_t ih)407 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
408 {
409
410 /* XXX for now, no evcnt parent reported */
411 return NULL;
412 }
413
414 int
pci_intr_setattr(pci_chipset_tag_t pc,pci_intr_handle_t * ih,int attr,uint64_t data)415 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
416 int attr, uint64_t data)
417 {
418
419 switch (attr) {
420 case PCI_INTR_MPSAFE:
421 return 0;
422 default:
423 return ENODEV;
424 }
425 }
426
427 void *
pci_intr_establish(pci_chipset_tag_t pc,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg)428 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
429 int (*func)(void *), void *arg)
430 {
431
432 return pci_intr_establish_xname(pc, ih, level, func, arg, NULL);
433 }
434
435 void *
pci_intr_establish_xname(pci_chipset_tag_t pc,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg,const char * xname)436 pci_intr_establish_xname(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
437 int (*func)(void *), void *arg, const char *xname)
438 {
439 int type;
440
441 if (brdtype == BRD_STORCENTER && ih == 1) {
442 /*
443 * XXX This is a workaround for the VT6410 IDE controller!
444 * Apparently its interrupt cannot be disabled and remains
445 * asserted during the whole device probing procedure,
446 * causing an interrupt storm.
447 * Using an edge-trigger fixes that and triggers the
448 * interrupt only once during probing.
449 */
450 type = IST_EDGE;
451 } else
452 type = IST_LEVEL;
453
454 /*
455 * ih is the value assigned in pci_intr_map(), above.
456 * It's the EPIC IRQ #.
457 */
458 return intr_establish_xname(ih + I8259_ICU, type, level, func, arg,
459 xname);
460 }
461
462 void
pci_intr_disestablish(pci_chipset_tag_t pc,void * cookie)463 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
464 {
465
466 intr_disestablish(cookie);
467 }
468
469 #if defined(PCI_NETBSD_CONFIGURE)
470 void
pci_conf_interrupt(pci_chipset_tag_t pc,int bus,int dev,int pin,int swiz,int * iline)471 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev,
472 int pin, int swiz, int *iline)
473 {
474 if (bus == 0) {
475 *iline = dev;
476 } else {
477 /*
478 * If we are not on bus zero, we're behind a bridge, so we
479 * swizzle.
480 *
481 * The documentation lies about this. In slot 3 (numbering
482 * from 0) aka device 16, INTD# becomes an interrupt for
483 * slot 2. INTC# becomes an interrupt for slot 1, etc.
484 * In slot 2 aka device 16, INTD# becomes an interrupt for
485 * slot 1, etc.
486 *
487 * Verified for INTD# on device 16, INTC# on device 16,
488 * INTD# on device 15, INTD# on device 13, and INTC# on
489 * device 14. I presume that the rest follow the same
490 * pattern.
491 *
492 * Slot 0 is device 13, and is the base for the rest.
493 */
494 *iline = 13 + ((swiz + dev + 3) & 3);
495 }
496 }
497 #endif
498
499 pci_intr_type_t
pci_intr_type(pci_chipset_tag_t pc,pci_intr_handle_t ih)500 pci_intr_type(pci_chipset_tag_t pc, pci_intr_handle_t ih)
501 {
502
503 return PCI_INTR_TYPE_INTX;
504 }
505
506 int
pci_intr_alloc(const struct pci_attach_args * pa,pci_intr_handle_t ** ihps,int * counts,pci_intr_type_t max_type)507 pci_intr_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
508 int *counts, pci_intr_type_t max_type)
509 {
510
511 if (counts != NULL && counts[PCI_INTR_TYPE_INTX] == 0)
512 return EINVAL;
513
514 return pci_intx_alloc(pa, ihps);
515 }
516
517 void
pci_intr_release(pci_chipset_tag_t pc,pci_intr_handle_t * pih,int count)518 pci_intr_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih, int count)
519 {
520
521 kmem_free(pih, sizeof(*pih));
522 }
523
524 int
pci_intx_alloc(const struct pci_attach_args * pa,pci_intr_handle_t ** ihpp)525 pci_intx_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihpp)
526 {
527 pci_intr_handle_t *ihp;
528
529 ihp = kmem_alloc(sizeof(*ihp), KM_SLEEP);
530 if (pci_intr_map(pa, ihp)) {
531 kmem_free(ihp, sizeof(*ihp));
532 return EINVAL;
533 }
534
535 *ihpp = ihp;
536 return 0;
537 }
538
539 /* experimental MSI support */
540 int
pci_msi_alloc(const struct pci_attach_args * pa,pci_intr_handle_t ** ihps,int * count)541 pci_msi_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
542 int *count)
543 {
544
545 return EOPNOTSUPP;
546 }
547
548 int
pci_msi_alloc_exact(const struct pci_attach_args * pa,pci_intr_handle_t ** ihps,int count)549 pci_msi_alloc_exact(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
550 int count)
551 {
552
553 return EOPNOTSUPP;
554 }
555
556 /* experimental MSI-X support */
557 int
pci_msix_alloc(const struct pci_attach_args * pa,pci_intr_handle_t ** ihps,int * count)558 pci_msix_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
559 int *count)
560 {
561
562 return EOPNOTSUPP;
563 }
564
565 int
pci_msix_alloc_exact(const struct pci_attach_args * pa,pci_intr_handle_t ** ihps,int count)566 pci_msix_alloc_exact(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
567 int count)
568 {
569
570 return EOPNOTSUPP;
571 }
572
573 int
pci_msix_alloc_map(const struct pci_attach_args * pa,pci_intr_handle_t ** ihps,u_int * table_indexes,int count)574 pci_msix_alloc_map(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
575 u_int *table_indexes, int count)
576 {
577
578 return EOPNOTSUPP;
579 }
580