1 /* $NetBSD: pci_machdep.c,v 1.33 2014/03/29 19:28:30 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.33 2014/03/29 19:28:30 christos Exp $"); 47 48 #include "opt_pci.h" 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/extent.h> 55 #include <sys/malloc.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 60 #define _POWERPC_BUS_DMA_PRIVATE 61 #include <sys/bus.h> 62 #include <machine/intr.h> 63 #include <machine/pio.h> 64 65 #include <dev/isa/isavar.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pciconf.h> 69 #include <dev/pci/pcidevs.h> 70 71 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 72 0, /* _bounce_thresh */ 73 _bus_dmamap_create, 74 _bus_dmamap_destroy, 75 _bus_dmamap_load, 76 _bus_dmamap_load_mbuf, 77 _bus_dmamap_load_uio, 78 _bus_dmamap_load_raw, 79 _bus_dmamap_unload, 80 NULL, /* _dmamap_sync */ 81 _bus_dmamem_alloc, 82 _bus_dmamem_free, 83 _bus_dmamem_map, 84 _bus_dmamem_unmap, 85 _bus_dmamem_mmap, 86 }; 87 88 /*#define EPIC_DEBUGIRQ*/ 89 90 static int brdtype; 91 #define BRD_SANDPOINTX2 2 92 #define BRD_SANDPOINTX3 3 93 #define BRD_ENCOREPP1 10 94 #define BRD_KUROBOX 100 95 #define BRD_QNAPTS 101 96 #define BRD_SYNOLOGY 102 97 #define BRD_STORCENTER 103 98 #define BRD_DLINKDSM 104 99 #define BRD_NH230NAS 105 100 #define BRD_UNKNOWN -1 101 102 #define PCI_CONFIG_ENABLE 0x80000000UL 103 104 void 105 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 106 { 107 pcitag_t tag; 108 pcireg_t dev11, dev22, dev15, dev13, dev16; 109 110 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 111 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 112 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 113 /* WinBond/Symphony Lab 83C553 at dev 11 */ 114 /* 115 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 116 * XXX SP3 #7 output values loopback to #6 input. 117 */ 118 brdtype = BRD_SANDPOINTX3; 119 return; 120 } 121 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 122 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 123 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 124 /* VIA 82C686B at dev 22 */ 125 brdtype = BRD_ENCOREPP1; 126 return; 127 } 128 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 129 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 130 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 131 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 132 brdtype = BRD_KUROBOX; 133 return; 134 } 135 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 136 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 137 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 138 /* Marvell GbE at dev 15 */ 139 brdtype = BRD_SYNOLOGY; 140 return; 141 } 142 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 13, 0); 143 dev13 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 144 if (PCI_VENDOR(dev13) == PCI_VENDOR_VIATECH) { 145 /* VIA 6410 PCIIDE at dev 13 */ 146 brdtype = BRD_STORCENTER; 147 return; 148 } 149 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 16, 0); 150 dev16 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 151 if (PCI_VENDOR(dev16) == PCI_VENDOR_ACARD) { 152 /* ACARD ATP865 at dev 16 */ 153 brdtype = BRD_DLINKDSM; 154 return; 155 } 156 if (PCI_VENDOR(dev16) == PCI_VENDOR_ITE 157 || PCI_VENDOR(dev16) == PCI_VENDOR_CMDTECH) { 158 brdtype = BRD_NH230NAS; 159 return; 160 } 161 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL 162 || PCI_VENDOR(dev15) == PCI_VENDOR_REALTEK) { 163 /* Intel or Realtek GbE at dev 15 */ 164 brdtype = BRD_QNAPTS; 165 return; 166 } 167 168 brdtype = BRD_UNKNOWN; 169 } 170 171 int 172 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 173 { 174 175 return 32; 176 } 177 178 pcitag_t 179 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 180 { 181 pcitag_t tag; 182 183 if (bus >= 256 || device >= 32 || function >= 8) 184 panic("pci_make_tag: bad request"); 185 186 tag = PCI_CONFIG_ENABLE | 187 (bus << 16) | (device << 11) | (function << 8); 188 return tag; 189 } 190 191 void 192 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 193 int *bp, int *dp, int *fp) 194 { 195 196 if (bp != NULL) 197 *bp = (tag >> 16) & 0xff; 198 if (dp != NULL) 199 *dp = (tag >> 11) & 0x1f; 200 if (fp != NULL) 201 *fp = (tag >> 8) & 0x7; 202 return; 203 } 204 205 /* 206 * The Kahlua documentation says that "reg" should be left-shifted by two 207 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 208 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 209 * the DINK32 "pcf" command). 210 */ 211 pcireg_t 212 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 213 { 214 pcireg_t data; 215 216 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 217 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 218 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 219 return data; 220 } 221 222 void 223 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 224 { 225 226 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 227 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 228 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 229 } 230 231 int 232 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 233 { 234 int pin = pa->pa_intrpin; 235 int line = pa->pa_intrline; 236 237 /* No IRQ used. */ 238 if (pin == 0) 239 goto bad; 240 if (pin > 4) { 241 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin); 242 goto bad; 243 } 244 245 /* 246 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 247 * `unknown' or `no connection' on a PC. We assume that a device with 248 * `no connection' either doesn't have an interrupt (in which case the 249 * pin number should be 0, and would have been noticed above), or 250 * wasn't configured by the BIOS (in which case we punt, since there's 251 * no real way we can know how the interrupt lines are mapped in the 252 * hardware). 253 * 254 * XXX 255 * Since IRQ 0 is only used by the clock, and we can't actually be sure 256 * that the BIOS did its job, we also recognize that as meaning that 257 * the BIOS has not configured the device. 258 */ 259 if (line == 255) { 260 aprint_error("pci_intr_map: no mapping for pin %c\n", 261 '@' + pin); 262 goto bad; 263 } 264 #ifdef EPIC_DEBUGIRQ 265 printf("line %d, pin %c", line, pin + '@'); 266 #endif 267 switch (brdtype) { 268 /* Sandpoint has 4 PCI slots in a weird order. 269 * From next to MPMC mezzanine card toward the board edge, 270 * 64bit slot PCI AD14 271 * 64bit slot PCI AD13 272 * 32bit slot PCI AD16 273 * 32bit slot PCI AD15 274 * Don't believe identifying labels printed on PCB and 275 * documents confusing as well since Moto names the slots 276 * as number 1 origin. 277 */ 278 case BRD_SANDPOINTX3: 279 /* 280 * Sandpoint X3 brd uses EPIC serial mode IRQ. 281 * - i8259 PIC interrupt to EPIC IRQ0. 282 * - WinBond IDE PCI C/D to EPIC IRQ8/9. 283 * - PCI AD13 pin A to EPIC IRQ2. 284 * - PCI AD14 pin A to EPIC IRQ3. 285 * - PCI AD15 pin A to EPIC IRQ4. 286 * - PCI AD16 pin A to EPIC IRQ5. 287 */ 288 if (line == 11 289 && pa->pa_function == 1 && pa->pa_bus == 0) { 290 /* X3 wires 83c553 pin C,D to EPIC IRQ8,9 */ 291 *ihp = 8; /* pin C only, indeed */ 292 break; 293 } 294 if (line < 13 || line > 16) { 295 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 296 line, pin + '@'); 297 goto bad; 298 } 299 line -= 13; /* B/C/D is not available */ 300 *ihp = 2 + line; 301 break; 302 case BRD_SANDPOINTX2: 303 /* 304 * Sandpoint X2 brd uses EPIC direct mode IRQ. 305 * - i8259 PIC interrupt EPIC IRQ2. 306 * - PCI AD13 pin A,B,C,D to EPIC IRQ0,1,2,3. 307 * - PCI AD14 pin A,B,C,D to EPIC IRQ1,2,3,0. 308 * - PCI AD15 pin A,B,C,D to EPIC IRQ2,3,0,1. 309 * - PCI AD16 pin A,B,C,D to EPIC IRQ3,0,1,2. 310 * - PCI AD12 is wired to PMPC device itself. 311 */ 312 if (line == 11 313 && pa->pa_function == 1 && pa->pa_bus == 0) { 314 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 315 *ihp = 2; 316 break; 317 } 318 if (line < 13 || line > 16) { 319 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 320 line, pin + '@'); 321 goto bad; 322 } 323 line -= 13; pin -= 1; 324 *ihp = (line + pin) & 03; 325 break; 326 case BRD_ENCOREPP1: 327 /* 328 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. 329 * PDF says VIA 686B SB i8259 interrupt goes through EPC IRQ0, 330 * while PCI pin A-D are tied with EPIC IRQ1-4. 331 * 332 * It mentions i82559 is at AD24, however, found at AD25 instead. 333 * Heuristics show that i82559 responds to EPIC 2 (!). Then we 334 * decided to return EPIC 2 here since i82559 is the only one PCI 335 * device ENCPP1 can have; 336 */ 337 if (pa->pa_device != 25) 338 goto bad; /* eeh !? */ 339 *ihp = 2; 340 break; 341 case BRD_KUROBOX: 342 /* map line 11,12,13,14 to EPIC IRQ 0,1,4,3 */ 343 *ihp = (line == 13) ? 4 : line - 11; 344 break; 345 case BRD_QNAPTS: 346 /* map line 13-16 to EPIC IRQ0-3 */ 347 *ihp = line - 13; 348 break; 349 case BRD_SYNOLOGY: 350 /* map line 12,13-15 to EPIC IRQ 4,0-2 */ 351 *ihp = (line == 12) ? 4 : line - 13; 352 break; 353 case BRD_DLINKDSM: 354 /* map line 13,14A,14B,14C,15,16 to EPIC IRQ 0,1,1,2,3,4 */ 355 *ihp = (line < 15) ? line - 13 : line - 12; 356 if (line == 14 && pin == 3) 357 *ihp += 1; /* USB pin C (EHCI) uses next IRQ */ 358 break; 359 case BRD_NH230NAS: 360 /* map line 13,14,15,16 to EPIC IRQ0,3,1,2 */ 361 *ihp = (line == 16) ? 2 : 362 (line == 15) ? 1 : 363 (line == 14) ? 3 : 0; 364 break; 365 case BRD_STORCENTER: 366 /* map line 13,14A,14B,14C,15 to EPIC IRQ 1,2,3,4,0 */ 367 *ihp = (line == 15) ? 0 : 368 (line == 13) ? 1 : 1 + pin; 369 break; 370 default: 371 /* simply map line 12-15 to EPIC IRQ0-3 */ 372 *ihp = line - 12; 373 #if defined(DIAGNOSTIC) || defined(DEBUG) 374 printf("pci_intr_map: line %d, pin %c for unknown board" 375 " mapped to irq %d\n", line, pin + '@', *ihp); 376 #endif 377 break; 378 } 379 #ifdef EPIC_DEBUGIRQ 380 printf(" = EPIC %d\n", *ihp); 381 #endif 382 return 0; 383 bad: 384 *ihp = -1; 385 return 1; 386 } 387 388 const char * 389 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 390 size_t len) 391 { 392 if (ih < 0 || ih >= OPENPIC_ICU) 393 panic("pci_intr_string: bogus handle 0x%x", ih); 394 395 snprintf(buf, len, "irq %d", ih + I8259_ICU); 396 return buf; 397 398 } 399 400 const struct evcnt * 401 pci_intr_evcnt(void *v, pci_intr_handle_t ih) 402 { 403 404 /* XXX for now, no evcnt parent reported */ 405 return NULL; 406 } 407 408 int 409 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 410 int attr, uint64_t data) 411 { 412 413 switch (attr) { 414 case PCI_INTR_MPSAFE: 415 return 0; 416 default: 417 return ENODEV; 418 } 419 } 420 421 void * 422 pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 423 int (*func)(void *), void *arg) 424 { 425 int type; 426 427 if (brdtype == BRD_STORCENTER && ih == 1) { 428 /* 429 * XXX This is a workaround for the VT6410 IDE controller! 430 * Apparently its interrupt cannot be disabled and remains 431 * asserted during the whole device probing procedure, 432 * causing an interrupt storm. 433 * Using an edge-trigger fixes that and triggers the 434 * interrupt only once during probing. 435 */ 436 type = IST_EDGE; 437 } else 438 type = IST_LEVEL; 439 440 /* 441 * ih is the value assigned in pci_intr_map(), above. 442 * It's the EPIC IRQ #. 443 */ 444 return intr_establish(ih + I8259_ICU, type, level, func, arg); 445 } 446 447 void 448 pci_intr_disestablish(void *v, void *cookie) 449 { 450 451 intr_disestablish(cookie); 452 } 453 454 #if defined(PCI_NETBSD_CONFIGURE) 455 void 456 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, 457 int pin, int swiz, int *iline) 458 { 459 if (bus == 0) { 460 *iline = dev; 461 } else { 462 /* 463 * If we are not on bus zero, we're behind a bridge, so we 464 * swizzle. 465 * 466 * The documentation lies about this. In slot 3 (numbering 467 * from 0) aka device 16, INTD# becomes an interrupt for 468 * slot 2. INTC# becomes an interrupt for slot 1, etc. 469 * In slot 2 aka device 16, INTD# becomes an interrupt for 470 * slot 1, etc. 471 * 472 * Verified for INTD# on device 16, INTC# on device 16, 473 * INTD# on device 15, INTD# on device 13, and INTC# on 474 * device 14. I presume that the rest follow the same 475 * pattern. 476 * 477 * Slot 0 is device 13, and is the base for the rest. 478 */ 479 *iline = 13 + ((swiz + dev + 3) & 3); 480 } 481 } 482 #endif 483