1 /* $NetBSD: pci_machdep.c,v 1.16 2008/05/30 19:26:35 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.16 2008/05/30 19:26:35 ad Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/errno.h> 52 #include <sys/extent.h> 53 #include <sys/malloc.h> 54 #include <sys/queue.h> 55 #include <sys/systm.h> 56 #include <sys/time.h> 57 58 #include <uvm/uvm.h> 59 60 #define _POWERPC_BUS_DMA_PRIVATE 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 #include <machine/pio.h> 64 65 #include <dev/isa/isavar.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pciconf.h> 69 #include <dev/pci/pcidevs.h> 70 71 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 72 0, /* _bounce_thresh */ 73 _bus_dmamap_create, 74 _bus_dmamap_destroy, 75 _bus_dmamap_load, 76 _bus_dmamap_load_mbuf, 77 _bus_dmamap_load_uio, 78 _bus_dmamap_load_raw, 79 _bus_dmamap_unload, 80 NULL, /* _dmamap_sync */ 81 _bus_dmamem_alloc, 82 _bus_dmamem_free, 83 _bus_dmamem_map, 84 _bus_dmamem_unmap, 85 _bus_dmamem_mmap, 86 }; 87 88 #define EPIC_DEBUGIRQ 89 90 static int brdtype; 91 #define BRD_SANDPOINTX2 2 92 #define BRD_SANDPOINTX3 3 93 #define BRD_ENCOREPP1 10 94 #define BRD_KUROBOX 100 95 #define BRD_QNAPTS101 101 96 #define BRD_SYNOLOGY 102 97 #define BRD_UNKNOWN -1 98 99 #define PCI_CONFIG_ENABLE 0x80000000UL 100 101 void 102 pci_attach_hook(struct device *parent, struct device *self, 103 struct pcibus_attach_args *pba) 104 { 105 pcitag_t tag; 106 pcireg_t dev11, dev22, dev15; 107 108 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 109 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 110 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 111 /* WinBond/Symphony Lab 83C553 at dev 11 */ 112 /* 113 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 114 * XXX SP3 #7 output values loopback to #6 input. 115 */ 116 brdtype = BRD_SANDPOINTX3; 117 return; 118 } 119 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 120 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 121 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 122 /* VIA 82C686B at dev 22 */ 123 brdtype = BRD_ENCOREPP1; 124 return; 125 } 126 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 127 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 128 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 129 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 130 brdtype = BRD_KUROBOX; 131 return; 132 } 133 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 134 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 135 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL) { 136 /* Intel GbE at dev 15 */ 137 brdtype = BRD_QNAPTS101; 138 return; 139 } 140 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 141 /* Marvell GbE at dev 15 */ 142 brdtype = BRD_SYNOLOGY; 143 return; 144 } 145 brdtype = BRD_UNKNOWN; 146 } 147 148 int 149 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 150 { 151 152 return 32; 153 } 154 155 pcitag_t 156 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 157 { 158 pcitag_t tag; 159 160 if (bus >= 256 || device >= 32 || function >= 8) 161 panic("pci_make_tag: bad request"); 162 163 tag = PCI_CONFIG_ENABLE | 164 (bus << 16) | (device << 11) | (function << 8); 165 return tag; 166 } 167 168 void 169 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 170 int *bp, int *dp, int *fp) 171 { 172 173 if (bp != NULL) 174 *bp = (tag >> 16) & 0xff; 175 if (dp != NULL) 176 *dp = (tag >> 11) & 0x1f; 177 if (fp != NULL) 178 *fp = (tag >> 8) & 0x7; 179 return; 180 } 181 182 /* 183 * The Kahlua documentation says that "reg" should be left-shifted by two 184 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 185 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 186 * the DINK32 "pcf" command). 187 */ 188 pcireg_t 189 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 190 { 191 pcireg_t data; 192 193 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 194 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 195 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 196 return data; 197 } 198 199 void 200 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 201 { 202 203 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 204 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 205 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 206 } 207 208 int 209 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 210 { 211 int pin = pa->pa_intrpin; 212 int line = pa->pa_intrline; 213 214 /* No IRQ used. */ 215 if (pin == 0) 216 goto bad; 217 if (pin > 4) { 218 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin); 219 goto bad; 220 } 221 222 /* 223 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 224 * `unknown' or `no connection' on a PC. We assume that a device with 225 * `no connection' either doesn't have an interrupt (in which case the 226 * pin number should be 0, and would have been noticed above), or 227 * wasn't configured by the BIOS (in which case we punt, since there's 228 * no real way we can know how the interrupt lines are mapped in the 229 * hardware). 230 * 231 * XXX 232 * Since IRQ 0 is only used by the clock, and we can't actually be sure 233 * that the BIOS did its job, we also recognize that as meaning that 234 * the BIOS has not configured the device. 235 */ 236 if (line == 255) { 237 aprint_error("pci_intr_map: no mapping for pin %c\n", 238 '@' + pin); 239 goto bad; 240 } 241 #ifdef EPIC_DEBUGIRQ 242 printf("line %d, pin %c", line, pin + '@'); 243 #endif 244 switch (brdtype) { 245 /* Sandpoint has 4 PCI slots in a weird order. 246 * From next to MPMC mezzanine card toward the board edge, 247 * 64bit slot PCI AD14 248 * 64bit slot PCI AD13 249 * 32bit slot PCI AD16 250 * 32bit slot PCI AD15 251 * Don't believe identifying labels printed on PCB and 252 * documents confusing as well since Moto names the slots 253 * as number 1 origin. 254 */ 255 case BRD_SANDPOINTX3: 256 /* 257 * Sandpoint X3 brd uses EPIC serial mode IRQ. 258 * - i8259 PIC interrupt to EPIC IRQ0. 259 * - WinBond IDE PCI C/D to EPIC IRQ8/9. 260 * - PCI AD13 pin A to EPIC IRQ2. 261 * - PCI AD14 pin A to EPIC IRQ3. 262 * - PCI AD15 pin A to EPIC IRQ4. 263 * - PCI AD16 pin A to EPIC IRQ5. 264 */ 265 if (line == 11 266 && pa->pa_function == 1 && pa->pa_bus == 0) { 267 /* X3 wires 83c553 pin C,D to EPIC IRQ8,9 */ 268 *ihp = 8; /* pin C only, indeed */ 269 break; 270 } 271 if (line < 13 || line > 16) { 272 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 273 line, pin + '@'); 274 goto bad; 275 } 276 line -= 13; /* B/C/D is not available */ 277 *ihp = 2 + line; 278 break; 279 case BRD_SANDPOINTX2: 280 /* 281 * Sandpoint X2 brd uses EPIC direct mode IRQ. 282 * - i8259 PIC interrupt EPIC IRQ2. 283 * - PCI AD13 pin A,B,C,D to EPIC IRQ0,1,2,3. 284 * - PCI AD14 pin A,B,C,D to EPIC IRQ1,2,3,0. 285 * - PCI AD15 pin A,B,C,D to EPIC IRQ2,3,0,1. 286 * - PCI AD16 pin A,B,C,D to EPIC IRQ3,0,1,2. 287 * - PCI AD12 is wired to PMPC device itself. 288 */ 289 if (line == 11 290 && pa->pa_function == 1 && pa->pa_bus == 0) { 291 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 292 *ihp = 2; 293 break; 294 } 295 if (line < 13 || line > 16) { 296 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 297 line, pin + '@'); 298 goto bad; 299 } 300 line -= 13; pin -= 1; 301 *ihp = (line + pin) & 03; 302 break; 303 case BRD_ENCOREPP1: 304 /* 305 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. 306 * PDF says VIA 686B SB i8259 interrupt goes through EPC IRQ0, 307 * while PCI pin A-D are tied with EPIC IRQ1-4. 308 * 309 * It mentions i82559 is at AD24, however, found at AD25 instead. 310 * Heuristics show that i82559 responds to EPIC 2 (!). Then we 311 * decided to return EPIC 2 here since i82559 is the only one PCI 312 * device ENCPP1 can have; 313 */ 314 if (pa->pa_device != 25) 315 goto bad; /* eeh !? */ 316 *ihp = 2; 317 break; 318 case BRD_KUROBOX: 319 /* map line 11,12,13,14 to EPIC IRQ0,1,4,3 */ 320 *ihp = (line == 13) ? 4 : line - 11; 321 break; 322 case BRD_QNAPTS101: 323 /* map line 12-15 to EPIC IRQ0-3 */ 324 *ihp = line - 12; 325 break; 326 case BRD_SYNOLOGY: 327 /* map line 12,13-15 to EPIC IRQ4,0-2 */ 328 *ihp = (line == 12) ? 4 : line - 13; 329 break; 330 default: 331 /* map line 12-15 to EPIC IRQ0-3 */ 332 *ihp = line - 12; 333 break; 334 } 335 #ifdef EPIC_DEBUGIRQ 336 printf(" = EPIC %d\n", *ihp); 337 #endif 338 return 0; 339 bad: 340 *ihp = -1; 341 return 1; 342 } 343 344 const char * 345 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 346 { 347 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 348 349 if (ih < 0 || ih >= OPENPIC_ICU) 350 panic("pci_intr_string: bogus handle 0x%x", ih); 351 352 sprintf(irqstr, "irq %d", ih + I8259_ICU); 353 return (irqstr); 354 355 } 356 357 const struct evcnt * 358 pci_intr_evcnt(void *v, pci_intr_handle_t ih) 359 { 360 361 /* XXX for now, no evcnt parent reported */ 362 return NULL; 363 } 364 365 int 366 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 367 int attr, uint64_t data) 368 { 369 370 switch (attr) { 371 case PCI_INTR_MPSAFE: 372 return 0; 373 default: 374 return ENODEV; 375 } 376 } 377 378 void * 379 pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 380 int (*func)(void *), void *arg) 381 { 382 /* 383 * ih is the value assigned in pci_intr_map(), above. 384 * It's the EPIC IRQ #. 385 */ 386 return intr_establish(ih + I8259_ICU, IST_LEVEL, level, func, arg); 387 } 388 389 void 390 pci_intr_disestablish(void *v, void *cookie) 391 { 392 393 intr_disestablish(cookie); 394 } 395 396 void 397 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, 398 int pin, int swiz, int *iline) 399 { 400 if (bus == 0) { 401 *iline = dev; 402 } else { 403 /* 404 * If we are not on bus zero, we're behind a bridge, so we 405 * swizzle. 406 * 407 * The documentation lies about this. In slot 3 (numbering 408 * from 0) aka device 16, INTD# becomes an interrupt for 409 * slot 2. INTC# becomes an interrupt for slot 1, etc. 410 * In slot 2 aka device 16, INTD# becomes an interrupt for 411 * slot 1, etc. 412 * 413 * Verified for INTD# on device 16, INTC# on device 16, 414 * INTD# on device 15, INTD# on device 13, and INTC# on 415 * device 14. I presume that the rest follow the same 416 * pattern. 417 * 418 * Slot 0 is device 13, and is the base for the rest. 419 */ 420 *iline = 13 + ((swiz + dev + 3) & 3); 421 } 422 } 423