1 /* $NetBSD: pci_machdep.c,v 1.17 2009/07/30 05:57:27 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.17 2009/07/30 05:57:27 nisimura Exp $"); 47 48 #include "opt_pci.h" 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/extent.h> 55 #include <sys/malloc.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 60 #include <uvm/uvm.h> 61 62 #define _POWERPC_BUS_DMA_PRIVATE 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 #include <machine/pio.h> 66 67 #include <dev/isa/isavar.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pciconf.h> 71 #include <dev/pci/pcidevs.h> 72 73 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 74 0, /* _bounce_thresh */ 75 _bus_dmamap_create, 76 _bus_dmamap_destroy, 77 _bus_dmamap_load, 78 _bus_dmamap_load_mbuf, 79 _bus_dmamap_load_uio, 80 _bus_dmamap_load_raw, 81 _bus_dmamap_unload, 82 NULL, /* _dmamap_sync */ 83 _bus_dmamem_alloc, 84 _bus_dmamem_free, 85 _bus_dmamem_map, 86 _bus_dmamem_unmap, 87 _bus_dmamem_mmap, 88 }; 89 90 #define EPIC_DEBUGIRQ 91 92 static int brdtype; 93 #define BRD_SANDPOINTX2 2 94 #define BRD_SANDPOINTX3 3 95 #define BRD_ENCOREPP1 10 96 #define BRD_KUROBOX 100 97 #define BRD_QNAPTS101 101 98 #define BRD_SYNOLOGY 102 99 #define BRD_UNKNOWN -1 100 101 #define PCI_CONFIG_ENABLE 0x80000000UL 102 103 void 104 pci_attach_hook(struct device *parent, struct device *self, 105 struct pcibus_attach_args *pba) 106 { 107 pcitag_t tag; 108 pcireg_t dev11, dev22, dev15; 109 110 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 111 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 112 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 113 /* WinBond/Symphony Lab 83C553 at dev 11 */ 114 /* 115 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 116 * XXX SP3 #7 output values loopback to #6 input. 117 */ 118 brdtype = BRD_SANDPOINTX3; 119 return; 120 } 121 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 122 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 123 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 124 /* VIA 82C686B at dev 22 */ 125 brdtype = BRD_ENCOREPP1; 126 return; 127 } 128 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 129 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 130 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 131 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 132 brdtype = BRD_KUROBOX; 133 return; 134 } 135 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 136 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 137 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL) { 138 /* Intel GbE at dev 15 */ 139 brdtype = BRD_QNAPTS101; 140 return; 141 } 142 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 143 /* Marvell GbE at dev 15 */ 144 brdtype = BRD_SYNOLOGY; 145 return; 146 } 147 brdtype = BRD_UNKNOWN; 148 } 149 150 int 151 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 152 { 153 154 return 32; 155 } 156 157 pcitag_t 158 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 159 { 160 pcitag_t tag; 161 162 if (bus >= 256 || device >= 32 || function >= 8) 163 panic("pci_make_tag: bad request"); 164 165 tag = PCI_CONFIG_ENABLE | 166 (bus << 16) | (device << 11) | (function << 8); 167 return tag; 168 } 169 170 void 171 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 172 int *bp, int *dp, int *fp) 173 { 174 175 if (bp != NULL) 176 *bp = (tag >> 16) & 0xff; 177 if (dp != NULL) 178 *dp = (tag >> 11) & 0x1f; 179 if (fp != NULL) 180 *fp = (tag >> 8) & 0x7; 181 return; 182 } 183 184 /* 185 * The Kahlua documentation says that "reg" should be left-shifted by two 186 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 187 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 188 * the DINK32 "pcf" command). 189 */ 190 pcireg_t 191 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 192 { 193 pcireg_t data; 194 195 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 196 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 197 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 198 return data; 199 } 200 201 void 202 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 203 { 204 205 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 206 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 207 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 208 } 209 210 int 211 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 212 { 213 int pin = pa->pa_intrpin; 214 int line = pa->pa_intrline; 215 216 /* No IRQ used. */ 217 if (pin == 0) 218 goto bad; 219 if (pin > 4) { 220 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin); 221 goto bad; 222 } 223 224 /* 225 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 226 * `unknown' or `no connection' on a PC. We assume that a device with 227 * `no connection' either doesn't have an interrupt (in which case the 228 * pin number should be 0, and would have been noticed above), or 229 * wasn't configured by the BIOS (in which case we punt, since there's 230 * no real way we can know how the interrupt lines are mapped in the 231 * hardware). 232 * 233 * XXX 234 * Since IRQ 0 is only used by the clock, and we can't actually be sure 235 * that the BIOS did its job, we also recognize that as meaning that 236 * the BIOS has not configured the device. 237 */ 238 if (line == 255) { 239 aprint_error("pci_intr_map: no mapping for pin %c\n", 240 '@' + pin); 241 goto bad; 242 } 243 #ifdef EPIC_DEBUGIRQ 244 printf("line %d, pin %c", line, pin + '@'); 245 #endif 246 switch (brdtype) { 247 /* Sandpoint has 4 PCI slots in a weird order. 248 * From next to MPMC mezzanine card toward the board edge, 249 * 64bit slot PCI AD14 250 * 64bit slot PCI AD13 251 * 32bit slot PCI AD16 252 * 32bit slot PCI AD15 253 * Don't believe identifying labels printed on PCB and 254 * documents confusing as well since Moto names the slots 255 * as number 1 origin. 256 */ 257 case BRD_SANDPOINTX3: 258 /* 259 * Sandpoint X3 brd uses EPIC serial mode IRQ. 260 * - i8259 PIC interrupt to EPIC IRQ0. 261 * - WinBond IDE PCI C/D to EPIC IRQ8/9. 262 * - PCI AD13 pin A to EPIC IRQ2. 263 * - PCI AD14 pin A to EPIC IRQ3. 264 * - PCI AD15 pin A to EPIC IRQ4. 265 * - PCI AD16 pin A to EPIC IRQ5. 266 */ 267 if (line == 11 268 && pa->pa_function == 1 && pa->pa_bus == 0) { 269 /* X3 wires 83c553 pin C,D to EPIC IRQ8,9 */ 270 *ihp = 8; /* pin C only, indeed */ 271 break; 272 } 273 if (line < 13 || line > 16) { 274 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 275 line, pin + '@'); 276 goto bad; 277 } 278 line -= 13; /* B/C/D is not available */ 279 *ihp = 2 + line; 280 break; 281 case BRD_SANDPOINTX2: 282 /* 283 * Sandpoint X2 brd uses EPIC direct mode IRQ. 284 * - i8259 PIC interrupt EPIC IRQ2. 285 * - PCI AD13 pin A,B,C,D to EPIC IRQ0,1,2,3. 286 * - PCI AD14 pin A,B,C,D to EPIC IRQ1,2,3,0. 287 * - PCI AD15 pin A,B,C,D to EPIC IRQ2,3,0,1. 288 * - PCI AD16 pin A,B,C,D to EPIC IRQ3,0,1,2. 289 * - PCI AD12 is wired to PMPC device itself. 290 */ 291 if (line == 11 292 && pa->pa_function == 1 && pa->pa_bus == 0) { 293 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 294 *ihp = 2; 295 break; 296 } 297 if (line < 13 || line > 16) { 298 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 299 line, pin + '@'); 300 goto bad; 301 } 302 line -= 13; pin -= 1; 303 *ihp = (line + pin) & 03; 304 break; 305 case BRD_ENCOREPP1: 306 /* 307 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. 308 * PDF says VIA 686B SB i8259 interrupt goes through EPC IRQ0, 309 * while PCI pin A-D are tied with EPIC IRQ1-4. 310 * 311 * It mentions i82559 is at AD24, however, found at AD25 instead. 312 * Heuristics show that i82559 responds to EPIC 2 (!). Then we 313 * decided to return EPIC 2 here since i82559 is the only one PCI 314 * device ENCPP1 can have; 315 */ 316 if (pa->pa_device != 25) 317 goto bad; /* eeh !? */ 318 *ihp = 2; 319 break; 320 case BRD_KUROBOX: 321 /* map line 11,12,13,14 to EPIC IRQ0,1,4,3 */ 322 *ihp = (line == 13) ? 4 : line - 11; 323 break; 324 case BRD_QNAPTS101: 325 /* map line 12-15 to EPIC IRQ0-3 */ 326 *ihp = line - 12; 327 break; 328 case BRD_SYNOLOGY: 329 /* map line 12,13-15 to EPIC IRQ4,0-2 */ 330 *ihp = (line == 12) ? 4 : line - 13; 331 break; 332 default: 333 /* map line 12-15 to EPIC IRQ0-3 */ 334 *ihp = line - 12; 335 break; 336 } 337 #ifdef EPIC_DEBUGIRQ 338 printf(" = EPIC %d\n", *ihp); 339 #endif 340 return 0; 341 bad: 342 *ihp = -1; 343 return 1; 344 } 345 346 const char * 347 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 348 { 349 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 350 351 if (ih < 0 || ih >= OPENPIC_ICU) 352 panic("pci_intr_string: bogus handle 0x%x", ih); 353 354 sprintf(irqstr, "irq %d", ih + I8259_ICU); 355 return (irqstr); 356 357 } 358 359 const struct evcnt * 360 pci_intr_evcnt(void *v, pci_intr_handle_t ih) 361 { 362 363 /* XXX for now, no evcnt parent reported */ 364 return NULL; 365 } 366 367 int 368 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 369 int attr, uint64_t data) 370 { 371 372 switch (attr) { 373 case PCI_INTR_MPSAFE: 374 return 0; 375 default: 376 return ENODEV; 377 } 378 } 379 380 void * 381 pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 382 int (*func)(void *), void *arg) 383 { 384 /* 385 * ih is the value assigned in pci_intr_map(), above. 386 * It's the EPIC IRQ #. 387 */ 388 return intr_establish(ih + I8259_ICU, IST_LEVEL, level, func, arg); 389 } 390 391 void 392 pci_intr_disestablish(void *v, void *cookie) 393 { 394 395 intr_disestablish(cookie); 396 } 397 398 #if defined(PCI_NETBSD_CONFIGURE) 399 void 400 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, 401 int pin, int swiz, int *iline) 402 { 403 if (bus == 0) { 404 *iline = dev; 405 } else { 406 /* 407 * If we are not on bus zero, we're behind a bridge, so we 408 * swizzle. 409 * 410 * The documentation lies about this. In slot 3 (numbering 411 * from 0) aka device 16, INTD# becomes an interrupt for 412 * slot 2. INTC# becomes an interrupt for slot 1, etc. 413 * In slot 2 aka device 16, INTD# becomes an interrupt for 414 * slot 1, etc. 415 * 416 * Verified for INTD# on device 16, INTC# on device 16, 417 * INTD# on device 15, INTD# on device 13, and INTC# on 418 * device 14. I presume that the rest follow the same 419 * pattern. 420 * 421 * Slot 0 is device 13, and is the base for the rest. 422 */ 423 *iline = 13 + ((swiz + dev + 3) & 3); 424 } 425 } 426 #endif 427