1 /* $NetBSD: intr.h,v 1.8 2014/05/19 22:47:53 rmind Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _BOOKE_INTR_H_ 38 #define _BOOKE_INTR_H_ 39 40 /* Interrupt priority `levels'. */ 41 #define IPL_NONE 0 /* nothing */ 42 #define IPL_SOFTCLOCK 1 /* software clock interrupt */ 43 #define IPL_SOFTBIO 2 /* software block i/o interrupt */ 44 #define IPL_SOFTNET 3 /* software network interrupt */ 45 #define IPL_SOFTSERIAL 4 /* software serial interrupt */ 46 #define IPL_VM 5 /* memory allocation */ 47 #define IPL_SCHED 6 /* clock */ 48 #define IPL_HIGH 7 /* everything */ 49 #define NIPL 8 50 51 /* Interrupt sharing types. */ 52 #define IST_NONE (NIPL+0) /* none */ 53 #define IST_EDGE (NIPL+1) /* edge-triggered */ 54 #define IST_LEVEL (NIPL+2) /* level-triggered active-low */ 55 #define IST_LEVEL_LOW IST_LEVEL 56 #define IST_LEVEL_HIGH (NIPL+3) /* level-triggered active-high */ 57 #define IST_PULSE (NIPL+4) /* pulsed */ 58 #define IST_MSI (NIPL+5) /* message signaling interrupt (PCI) */ 59 #define IST_ONCHIP (NIPL+6) /* on-chip device */ 60 #ifdef __INTR_PRIVATE 61 #define IST_MSIGROUP (NIPL+7) /* openpic msi groups */ 62 #define IST_TIMER (NIPL+8) /* openpic timers */ 63 #define IST_IPI (NIPL+9) /* openpic ipi */ 64 #define IST_MI (NIPL+10) /* openpic message */ 65 #define IST_MAX (NIPL+11) 66 #endif 67 68 #define IPI_DST_ALL ((cpuid_t)-2) 69 #define IPI_DST_NOTME ((cpuid_t)-1) 70 71 #define IPI_NOMESG 0x0000 72 #define IPI_HALT 0x0001 73 #define IPI_XCALL 0x0002 74 #define IPI_KPREEMPT 0x0004 75 #define IPI_TLB1SYNC 0x0008 76 #define IPI_GENERIC 0x0010 77 78 #define __HAVE_FAST_SOFTINTS 1 79 #define SOFTINT_KPREEMPT SOFTINT_COUNT 80 81 #ifndef _LOCORE 82 83 struct cpu_info; 84 85 void *intr_establish(int, int, int, int (*)(void *), void *); 86 void intr_disestablish(void *); 87 void intr_cpu_attach(struct cpu_info *); 88 void intr_cpu_hatch(struct cpu_info *); 89 void intr_init(void); 90 const char * 91 intr_string(int, int, char *, size_t); 92 const char * 93 intr_typename(int); 94 95 void cpu_send_ipi(cpuid_t, uint32_t); 96 97 void spl0(void); 98 int splraise(int); 99 void splx(int); 100 #ifdef __INTR_NOINLINE 101 int splhigh(void); 102 int splsched(void); 103 int splvm(void); 104 int splsoftserial(void); 105 int splsoftnet(void); 106 int splsoftbio(void); 107 int splsoftclock(void); 108 #endif 109 110 typedef int ipl_t; 111 typedef struct { 112 ipl_t _ipl; 113 } ipl_cookie_t; 114 115 #ifdef __INTR_PRIVATE 116 117 struct trapframe; 118 119 struct intrsw { 120 void *(*intrsw_establish)(int, int, int, int (*)(void *), void *); 121 void (*intrsw_disestablish)(void *); 122 void (*intrsw_cpu_attach)(struct cpu_info *); 123 void (*intrsw_cpu_hatch)(struct cpu_info *); 124 void (*intrsw_cpu_send_ipi)(cpuid_t, uint32_t); 125 void (*intrsw_init)(void); 126 void (*intrsw_critintr)(struct trapframe *); 127 void (*intrsw_decrintr)(struct trapframe *); 128 void (*intrsw_extintr)(struct trapframe *); 129 void (*intrsw_fitintr)(struct trapframe *); 130 void (*intrsw_wdogintr)(struct trapframe *); 131 int (*intrsw_splraise)(int); 132 void (*intrsw_spl0)(void); 133 void (*intrsw_splx)(int); 134 const char *(*intrsw_string)(int, int, char *, size_t); 135 const char *(*intrsw_typename)(int); 136 #ifdef __HAVE_FAST_SOFTINTS 137 void (*intrsw_softint_init_md)(struct lwp *, u_int, uintptr_t *); 138 void (*intrsw_softint_trigger)(uintptr_t); 139 #endif 140 }; 141 142 extern const struct intrsw *powerpc_intrsw; 143 void softint_fast_dispatch(struct lwp *, int); 144 #endif /* __INTR_PRIVATE */ 145 146 #ifndef __INTR_NOINLINE 147 static inline int 148 splhigh(void) 149 { 150 151 return splraise(IPL_HIGH); 152 } 153 154 static inline int 155 splsched(void) 156 { 157 158 return splraise(IPL_SCHED); 159 } 160 161 static inline int 162 splvm(void) 163 { 164 165 return splraise(IPL_VM); 166 } 167 168 static inline int 169 splsoftserial(void) 170 { 171 172 return splraise(IPL_SOFTSERIAL); 173 } 174 175 static inline int 176 splsoftnet(void) 177 { 178 179 return splraise(IPL_SOFTNET); 180 } 181 182 static inline int 183 splsoftbio(void) 184 { 185 186 return splraise(IPL_SOFTBIO); 187 } 188 189 static inline int 190 splsoftclock(void) 191 { 192 193 return splraise(IPL_SOFTCLOCK); 194 } 195 196 static inline int 197 splraiseipl(ipl_cookie_t icookie) 198 { 199 200 return splraise(icookie._ipl); 201 } 202 203 static inline ipl_cookie_t 204 makeiplcookie(ipl_t ipl) 205 { 206 207 return (ipl_cookie_t){._ipl = ipl}; 208 } 209 #endif /* !__INTR_NOINLINE */ 210 211 #endif /* !_LOCORE */ 212 #endif /* !_BOOKE_INTR_H_ */ 213