1 /* $NetBSD: intr.h,v 1.13 2022/09/12 08:14:55 rin Exp $ */
2 /*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 *
10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #ifndef _BOOKE_INTR_H_
38 #define _BOOKE_INTR_H_
39
40 /* Interrupt priority `levels'. */
41 #define IPL_NONE 0 /* nothing */
42 #define IPL_SOFTCLOCK 1 /* software clock interrupt */
43 #define IPL_SOFTBIO 2 /* software block i/o interrupt */
44 #define IPL_SOFTNET 3 /* software network interrupt */
45 #define IPL_SOFTSERIAL 4 /* software serial interrupt */
46 #define IPL_VM 5 /* memory allocation */
47 #define IPL_SCHED 6 /* clock */
48 #define IPL_HIGH 7 /* everything */
49 #define NIPL 8
50
51 /* Interrupt sharing types. */
52 #define IST_NONE (NIPL+0) /* none */
53 #define IST_EDGE (NIPL+1) /* edge-triggered */
54 #define IST_LEVEL (NIPL+2) /* level-triggered active-low */
55 #define IST_LEVEL_LOW IST_LEVEL
56 #define IST_LEVEL_HIGH (NIPL+3) /* level-triggered active-high */
57 #define IST_PULSE (NIPL+4) /* pulsed */
58 #define IST_MSI (NIPL+5) /* message signaling interrupt (PCI) */
59 #define IST_ONCHIP (NIPL+6) /* on-chip device */
60 #ifdef __INTR_PRIVATE
61 #define IST_MSIGROUP (NIPL+7) /* openpic msi groups */
62 #define IST_TIMER (NIPL+8) /* openpic timers */
63 #define IST_IPI (NIPL+9) /* openpic ipi */
64 #define IST_MI (NIPL+10) /* openpic message */
65 #define IST_MAX (NIPL+11)
66 #endif
67
68 #define IPI_DST_ALL ((cpuid_t)-2)
69 #define IPI_DST_NOTME ((cpuid_t)-1)
70
71 #define IPI_NOMESG 0x0000
72 #define IPI_HALT 0x0001
73 #define IPI_XCALL 0x0002
74 #define IPI_KPREEMPT 0x0004
75 #define IPI_TLB1SYNC 0x0008
76 #define IPI_GENERIC 0x0010
77 #define IPI_SUSPEND 0x0020
78 #define IPI_AST 0x0040
79
80 #if 0 /* PR port-powerpc/56922: fast softints are broken on powerpc */
81 #define __HAVE_FAST_SOFTINTS 1
82 #endif
83 #define SOFTINT_KPREEMPT SOFTINT_COUNT
84
85 #ifndef _LOCORE
86
87 struct cpu_info;
88
89 void *intr_establish(int, int, int, int (*)(void *), void *);
90 void *intr_establish_xname(int, int, int, int (*)(void *), void *,
91 const char *);
92 void intr_disestablish(void *);
93 void intr_cpu_attach(struct cpu_info *);
94 void intr_cpu_hatch(struct cpu_info *);
95 void intr_init(void);
96 const char *
97 intr_string(int, int, char *, size_t);
98 const char *
99 intr_typename(int);
100
101 void cpu_send_ipi(cpuid_t, uint32_t);
102
103 void spl0(void);
104 int splraise(int);
105 void splx(int);
106 #ifdef __INTR_NOINLINE
107 int splhigh(void);
108 int splsched(void);
109 int splvm(void);
110 int splsoftserial(void);
111 int splsoftnet(void);
112 int splsoftbio(void);
113 int splsoftclock(void);
114 #endif
115
116 typedef int ipl_t;
117 typedef struct {
118 ipl_t _ipl;
119 } ipl_cookie_t;
120
121 #ifdef __INTR_PRIVATE
122
123 struct trapframe;
124
125 struct intrsw {
126 void *(*intrsw_establish)(int, int, int, int (*)(void *), void *,
127 const char *);
128 void (*intrsw_disestablish)(void *);
129 void (*intrsw_cpu_attach)(struct cpu_info *);
130 void (*intrsw_cpu_hatch)(struct cpu_info *);
131 void (*intrsw_cpu_send_ipi)(cpuid_t, uint32_t);
132 void (*intrsw_init)(void);
133 void (*intrsw_critintr)(struct trapframe *);
134 void (*intrsw_decrintr)(struct trapframe *);
135 void (*intrsw_extintr)(struct trapframe *);
136 void (*intrsw_fitintr)(struct trapframe *);
137 void (*intrsw_wdogintr)(struct trapframe *);
138 int (*intrsw_splraise)(int);
139 void (*intrsw_spl0)(void);
140 void (*intrsw_splx)(int);
141 const char *(*intrsw_string)(int, int, char *, size_t);
142 const char *(*intrsw_typename)(int);
143 #ifdef __HAVE_FAST_SOFTINTS
144 void (*intrsw_softint_init_md)(struct lwp *, u_int, uintptr_t *);
145 void (*intrsw_softint_trigger)(uintptr_t);
146 #endif
147 };
148
149 extern const struct intrsw *powerpc_intrsw;
150 void softint_fast_dispatch(struct lwp *, int);
151 #endif /* __INTR_PRIVATE */
152
153 #ifndef __INTR_NOINLINE
154 static __inline int
splhigh(void)155 splhigh(void)
156 {
157
158 return splraise(IPL_HIGH);
159 }
160
161 static __inline int
splsched(void)162 splsched(void)
163 {
164
165 return splraise(IPL_SCHED);
166 }
167
168 static __inline int
splvm(void)169 splvm(void)
170 {
171
172 return splraise(IPL_VM);
173 }
174
175 static __inline int
splsoftserial(void)176 splsoftserial(void)
177 {
178
179 return splraise(IPL_SOFTSERIAL);
180 }
181
182 static __inline int
splsoftnet(void)183 splsoftnet(void)
184 {
185
186 return splraise(IPL_SOFTNET);
187 }
188
189 static __inline int
splsoftbio(void)190 splsoftbio(void)
191 {
192
193 return splraise(IPL_SOFTBIO);
194 }
195
196 static __inline int
splsoftclock(void)197 splsoftclock(void)
198 {
199
200 return splraise(IPL_SOFTCLOCK);
201 }
202
203 static __inline int
splraiseipl(ipl_cookie_t icookie)204 splraiseipl(ipl_cookie_t icookie)
205 {
206
207 return splraise(icookie._ipl);
208 }
209
210 static __inline ipl_cookie_t
makeiplcookie(ipl_t ipl)211 makeiplcookie(ipl_t ipl)
212 {
213
214 return (ipl_cookie_t){._ipl = ipl};
215 }
216 #endif /* !__INTR_NOINLINE */
217
218 #endif /* !_LOCORE */
219 #endif /* !_BOOKE_INTR_H_ */
220