1 /* $NetBSD: fpu_emu.h,v 1.12 2022/09/07 02:41:39 rin Exp $ */
2
3 /*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley.
10 *
11 * All advertising materials mentioning features or use of this software
12 * must display the following acknowledgement:
13 * This product includes software developed by the University of
14 * California, Lawrence Berkeley Laboratory.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93
41 */
42
43 /*
44 * Floating point emulator (tailored for SPARC, but structurally
45 * machine-independent).
46 *
47 * Floating point numbers are carried around internally in an `expanded'
48 * or `unpacked' form consisting of:
49 * - sign
50 * - unbiased exponent
51 * - mantissa (`1.' + 112-bit fraction + guard + round)
52 * - sticky bit
53 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is
54 * always nonzero. Additional low-order `guard' and `round' bits are
55 * scrunched in, making the entire mantissa 115 bits long. This is divided
56 * into four 32-bit words, with `spare' bits left over in the upper part
57 * of the top word (the high bits of fp_mant[0]). An internal `exploded'
58 * number is thus kept within the half-open interval [1.0,2.0) (but see
59 * the `number classes' below). This holds even for denormalized numbers:
60 * when we explode an external denorm, we normalize it, introducing low-order
61 * zero bits, so that the rest of the code always sees normalized values.
62 *
63 * Note that a number of our algorithms use the `spare' bits at the top.
64 * The most demanding algorithm---the one for sqrt---depends on two such
65 * bits, so that it can represent values up to (but not including) 8.0,
66 * and then it needs a carry on top of that, so that we need three `spares'.
67 *
68 * The sticky-word is 32 bits so that we can use `OR' operators to goosh
69 * whole words from the mantissa into it.
70 *
71 * All operations are done in this internal extended precision. According
72 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is,
73 * it is OK to do a+b in extended precision and then round the result to
74 * single precision---provided single, double, and extended precisions are
75 * `far enough apart' (they always are), but we will try to avoid any such
76 * extra work where possible.
77 */
78 struct fpn {
79 int fp_class; /* see below */
80 int fp_sign; /* 0 => positive, 1 => negative */
81 int fp_exp; /* exponent (unbiased) */
82 int fp_sticky; /* nonzero bits lost at right end */
83 u_int fp_mant[4]; /* 115-bit mantissa */
84 };
85
86 #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */
87 #define FP_NG 2 /* number of low-order guard bits */
88 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */
89 #define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */
90 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */
91 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */
92 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */
93
94 /*
95 * Number classes. Since zero, Inf, and NaN cannot be represented using
96 * the above layout, we distinguish these from other numbers via a class.
97 * In addition, to make computation easier and to follow Appendix N of
98 * the SPARC Version 8 standard, we give each kind of NaN a separate class.
99 */
100 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */
101 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */
102 #define FPC_ZERO 0 /* zero (sign matters) */
103 #define FPC_NUM 1 /* number (sign matters) */
104 #define FPC_INF 2 /* infinity (sign matters) */
105
106 #define ISSNAN(fp) ((fp)->fp_class == FPC_SNAN)
107 #define ISQNAN(fp) ((fp)->fp_class == FPC_QNAN)
108 #define ISNAN(fp) ((fp)->fp_class < 0)
109 #define ISZERO(fp) ((fp)->fp_class == 0)
110 #define ISINF(fp) ((fp)->fp_class == FPC_INF)
111
112 /*
113 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points
114 * to the `more significant' operand for our purposes. Appendix N says that
115 * the result of a computation involving two numbers are:
116 *
117 * If both are SNaN: operand 2, converted to Quiet
118 * If only one is SNaN: the SNaN operand, converted to Quiet
119 * If both are QNaN: operand 2
120 * If only one is QNaN: the QNaN operand
121 *
122 * In addition, in operations with an Inf operand, the result is usually
123 * Inf. The class numbers are carefully arranged so that if
124 * (unsigned)class(op1) > (unsigned)class(op2)
125 * then op1 is the one we want; otherwise op2 is the one we want.
126 */
127 #define ORDER(x, y) { \
128 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \
129 SWAP(x, y); \
130 }
131 #define SWAP(x, y) { \
132 struct fpn *swap; \
133 swap = (x), (x) = (y), (y) = swap; \
134 }
135
136 /*
137 * FPU data types.
138 */
139 #define FTYPE_INT 0x00 /* data = 32-bit signed integer */
140 #define FTYPE_LNG 0x01 /* data = 64-bit signed long integer */
141 #define FTYPE_SNG 0x02 /* data = 32-bit float */
142 #define FTYPE_DBL 0x04 /* data = 64-bit double */
143 #define FTYPE_RD_RZ 0x08
144 #define FTYPE_FPSCR 0x10
145 #define FTYPE_FLAG_MASK (FTYPE_RD_RZ | FTYPE_FPSCR)
146
147 /*
148 * Emulator state.
149 */
150 struct fpemu {
151 struct fpreg *fe_fpstate; /* registers, etc */
152 int fe_fpscr; /* fpscr copy (modified during op) */
153 int fe_cx; /* keep track of exceptions */
154 struct fpn fe_f1; /* operand 1 */
155 struct fpn fe_f2; /* operand 2, if required */
156 struct fpn fe_f3; /* available storage for result */
157 vaddr_t fe_addr; /* last address accessed */
158 };
159
160 /*
161 * Arithmetic functions.
162 * Each of these may modify its inputs (f1,f2) and/or the temporary.
163 * Each returns a pointer to the result and/or sets exceptions.
164 */
165 struct fpn *fpu_add(struct fpemu *);
166 struct fpn *fpu_mul(struct fpemu *);
167 struct fpn *fpu_div(struct fpemu *);
168 struct fpn *fpu_sqrt(struct fpemu *);
169
170 static inline struct fpn *
fpu_sub(struct fpemu * fe)171 fpu_sub(struct fpemu *fe)
172 {
173 struct fpn *fp = &fe->fe_f2;
174
175 if (!ISNAN(fp))
176 fp->fp_sign ^= 1;
177 return fpu_add(fe);
178 }
179
180 /*
181 * Other functions.
182 */
183
184 /* Perform a compare instruction (with or without unordered exception). */
185 void fpu_compare(struct fpemu *, int);
186
187 /* Build a new Quiet NaN (sign=0, frac=all 1's). */
188 struct fpn *fpu_newnan(struct fpemu *);
189
190 /*
191 * Shift a number right some number of bits, taking care of round/sticky.
192 * Note that the result is probably not a well-formed number (it will lack
193 * the normal 1-bit mant[0]&FP_1).
194 */
195 int fpu_shr(struct fpn *, int);
196
197 void fpu_norm(struct fpn *);
198
199 void fpu_explode(struct fpemu *, struct fpn *, int, uint64_t);
200 void fpu_implode(struct fpemu *, struct fpn *, int, uint64_t *);
201
202 #ifdef DEBUG
203 #define FPE_EX 0x1
204 #define FPE_INSN 0x2
205 #define FPE_OP 0x4
206 #define FPE_REG 0x8
207 extern int fpe_debug;
208 void fpu_dumpfpn(struct fpn *);
209 #define DPRINTF(x, y) if (fpe_debug & (x)) printf y
210 #define DUMPFPN(x, f) if (fpe_debug & (x)) fpu_dumpfpn((f))
211 #else
212 #define DPRINTF(x, y)
213 #define DUMPFPN(x, f)
214 #endif
215