1 /* $NetBSD: pq3diic.c,v 1.5 2020/07/06 09:34:16 rin Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: pq3diic.c,v 1.5 2020/07/06 09:34:16 rin Exp $"); 39 40 #include "ioconf.h" 41 42 #include <sys/param.h> 43 #include <sys/cpu.h> 44 #include <sys/device.h> 45 #include <sys/tty.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/i2c/i2cvar.h> 51 52 #include <dev/i2c/motoi2creg.h> 53 #include <dev/i2c/motoi2cvar.h> 54 55 #include <powerpc/booke/cpuvar.h> 56 #include <powerpc/booke/e500var.h> 57 #include <powerpc/booke/e500reg.h> 58 59 struct pq3diic_softc { 60 device_t sc_dev; 61 void *sc_ih; 62 struct motoi2c_softc sc_motoi2c[2]; 63 }; 64 65 static int pq3diic_match(device_t, cfdata_t, void *); 66 static void pq3diic_attach(device_t, device_t, void *); 67 68 CFATTACH_DECL_NEW(pq3diic, sizeof(struct pq3diic_softc), 69 pq3diic_match, pq3diic_attach, NULL, NULL); 70 71 static int 72 pq3diic_match(device_t parent, cfdata_t cf, void *aux) 73 { 74 75 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 76 return 0; 77 78 return 1; 79 } 80 81 static int 82 pq3diic_intr(void *arg) 83 { 84 struct pq3diic_softc * const sc = arg; 85 int rv = 0; 86 87 rv += motoi2c_intr(&sc->sc_motoi2c[0]); 88 rv += motoi2c_intr(&sc->sc_motoi2c[1]); 89 90 return rv; 91 } 92 93 static void 94 pq3diic_attach(device_t parent, device_t self, void *aux) 95 { 96 struct cpunode_softc * const psc = device_private(parent); 97 struct pq3diic_softc * const sc = device_private(self); 98 struct cpunode_attach_args * const cna = aux; 99 struct cpunode_locators * const cnl = &cna->cna_locs; 100 u_int nports = cnl->cnl_size / I2C_SIZE; 101 int error; 102 103 psc->sc_children |= cna->cna_childmask; 104 sc->sc_dev = self; 105 106 aprint_normal(": %u port%s\n", nports, nports == 1 ? "" : "s"); 107 108 for (u_int port = 0; port <= uimin(1, nports); port++) { 109 struct motoi2c_softc * const msc = &sc->sc_motoi2c[port]; 110 msc->sc_iot = cna->cna_memt; 111 error = bus_space_map(msc->sc_iot, 112 cnl->cnl_addr + port * I2C_SIZE, 113 I2C_SIZE, 0, &msc->sc_ioh); 114 if (error) { 115 aprint_error_dev(self, 116 "can't map registers for i2c#%uL %d\n", 117 port, error); 118 } else { 119 motoi2c_attach_common(self, msc, NULL); 120 } 121 } 122 123 sc->sc_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 124 pq3diic_intr, sc); 125 if (sc->sc_ih == NULL) 126 aprint_error_dev(self, "failed to establish interrupt %d\n", 127 cnl->cnl_intrs[0]); 128 else 129 aprint_normal_dev(self, "interrupting on irq %d\n", 130 cnl->cnl_intrs[0]); 131 } 132