1 /* $NetBSD: pq3diic.c,v 1.7 2022/07/22 23:43:24 thorpej Exp $ */
2 /*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 *
10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: pq3diic.c,v 1.7 2022/07/22 23:43:24 thorpej Exp $");
39
40 #include "ioconf.h"
41
42 #include <sys/param.h>
43 #include <sys/cpu.h>
44 #include <sys/device.h>
45 #include <sys/tty.h>
46
47 #include <sys/intr.h>
48 #include <sys/bus.h>
49
50 #include <dev/i2c/i2cvar.h>
51
52 #include <dev/i2c/motoi2creg.h>
53 #include <dev/i2c/motoi2cvar.h>
54
55 #include <powerpc/booke/cpuvar.h>
56 #include <powerpc/booke/e500var.h>
57 #include <powerpc/booke/e500reg.h>
58
59 static int pq3diic_match(device_t, cfdata_t, void *);
60 static void pq3diic_attach(device_t, device_t, void *);
61
62 CFATTACH_DECL_NEW(pq3diic, sizeof(struct motoi2c_softc),
63 pq3diic_match, pq3diic_attach, NULL, NULL);
64
65 static int
pq3diic_match(device_t parent,cfdata_t cf,void * aux)66 pq3diic_match(device_t parent, cfdata_t cf, void *aux)
67 {
68
69 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux))
70 return 0;
71
72 return 1;
73 }
74
75 #if 0
76 static int
77 pq3diic_intr(void *arg)
78 {
79 struct pq3diic_softc * const sc = arg;
80
81 return motoi2c_intr(&sc->sc_motoi2c);
82 }
83 #endif
84
85 static void
pq3diic_attach(device_t parent,device_t self,void * aux)86 pq3diic_attach(device_t parent, device_t self, void *aux)
87 {
88 struct cpunode_softc * const psc = device_private(parent);
89 struct motoi2c_softc * const sc = device_private(self);
90 struct cpunode_attach_args * const cna = aux;
91 struct cpunode_locators * const cnl = &cna->cna_locs;
92 int error;
93
94 psc->sc_children |= cna->cna_childmask;
95 sc->sc_dev = self;
96
97 aprint_normal("\n");
98
99 sc->sc_iot = cna->cna_memt;
100 error = bus_space_map(sc->sc_iot, cnl->cnl_addr, I2C_SIZE,
101 0, &sc->sc_ioh);
102 if (error) {
103 aprint_error_dev(self,
104 "can't map registers (error = %d)\n", error);
105 return;
106 }
107
108 motoi2c_attach(sc, NULL);
109
110 #if 0
111 /*
112 * XXX e500_intr.c can't handle shared interrupts, but that's
113 * XXX ok, because motoi2c doesn't support using interrupts
114 * XXX at the moment anyway.
115 */
116 sc->sc_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP,
117 pq3diic_intr, sc);
118 if (sc->sc_ih == NULL)
119 aprint_error_dev(self, "failed to establish interrupt %d\n",
120 cnl->cnl_intrs[0]);
121 else
122 aprint_normal_dev(self, "interrupting on irq %d\n",
123 cnl->cnl_intrs[0]);
124 #endif
125 }
126