1 /* $NetBSD: wdc_spd.c,v 1.30 2023/12/20 15:29:05 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2001, 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: wdc_spd.c,v 1.30 2023/12/20 15:29:05 thorpej Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37
38 #define __read_1(a) \
39 ({ \
40 u_int32_t ra_ = (a); \
41 u_int8_t r = (*(volatile u_int8_t *)ra_); \
42 \
43 if (ra_ == 0xb400004e) /* (wdc)STAT LED off */ \
44 SPD_LED_OFF(); \
45 \
46 (r); \
47 })
48 #define __write_1(a, v) \
49 { \
50 u_int32_t wa_ = (a); \
51 (*(volatile u_int8_t *)wa_) = (v); \
52 \
53 if (wa_ == 0xb400004e) /* (wdc)CMD LED on */ \
54 SPD_LED_ON(); \
55 }
56 #define _PLAYSTATION2_BUS_SPACE_PRIVATE
57 #include <machine/bus.h>
58
59 #include <dev/ata/atavar.h>
60 #include <dev/ic/wdcvar.h>
61
62 #include <playstation2/ee/eevar.h>
63 #include <playstation2/dev/spdvar.h>
64 #include <playstation2/dev/spdreg.h>
65
66 #define WDC_SPD_HDD_AUXREG_OFFSET 0x1c
67
68 struct wdc_spd_softc {
69 struct wdc_softc sc_wdcdev;
70 struct ata_channel *sc_chanlist[1];
71 struct ata_channel sc_channel;
72 struct wdc_regs sc_wdc_regs;
73 void *sc_ih;
74 };
75
76 #ifdef DEBUG
77 #define STATIC
78 #else
79 #define STATIC static
80 #endif
81
82 STATIC int wdc_spd_match(device_t, cfdata_t, void *);
83 STATIC void wdc_spd_attach(device_t, device_t, void *);
84
85 CFATTACH_DECL_NEW(wdc_spd, sizeof (struct wdc_spd_softc),
86 wdc_spd_match, wdc_spd_attach, NULL, NULL);
87
88 extern struct cfdriver wdc_cd;
89
90 STATIC void __wdc_spd_enable(void);
91 STATIC void __wdc_spd_disable(void) __attribute__((__unused__));
92 STATIC void __wdc_spd_bus_space(struct wdc_regs *);
93
94 /*
95 * wdc register is 16 bit wide.
96 */
97 #define VADDR(h, o) ((h) + (o))
98 _BUS_SPACE_READ(_wdc_spd, 1, 8)
99 _BUS_SPACE_READ(_wdc_spd, 2, 16)
100 _BUS_SPACE_READ_MULTI(_wdc_spd, 1, 8)
101 _BUS_SPACE_READ_MULTI(_wdc_spd, 2, 16)
102 _BUS_SPACE_READ_REGION(_wdc_spd, 1, 8)
103 _BUS_SPACE_READ_REGION(_wdc_spd, 2, 16)
104 _BUS_SPACE_WRITE(_wdc_spd, 1, 8)
105 _BUS_SPACE_WRITE(_wdc_spd, 2, 16)
106 _BUS_SPACE_WRITE_MULTI(_wdc_spd, 1, 8)
107 _BUS_SPACE_WRITE_MULTI(_wdc_spd, 2, 16)
108 _BUS_SPACE_WRITE_REGION(_wdc_spd, 1, 8)
109 _BUS_SPACE_WRITE_REGION(_wdc_spd, 2, 16)
110 _BUS_SPACE_SET_MULTI(_wdc_spd, 1, 8)
111 _BUS_SPACE_SET_MULTI(_wdc_spd, 2, 16)
112 _BUS_SPACE_SET_REGION(_wdc_spd, 1, 8)
113 _BUS_SPACE_SET_REGION(_wdc_spd, 2, 16)
114 _BUS_SPACE_COPY_REGION(_wdc_spd, 1, 8)
115 _BUS_SPACE_COPY_REGION(_wdc_spd, 2, 16)
116 #undef VADDR
117
118 STATIC const struct playstation2_bus_space _wdc_spd_space = {
119 pbs_map : _BUS_SPACE_NO_MAP,
120 pbs_unmap : _BUS_SPACE_NO_UNMAP,
121 pbs_subregion : _BUS_SPACE_NO_SUBREGION,
122 pbs_alloc : _BUS_SPACE_NO_ALLOC,
123 pbs_free : _BUS_SPACE_NO_FREE,
124 pbs_vaddr : _BUS_SPACE_NO_VADDR,
125 pbs_r_1 : _wdc_spd_read_1,
126 pbs_r_2 : _wdc_spd_read_2,
127 pbs_r_4 : _BUS_SPACE_NO_READ(4, 32),
128 pbs_r_8 : _BUS_SPACE_NO_READ(8, 64),
129 pbs_rm_1 : _wdc_spd_read_multi_1,
130 pbs_rm_2 : _wdc_spd_read_multi_2,
131 pbs_rm_4 : _BUS_SPACE_NO_READ_MULTI(4, 32),
132 pbs_rm_8 : _BUS_SPACE_NO_READ_MULTI(8, 64),
133 pbs_rr_1 : _wdc_spd_read_region_1,
134 pbs_rr_2 : _wdc_spd_read_region_2,
135 pbs_rr_4 : _BUS_SPACE_NO_READ_REGION(4, 32),
136 pbs_rr_8 : _BUS_SPACE_NO_READ_REGION(8, 64),
137 pbs_w_1 : _wdc_spd_write_1,
138 pbs_w_2 : _wdc_spd_write_2,
139 pbs_w_4 : _BUS_SPACE_NO_WRITE(4, 32),
140 pbs_w_8 : _BUS_SPACE_NO_WRITE(8, 64),
141 pbs_wm_1 : _wdc_spd_write_multi_1,
142 pbs_wm_2 : _wdc_spd_write_multi_2,
143 pbs_wm_4 : _BUS_SPACE_NO_WRITE_MULTI(4, 32),
144 pbs_wm_8 : _BUS_SPACE_NO_WRITE_MULTI(8, 64),
145 pbs_wr_1 : _wdc_spd_write_region_1,
146 pbs_wr_2 : _wdc_spd_write_region_2,
147 pbs_wr_4 : _BUS_SPACE_NO_WRITE_REGION(4, 32),
148 pbs_wr_8 : _BUS_SPACE_NO_WRITE_REGION(8, 64),
149 pbs_sm_1 : _wdc_spd_set_multi_1,
150 pbs_sm_2 : _wdc_spd_set_multi_2,
151 pbs_sm_4 : _BUS_SPACE_NO_SET_MULTI(4, 32),
152 pbs_sm_8 : _BUS_SPACE_NO_SET_MULTI(8, 64),
153 pbs_sr_1 : _wdc_spd_set_region_1,
154 pbs_sr_2 : _wdc_spd_set_region_2,
155 pbs_sr_4 : _BUS_SPACE_NO_SET_REGION(4, 32),
156 pbs_sr_8 : _BUS_SPACE_NO_SET_REGION(8, 64),
157 pbs_c_1 : _wdc_spd_copy_region_1,
158 pbs_c_2 : _wdc_spd_copy_region_2,
159 pbs_c_4 : _BUS_SPACE_NO_COPY_REGION(4, 32),
160 pbs_c_8 : _BUS_SPACE_NO_COPY_REGION(8, 64),
161 };
162
163 int
wdc_spd_match(device_t parent,cfdata_t cf,void * aux)164 wdc_spd_match(device_t parent, cfdata_t cf, void *aux)
165 {
166 struct spd_attach_args *spa = aux;
167 struct wdc_regs wdr;
168 int i, result;
169
170 if (spa->spa_slot != SPD_HDD)
171 return (0);
172
173 __wdc_spd_bus_space(&wdr);
174
175 for (i = 0, result = 0; i < 8; i++) { /* 8 sec */
176 if (result == 0)
177 result = wdcprobe(&wdr);
178 delay(1000000);
179 }
180
181 return (result);
182 }
183
184 void
wdc_spd_attach(device_t parent,device_t self,void * aux)185 wdc_spd_attach(device_t parent, device_t self, void *aux)
186 {
187 struct spd_attach_args *spa = aux;
188 struct wdc_spd_softc *sc = device_private(self);
189 struct wdc_softc *wdc = &sc->sc_wdcdev;
190 struct ata_channel *ch = &sc->sc_channel;
191
192 aprint_normal(": %s\n", spa->spa_product_name);
193
194 sc->sc_wdcdev.sc_atac.atac_dev = self;
195 sc->sc_wdcdev.regs = &sc->sc_wdc_regs;
196
197 wdc->sc_atac.atac_cap =
198 ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_DATA16;
199 wdc->sc_atac.atac_pio_cap = 0;
200 sc->sc_chanlist[0] = &sc->sc_channel;
201 wdc->sc_atac.atac_channels = sc->sc_chanlist;
202 wdc->sc_atac.atac_nchannels = 1;
203 ch->ch_channel = 0;
204 ch->ch_atac = &sc->sc_wdcdev.sc_atac;
205 ch->ch_ndrives = 2;
206
207 __wdc_spd_bus_space(CHAN_TO_WDC_REGS(ch));
208
209 spd_intr_establish(SPD_HDD, wdcintr, &sc->sc_channel);
210
211 __wdc_spd_enable();
212
213 wdcattach(&sc->sc_channel);
214 }
215
216 void
__wdc_spd_bus_space(struct wdc_regs * wdr)217 __wdc_spd_bus_space(struct wdc_regs *wdr)
218 {
219 int i;
220
221 wdr->cmd_iot = &_wdc_spd_space;
222 for (i = 0; i < 8; i++)
223 wdr->cmd_iohs[i] = SPD_HDD_IO_BASE + i * 2; /* wdc register is 16 bit wide. */
224 wdc_init_shadow_regs(wdr);
225 wdr->ctl_iot = &_wdc_spd_space;
226 wdr->ctl_ioh = SPD_HDD_IO_BASE + WDC_SPD_HDD_AUXREG_OFFSET;
227 wdr->data32iot = wdr->cmd_iot;
228 wdr->data32ioh = SPD_HDD_IO_BASE;
229 }
230
231 void
__wdc_spd_enable(void)232 __wdc_spd_enable(void)
233 {
234 u_int16_t r;
235
236 r = _reg_read_2(SPD_INTR_ENABLE_REG16);
237 r |= SPD_INTR_HDD;
238 _reg_write_2(SPD_INTR_ENABLE_REG16, r);
239 }
240
241 void
__wdc_spd_disable(void)242 __wdc_spd_disable(void)
243 {
244 u_int16_t r;
245
246 r = _reg_read_2(SPD_INTR_ENABLE_REG16);
247 r &= ~SPD_INTR_HDD;
248 _reg_write_2(SPD_INTR_ENABLE_REG16, r);
249 }
250