1 /* $NetBSD: rmixl_gpio.c,v 1.5 2021/08/07 16:18:59 thorpej Exp $ */
2 /* $NetBSD: rmixl_gpio.c,v 1.5 2021/08/07 16:18:59 thorpej Exp $ */
3 /*-
4 * Copyright (c) 2007 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: rmixl_gpio.c,v 1.5 2021/08/07 16:18:59 thorpej Exp $");
33
34 #define _INTR_PRIVATE
35
36 #include "locators.h"
37 #include "gpio.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/cpu.h>
42 #include <sys/evcnt.h>
43 #include <sys/intr.h>
44 #include <sys/atomic.h>
45
46 #include <uvm/uvm_extern.h>
47
48 #include <mips/rmi/rmixlreg.h>
49 #include <mips/rmi/rmixlvar.h>
50 #include <mips/rmi/rmixl_obiovar.h>
51
52 #if NGPIO > 0
53 #include <sys/gpio.h>
54 #include <dev/gpio/gpiovar.h>
55 #endif
56
57 struct gpio_softc {
58 device_t gpio_dev;
59 void *gpio_ih;
60 bus_space_tag_t gpio_memt;
61 bus_space_handle_t gpio_memh;
62 uint32_t gpio_enable_mask;
63 uint32_t gpio_edge_mask;
64 uint32_t gpio_edge_falling_mask;
65 uint32_t gpio_edge_rising_mask;
66 uint32_t gpio_level_mask;
67 uint32_t gpio_level_hi_mask;
68 uint32_t gpio_level_lo_mask;
69 uint32_t gpio_inuse_mask;
70 #if NGPIO > 0
71 struct gpio_chipset_tag gpio_chipset;
72 gpio_pin_t gpio_pins[RMIXL_GPIO_NSIGNALS];
73 #endif
74 };
75
76 #define GPIO_READ(gpio, reg) \
77 bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg))
78 #define GPIO_WRITE(gpio, reg, val) \
79 bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val))
80
81 static int gpio_match(device_t, cfdata_t, void *);
82 static void gpio_attach(device_t, device_t, void *);
83
84 CFATTACH_DECL_NEW(rmixl_gpio,
85 sizeof(struct gpio_softc),
86 gpio_match, gpio_attach,
87 NULL, NULL);
88
89 #if NGPIO > 0
90
91 static int
rmixl_gpio_pin_read(void * arg,int pin)92 rmixl_gpio_pin_read(void *arg, int pin)
93 {
94 struct gpio_softc * const gpio = arg;
95
96 KASSERT(((1 << pin) & RMIXL_GPIO_INPUT_MASK) != 0);
97 return (GPIO_READ(gpio, RMIXL_GPIO_INPUT) >> pin) & 1;
98 }
99
100 static void
rmixl_gpio_pin_write(void * arg,int pin,int value)101 rmixl_gpio_pin_write(void *arg, int pin, int value)
102 {
103 struct gpio_softc * const gpio = arg;
104 uint32_t mask = 1 << pin;
105 uint32_t old, new;
106
107 KASSERT(((1 << pin) & RMIXL_GPIO_OUTPUT_MASK) != 0);
108
109 old = GPIO_READ(gpio, RMIXL_GPIO_OUTPUT);
110 if (value)
111 new = old | mask;
112 else
113 new = old & ~mask;
114
115 if (old != new)
116 GPIO_WRITE(gpio, RMIXL_GPIO_OUTPUT, new);
117 }
118
119 static void
rmixl_gpio_pin_ctl(void * arg,int pin,int flags)120 rmixl_gpio_pin_ctl(void *arg, int pin, int flags)
121 {
122 struct gpio_softc * const gpio = arg;
123 uint32_t mask = 1 << pin;
124 uint32_t old, new;
125
126 KASSERT((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) != (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT));
127 old = GPIO_READ(gpio, RMIXL_GPIO_IO_DIR);
128 new = old;
129 switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
130 case GPIO_PIN_INPUT: new &= ~mask; break;
131 case GPIO_PIN_OUTPUT: new |= mask; break;
132 default: return;
133 }
134 if (old != new)
135 GPIO_WRITE(gpio, RMIXL_GPIO_IO_DIR, new);
136 }
137
138 static void
gpio_defer(device_t self)139 gpio_defer(device_t self)
140 {
141 struct gpio_softc * const gpio = device_private(self);
142 struct gpio_chipset_tag * const gp = &gpio->gpio_chipset;
143 struct gpiobus_attach_args gba;
144 gpio_pin_t *pins;
145 uint32_t mask, dir, valueout, valuein;
146 int pin;
147
148 gp->gp_cookie = gpio;
149 gp->gp_pin_read = rmixl_gpio_pin_read;
150 gp->gp_pin_write = rmixl_gpio_pin_write;
151 gp->gp_pin_ctl = rmixl_gpio_pin_ctl;
152
153 gba.gba_gc = gp;
154 gba.gba_pins = gpio->gpio_pins;
155 gba.gba_npins = __arraycount(gpio->gpio_pins);
156
157 dir = GPIO_READ(gpio, RMIXL_GPIO_IO_DIR);
158 valueout = GPIO_READ(gpio, RMIXL_GPIO_OUTPUT);
159 valuein = GPIO_READ(gpio, RMIXL_GPIO_INPUT);
160 for (pin = 0, mask = 1, pins = gpio->gpio_pins;
161 pin < RMIXL_GPIO_NSIGNALS; pin++, mask <<= 1, pins++) {
162 pins->pin_num = pin;
163 if (gpio->gpio_inuse_mask & mask) {
164 if ((gpio->gpio_inuse_mask & RMIXL_GPIO_INPUT_MASK))
165 pins->pin_caps = GPIO_PIN_INPUT;
166 } else {
167 int caps = 0;
168 if ((gpio->gpio_inuse_mask & RMIXL_GPIO_INPUT_MASK))
169 caps |= GPIO_PIN_INPUT;
170 if ((gpio->gpio_inuse_mask & RMIXL_GPIO_OUTPUT_MASK))
171 caps |= GPIO_PIN_INPUT;
172 pins->pin_caps = caps;
173 }
174 pins->pin_flags =
175 (dir & mask) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
176 pins->pin_state =
177 (((dir & mask) ? valueout : valuein) & mask)
178 ? GPIO_PIN_LOW
179 : GPIO_PIN_HIGH;
180 }
181
182 config_found(self, &gba, gpiobus_print, CFARGS_NONE);
183 }
184 #endif /* NGPIO > 0 */
185
186 int
gpio_match(device_t parent,cfdata_t cfdata,void * aux)187 gpio_match(device_t parent, cfdata_t cfdata, void *aux)
188 {
189 struct obio_attach_args *oa = aux;
190
191 if (oa->obio_addr == RMIXL_IO_DEV_GPIO) /* XXX XLS */
192 return 1;
193
194 return 0;
195 }
196
197 void
gpio_attach(device_t parent,device_t self,void * aux)198 gpio_attach(device_t parent, device_t self, void *aux)
199 {
200 struct obio_attach_args * const oa = aux;
201 struct gpio_softc * const gpio = device_private(self);
202 int error;
203
204 gpio->gpio_dev = self;
205
206 if (oa->obio_intr == OBIOCF_INTR_DEFAULT)
207 panic("\n%s: no intr assigned", device_xname(self));
208
209 if (oa->obio_size == OBIOCF_SIZE_DEFAULT)
210 oa->obio_size = 0x1000;
211
212 gpio->gpio_memt = oa->obio_eb_bst;
213 error = bus_space_map(oa->obio_eb_bst, oa->obio_addr, oa->obio_size,
214 0, &gpio->gpio_memh);
215
216 if (error) {
217 aprint_error(": failed to map register %#"
218 PRIxBUSSIZE "@%#" PRIxBUSADDR ": %d\n",
219 oa->obio_size, oa->obio_addr, error);
220 return;
221 }
222
223 #ifdef NOTYET
224 if (oa->obio_intr != OBIOCF_INTR_DEFAULT) {
225 gpio->gpio_ih = intr_establish(oa->obio_intr,
226 IPL_HIGH, IST_LEVEL, pic_handle_intr, &gpio->gpio_pic);
227 KASSERT(gpio->gpio_ih != NULL);
228 aprint_normal(", intr %d", oa->obio_intr);
229 }
230 #endif
231 aprint_normal("\n");
232 #if NGPIO > 0
233 config_interrupts(self, gpio_defer);
234 #endif
235 }
236