xref: /netbsd-src/sys/arch/mips/include/mips_param.h (revision 4d342c046e3288fb5a1edcd33cfec48c41c80664)
1 /*	$NetBSD: mips_param.h,v 1.47 2020/08/26 10:51:45 simonb Exp $	*/
2 
3 /*-
4  * Copyright (c) 2013 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 /*
29  * No reason this can't be common
30  */
31 #if defined(__MIPSEB__)
32 # if defined(__mips_n32) || defined(__mips_n64)
33 #  define	_MACHINE_ARCH	mips64eb
34 #  define	MACHINE_ARCH	"mips64eb"
35 #  define	_MACHINE32_ARCH	mipseb
36 #  define	MACHINE32_ARCH	"mipseb"
37 # else
38 #  define	_MACHINE_ARCH	mipseb
39 #  define	MACHINE_ARCH	"mipseb"
40 # endif
41 #elif defined(__MIPSEL__)
42 # if defined(__mips_n32) || defined(__mips_n64)
43 #  define	_MACHINE_ARCH	mips64el
44 #  define	MACHINE_ARCH	"mips64el"
45 #  define	_MACHINE32_ARCH	mipsel
46 #  define	MACHINE32_ARCH	"mipsel"
47 # else
48 #  define	_MACHINE_ARCH	mipsel
49 #  define	MACHINE_ARCH	"mipsel"
50 #endif
51 #else
52 #error neither __MIPSEL__ nor __MIPSEB__ are defined.
53 #endif
54 
55 /*
56  * Userland code should be using uname/sysctl to get MACHINE so simply
57  * export a generic MACHINE of "mips"
58  */
59 #ifndef _KERNEL
60 #undef MACHINE
61 #define	MACHINE "mips"
62 #endif
63 
64 #define	ALIGNBYTES32		(sizeof(double) - 1)
65 #define	ALIGN32(p)		(((uintptr_t)(p) + ALIGNBYTES32) &~ALIGNBYTES32)
66 
67 /*
68  * On mips, UPAGES is fixed by sys/arch/mips/mips/locore code
69  * to be the number of per-process-wired kernel-stack pages/PTES.
70  */
71 
72 #define	SSIZE		1		/* initial stack size/NBPG */
73 #define	SINCR		1		/* increment of stack/NBPG */
74 
75 #if (ENABLE_MIPS_16KB_PAGE + ENABLE_MIPS_8KB_PAGE + ENABLE_MIPS_4KB_PAGE) > 1
76 #error only one of ENABLE_MIPS_{4,8,16}KB_PAGE can be defined.
77 #endif
78 
79 #ifndef MSGBUFSIZE
80 #define	MSGBUFSIZE	NBPG		/* default message buffer size */
81 #endif
82 
83 /*
84  * Most MIPS have a cache line size of 32 bytes, but Cavium chips
85  * have a line size 128 bytes and we need to cover the larger size.
86  */
87 #define	COHERENCY_UNIT	128
88 #define	CACHE_LINE_SIZE	128
89 
90 #ifdef ENABLE_MIPS_16KB_PAGE
91 #define	PGSHIFT		14		/* LOG2(NBPG) */
92 #elif defined(ENABLE_MIPS_8KB_PAGE) \
93     || (!defined(ENABLE_MIPS_4KB_PAGE) && __mips >= 3)
94 #define	PGSHIFT		13		/* LOG2(NBPG) */
95 #else
96 #define	PGSHIFT		12		/* LOG2(NBPG) */
97 #endif
98 #define	NBPG		(1 << PGSHIFT)	/* bytes/page */
99 #define	PGOFSET		(NBPG - 1)	/* byte offset into page */
100 #define	PTPSHIFT	2
101 #define	PTPLENGTH	(PGSHIFT - PTPSHIFT)
102 #define	NPTEPG		(1 << PTPLENGTH)
103 
104 #define	SEGSHIFT	(PGSHIFT + PTPLENGTH)	/* LOG2(NBSEG) */
105 #define	NBSEG		(1 << SEGSHIFT)	/* bytes/segment */
106 #define	SEGOFSET	(NBSEG-1)	/* byte offset into segment */
107 
108 #ifdef _LP64
109 #define	SEGLENGTH	(PGSHIFT - 3)
110 #define	XSEGSHIFT	(SEGSHIFT + SEGLENGTH)	/* LOG2(NBXSEG) */
111 #define	NBXSEG		(1UL << XSEGSHIFT)	/* bytes/xsegment */
112 #define	XSEGOFSET	(NBXSEG - 1)	/* byte offset into xsegment */
113 #define	XSEGLENGTH	(PGSHIFT - 3)
114 #define	NXSEGPG		(1 << XSEGLENGTH)
115 #else
116 #define	SEGLENGTH	(31 - SEGSHIFT)
117 #endif
118 #define	NSEGPG		(1 << SEGLENGTH)
119 
120 #ifdef _LP64
121 #define	__MIN_USPACE	16384		/* LP64 needs a 16kB stack */
122 #else
123 /*
124  * Note for the non-LP64 case, cpu_switch_resume has the assumption
125  * that UPAGES == 2.  For MIPS-I we wire USPACE in TLB #0 and #1.
126  * For MIPS3+ we wire USPACE in the the TLB #0 pair.
127  */
128 #define	__MIN_USPACE	8192		/* otherwise use an 8kB stack */
129 #endif
130 #define	USPACE		MAX(__MIN_USPACE, PAGE_SIZE)
131 #define	UPAGES		(USPACE / PAGE_SIZE) /* number of pages for u-area */
132 #define	USPACE_ALIGN	USPACE		/* make sure it starts on a even VA */
133 #define	UPAGES_MAX	8		/* a (constant) max for userland use */
134 
135 /*
136  * Minimum and maximum sizes of the kernel malloc arena in PAGE_SIZE-sized
137  * logical pages.
138  */
139 #define	NKMEMPAGES_MIN_DEFAULT	((8 * 1024 * 1024) >> PAGE_SHIFT)
140 #define	NKMEMPAGES_MAX_DEFAULT	((128 * 1024 * 1024) >> PAGE_SHIFT)
141 
142 /*
143  * Mach derived conversion macros
144  */
145 #define	mips_round_page(x)	((((uintptr_t)(x)) + NBPG - 1) & ~(NBPG-1))
146 #define	mips_trunc_page(x)	((uintptr_t)(x) & ~(NBPG-1))
147 #define	mips_btop(x)		((paddr_t)(x) >> PGSHIFT)
148 #define	mips_ptob(x)		((paddr_t)(x) << PGSHIFT)
149 
150 #ifdef __MIPSEL__
151 #define	MID_MACHINE	MID_PMAX	/* MID_PMAX (little-endian) */
152 #endif
153 #ifdef __MIPSEB__
154 #define	MID_MACHINE	MID_MIPS	/* MID_MIPS (big-endian) */
155 #endif
156 
157 /*
158  * Constants related to network buffer management.
159  * MCLBYTES must be no larger than NBPG (the software page size), and,
160  * on machines that exchange pages of input or output buffers with mbuf
161  * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple
162  * of the hardware page size.
163  */
164 #ifndef MSIZE
165 #ifdef _LP64
166 #define	MSIZE		512		/* size of an mbuf */
167 #else
168 #define	MSIZE		256		/* size of an mbuf */
169 #endif
170 
171 #ifndef MCLSHIFT
172 # define MCLSHIFT	11		/* convert bytes to m_buf clusters */
173 #endif	/* MCLSHIFT */
174 
175 #define	MCLBYTES	(1 << MCLSHIFT)	/* size of a m_buf cluster */
176 
177 #endif
178