xref: /netbsd-src/sys/arch/luna68k/dev/lunafb.c (revision 80d9064ac03cbb6a4174695f0d5b237c8766d3d0)
1 /* $NetBSD: lunafb.c,v 1.35 2014/07/25 16:40:12 tsutsui Exp $ */
2 
3 /*-
4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Tohru Nishimura.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
33 
34 __KERNEL_RCSID(0, "$NetBSD: lunafb.c,v 1.35 2014/07/25 16:40:12 tsutsui Exp $");
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/conf.h>
39 #include <sys/device.h>
40 #include <sys/ioctl.h>
41 #include <sys/kmem.h>
42 #include <sys/mman.h>
43 #include <sys/proc.h>
44 #include <sys/tty.h>
45 #include <sys/errno.h>
46 #include <sys/buf.h>
47 
48 #include <uvm/uvm_extern.h>
49 
50 #include <dev/wscons/wsconsio.h>
51 #include <dev/wscons/wsdisplayvar.h>
52 #include <dev/rasops/rasops.h>
53 
54 #include <machine/cpu.h>
55 #include <machine/autoconf.h>
56 
57 #include <arch/luna68k/dev/omrasopsvar.h>
58 
59 #include "ioconf.h"
60 
61 struct bt454 {
62 	volatile uint8_t bt_addr;	/* map address register */
63 	volatile uint8_t bt_cmap;	/* colormap data register */
64 };
65 
66 struct bt458 {
67 	volatile uint8_t bt_addr;	/* map address register */
68 	uint8_t          pad0[3];
69 	volatile uint8_t bt_cmap;	/* colormap data register */
70 	uint8_t          pad1[3];
71 	volatile uint8_t bt_ctrl;	/* control register */
72 	uint8_t          pad2[3];
73 	volatile uint8_t bt_omap;	/* overlay (cursor) map register */
74 	uint8_t          pad3[3];
75 };
76 
77 #define	OMFB_RFCNT	0xB1000000	/* video h-origin/v-origin */
78 #define	OMFB_PLANEMASK	0xB1040000	/* planemask register */
79 #define	OMFB_FB_WADDR	0xB1080008	/* common plane */
80 #define	OMFB_FB_RADDR	0xB10C0008	/* plane #0 */
81 #define	OMFB_ROPFUNC	0xB12C0000	/* ROP function code */
82 #define	OMFB_RAMDAC	0xC1100000	/* Bt454/Bt458 RAMDAC */
83 #define	OMFB_SIZE	(0xB1300000 - 0xB1080000 + PAGE_SIZE)
84 
85 struct hwcmap {
86 #define CMAP_SIZE 256
87 	uint8_t r[CMAP_SIZE];
88 	uint8_t g[CMAP_SIZE];
89 	uint8_t b[CMAP_SIZE];
90 };
91 
92 static const struct {
93 	uint8_t r;
94 	uint8_t g;
95 	uint8_t b;
96 } ansicmap[16] = {
97 	{    0,    0,    0},
98 	{ 0x80,    0,    0},
99 	{    0, 0x80,    0},
100 	{ 0x80, 0x80,    0},
101 	{    0,    0, 0x80},
102 	{ 0x80,    0, 0x80},
103 	{    0, 0x80, 0x80},
104 	{ 0xc0, 0xc0, 0xc0},
105 	{ 0x80, 0x80, 0x80},
106 	{ 0xff,    0,    0},
107 	{    0, 0xff,    0},
108 	{ 0xff, 0xff,    0},
109 	{    0,    0, 0xff},
110 	{ 0xff,    0, 0xff},
111 	{    0, 0xff, 0xff},
112 	{ 0xff, 0xff, 0xff},
113 };
114 
115 struct om_hwdevconfig {
116 	int	dc_wid;			/* width of frame buffer */
117 	int	dc_ht;			/* height of frame buffer */
118 	int	dc_depth;		/* depth, bits per pixel */
119 	int	dc_rowbytes;		/* bytes in a FB scan line */
120 	int	dc_cmsize;		/* colormap size */
121 	struct hwcmap dc_cmap;		/* software copy of colormap */
122 	vaddr_t	dc_videobase;		/* base of flat frame buffer */
123 	struct rasops_info dc_ri;	/* raster blitter variables */
124 };
125 
126 struct omfb_softc {
127 	device_t sc_dev;		/* base device */
128 	struct om_hwdevconfig *sc_dc;	/* device configuration */
129 	int sc_nscreens;
130 	int sc_mode;
131 };
132 
133 static int  omgetcmap(struct omfb_softc *, struct wsdisplay_cmap *);
134 static int  omsetcmap(struct omfb_softc *, struct wsdisplay_cmap *);
135 
136 static struct om_hwdevconfig omfb_console_dc;
137 static void omfb_resetcmap(struct om_hwdevconfig *);
138 static void omfb_getdevconfig(paddr_t, struct om_hwdevconfig *);
139 
140 static struct wsscreen_descr omfb_stdscreen = {
141 	.name = "std"
142 };
143 
144 static const struct wsscreen_descr *_omfb_scrlist[] = {
145 	&omfb_stdscreen,
146 };
147 
148 static const struct wsscreen_list omfb_screenlist = {
149 	sizeof(_omfb_scrlist) / sizeof(struct wsscreen_descr *), _omfb_scrlist
150 };
151 
152 static int   omfbioctl(void *, void *, u_long, void *, int, struct lwp *);
153 static paddr_t omfbmmap(void *, void *, off_t, int);
154 static int   omfb_alloc_screen(void *, const struct wsscreen_descr *,
155 			       void **, int *, int *, long *);
156 static void  omfb_free_screen(void *, void *);
157 static int   omfb_show_screen(void *, void *, int,
158 			      void (*) (void *, int, int), void *);
159 
160 static const struct wsdisplay_accessops omfb_accessops = {
161 	.ioctl        = omfbioctl,
162 	.mmap         = omfbmmap,
163 	.alloc_screen = omfb_alloc_screen,
164 	.free_screen  = omfb_free_screen,
165 	.show_screen  = omfb_show_screen,
166 	.load_font    = NULL,
167 	.pollc        = NULL,
168 	.scroll       = NULL
169 };
170 
171 static int  omfbmatch(device_t, cfdata_t, void *);
172 static void omfbattach(device_t, device_t, void *);
173 
174 CFATTACH_DECL_NEW(fb, sizeof(struct omfb_softc),
175     omfbmatch, omfbattach, NULL, NULL);
176 
177 extern int hwplanemask;	/* hardware planemask; retrieved at boot */
178 
179 static int omfb_console;
180 int  omfb_cnattach(void);
181 
182 static int
183 omfbmatch(device_t parent, cfdata_t cf, void *aux)
184 {
185 	struct mainbus_attach_args *ma = aux;
186 
187 	if (strcmp(ma->ma_name, fb_cd.cd_name))
188 		return 0;
189 #if 0	/* XXX badaddr() bombs if no framebuffer is installed */
190 	if (badaddr((void *)ma->ma_addr, 4))
191 		return 0;
192 #else
193 	if (hwplanemask == 0)
194 		return 0;
195 #endif
196 	return 1;
197 }
198 
199 static void
200 omfbattach(device_t parent, device_t self, void *args)
201 {
202 	struct omfb_softc *sc = device_private(self);
203 	struct wsemuldisplaydev_attach_args waa;
204 
205 	sc->sc_dev = self;
206 
207 	if (omfb_console) {
208 		sc->sc_dc = &omfb_console_dc;
209 		sc->sc_nscreens = 1;
210 	} else {
211 		sc->sc_dc = kmem_zalloc(sizeof(struct om_hwdevconfig),
212 		    KM_SLEEP);
213 		omfb_getdevconfig(OMFB_FB_WADDR, sc->sc_dc);
214 	}
215 	aprint_normal(": %d x %d, %dbpp\n", sc->sc_dc->dc_wid, sc->sc_dc->dc_ht,
216 	    sc->sc_dc->dc_depth);
217 
218 	sc->sc_mode = WSDISPLAYIO_MODE_EMUL;
219 	waa.console = omfb_console;
220 	waa.scrdata = &omfb_screenlist;
221 	waa.accessops = &omfb_accessops;
222 	waa.accesscookie = sc;
223 
224 	config_found(self, &waa, wsemuldisplaydevprint);
225 }
226 
227 /* EXPORT */ int
228 omfb_cnattach(void)
229 {
230 	struct om_hwdevconfig *dc = &omfb_console_dc;
231 	struct rasops_info *ri = &dc->dc_ri;
232 	long defattr;
233 
234 	omfb_getdevconfig(OMFB_FB_WADDR, dc);
235 	(*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr);
236 	wsdisplay_cnattach(&omfb_stdscreen, ri, 0, 0, defattr);
237 	omfb_console = 1;
238 	return 0;
239 }
240 
241 static int
242 omfbioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l)
243 {
244 	struct omfb_softc *sc = v;
245 	struct om_hwdevconfig *dc = sc->sc_dc;
246 	int new_mode;
247 
248 	switch (cmd) {
249 	case WSDISPLAYIO_GTYPE:
250 		*(u_int *)data = WSDISPLAY_TYPE_LUNA;
251 		return 0;
252 
253 	case WSDISPLAYIO_GINFO:
254 #define	wsd_fbip ((struct wsdisplay_fbinfo *)data)
255 		wsd_fbip->height = dc->dc_ht;
256 		wsd_fbip->width = dc->dc_wid;
257 		wsd_fbip->depth = dc->dc_depth;
258 		wsd_fbip->cmsize = dc->dc_cmsize;
259 #undef fbt
260 		return 0;
261 
262 	case WSDISPLAYIO_LINEBYTES:
263 		*(u_int *)data = dc->dc_rowbytes;
264 		return 0;
265 
266 	case WSDISPLAYIO_GETCMAP:
267 		return omgetcmap(sc, (struct wsdisplay_cmap *)data);
268 
269 	case WSDISPLAYIO_PUTCMAP:
270 		return omsetcmap(sc, (struct wsdisplay_cmap *)data);
271 
272 	case WSDISPLAYIO_SMODE:
273 		new_mode = *(int *)data;
274 		if (new_mode != sc->sc_mode) {
275 			sc->sc_mode = new_mode;
276 			if (new_mode == WSDISPLAYIO_MODE_EMUL)
277 				omfb_resetcmap(dc);
278 		}
279 		return 0;
280 
281 	case WSDISPLAYIO_SVIDEO:
282 	case WSDISPLAYIO_GVIDEO:
283 	case WSDISPLAYIO_GCURPOS:
284 	case WSDISPLAYIO_SCURPOS:
285 	case WSDISPLAYIO_GCURMAX:
286 	case WSDISPLAYIO_GCURSOR:
287 	case WSDISPLAYIO_SCURSOR:
288 		break;
289 	}
290 	return EPASSTHROUGH;
291 }
292 
293 /*
294  * Return the address that would map the given device at the given
295  * offset, allowing for the given protection, or return -1 for error.
296  */
297 static paddr_t
298 omfbmmap(void *v, void *vs, off_t offset, int prot)
299 {
300 	struct omfb_softc *sc = v;
301 	struct om_hwdevconfig *dc = sc->sc_dc;
302 	paddr_t cookie = -1;
303 
304 	switch (sc->sc_mode) {
305 #if 0
306 	case WSDISPLAYIO_MODE_MAPPED:
307 		if (offset >= 0 && offset < OMFB_SIZE)
308 			cookie = m68k_btop(m68k_trunc_page(dc->dc_videobase) +
309 			    offset);
310 		break;
311 #endif
312 	case WSDISPLAYIO_MODE_DUMBFB:
313 		if (offset >= 0 &&
314 		    offset < dc->dc_rowbytes * dc->dc_ht * dc->dc_depth)
315 			cookie = m68k_btop(m68k_trunc_page(OMFB_FB_RADDR) +
316 			    offset);
317 		break;
318 	}
319 
320 	return cookie;
321 }
322 
323 static int
324 omgetcmap(struct omfb_softc *sc, struct wsdisplay_cmap *p)
325 {
326 	u_int index = p->index, count = p->count;
327 	int cmsize, error;
328 
329 	cmsize = sc->sc_dc->dc_cmsize;
330 	if (index >= cmsize || count > cmsize - index)
331 		return EINVAL;
332 
333 	error = copyout(&sc->sc_dc->dc_cmap.r[index], p->red, count);
334 	if (error)
335 		return error;
336 	error = copyout(&sc->sc_dc->dc_cmap.g[index], p->green, count);
337 	if (error)
338 		return error;
339 	error = copyout(&sc->sc_dc->dc_cmap.b[index], p->blue, count);
340 	return error;
341 }
342 
343 static int
344 omsetcmap(struct omfb_softc *sc, struct wsdisplay_cmap *p)
345 {
346 	struct hwcmap cmap;
347 	u_int index = p->index, count = p->count;
348 	int cmsize, i, error;
349 
350 	cmsize = sc->sc_dc->dc_cmsize;
351 	if (index >= cmsize || (index + count) > cmsize)
352 		return (EINVAL);
353 
354 	error = copyin(p->red, &cmap.r[index], count);
355 	if (error)
356 		return error;
357 	error = copyin(p->green, &cmap.g[index], count);
358 	if (error)
359 		return error;
360 	error = copyin(p->blue, &cmap.b[index], count);
361 	if (error)
362 		return error;
363 
364 	memcpy(&sc->sc_dc->dc_cmap.r[index], &cmap.r[index], count);
365 	memcpy(&sc->sc_dc->dc_cmap.g[index], &cmap.g[index], count);
366 	memcpy(&sc->sc_dc->dc_cmap.b[index], &cmap.b[index], count);
367 	if (hwplanemask == 0x0f) {
368 		struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC;
369 		odac->bt_addr = index;
370 		for (i = index; i < index + count; i++) {
371 			odac->bt_cmap = sc->sc_dc->dc_cmap.r[i];
372 			odac->bt_cmap = sc->sc_dc->dc_cmap.g[i];
373 			odac->bt_cmap = sc->sc_dc->dc_cmap.b[i];
374 		}
375 	} else if (hwplanemask == 0xff) {
376 		struct bt458 *ndac = (struct bt458 *)OMFB_RAMDAC;
377 		ndac->bt_addr = index;
378 		for (i = index; i < index + count; i++) {
379 			ndac->bt_cmap = sc->sc_dc->dc_cmap.r[i];
380 			ndac->bt_cmap = sc->sc_dc->dc_cmap.g[i];
381 			ndac->bt_cmap = sc->sc_dc->dc_cmap.b[i];
382 		}
383 	}
384 	return 0;
385 }
386 
387 static void
388 omfb_resetcmap(struct om_hwdevconfig *dc)
389 {
390 	int i;
391 
392 	if (hwplanemask == 0x01) {
393 		struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC;
394 
395 		/*
396 		 * On 1bpp framebuffer, only plane P0 has framebuffer memory
397 		 * and other planes seems pulled up, i.e. always 1.
398 		 * Set white only for a palette (P0,P1,P2,P3) = (1,1,1,1).
399 		 */
400 		odac->bt_addr = 0;
401 		for (i = 0; i < 15; i++) {
402 			odac->bt_cmap = dc->dc_cmap.r[i] = 0;
403 			odac->bt_cmap = dc->dc_cmap.g[i] = 0;
404 			odac->bt_cmap = dc->dc_cmap.b[i] = 0;
405 		}
406 		/*
407 		 * The B/W video connector is connected to IOG of Bt454,
408 		 * and IOR and IOB are unused.
409 		 */
410 		odac->bt_cmap = dc->dc_cmap.r[15] = 0;
411 		odac->bt_cmap = dc->dc_cmap.g[15] = 255;
412 		odac->bt_cmap = dc->dc_cmap.b[15] = 0;
413 	} else if (hwplanemask == 0x0f) {
414 		struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC;
415 
416 		odac->bt_addr = 0;
417 		for (i = 0; i < 16; i++) {
418 			odac->bt_cmap = dc->dc_cmap.r[i] = ansicmap[i].r;
419 			odac->bt_cmap = dc->dc_cmap.g[i] = ansicmap[i].g;
420 			odac->bt_cmap = dc->dc_cmap.b[i] = ansicmap[i].b;
421 		}
422 	} else if (hwplanemask == 0xff) {
423 		struct bt458 *ndac = (struct bt458 *)OMFB_RAMDAC;
424 
425 		/*
426 		 * Initialize the Bt458.  When we write to control registers,
427 		 * the address is not incremented automatically. So we specify
428 		 * it ourselves for each control register.
429 		 */
430 		ndac->bt_addr = 0x04;
431 		ndac->bt_ctrl = 0xff; /* all planes will be read */
432 		ndac->bt_addr = 0x05;
433 		ndac->bt_ctrl = 0x00; /* all planes have non-blink */
434 		ndac->bt_addr = 0x06;
435 		ndac->bt_ctrl = 0x40; /* pallete enabled, ovly plane disabled */
436 		ndac->bt_addr = 0x07;
437 		ndac->bt_ctrl = 0x00; /* no test mode */
438 
439 		/*
440 		 * Set ANSI 16 colors.  We only supports 4bpp console right
441 		 * now, repeat 16 colors in 256 colormap.
442 		 */
443 		ndac->bt_addr = 0;
444 		for (i = 0; i < 256; i++) {
445 			ndac->bt_cmap = dc->dc_cmap.r[i] = ansicmap[i % 16].r;
446 			ndac->bt_cmap = dc->dc_cmap.g[i] = ansicmap[i % 16].g;
447 			ndac->bt_cmap = dc->dc_cmap.b[i] = ansicmap[i % 16].b;
448 		}
449 	}
450 }
451 
452 static void
453 omfb_getdevconfig(paddr_t paddr, struct om_hwdevconfig *dc)
454 {
455 	int bpp, i;
456 	struct rasops_info *ri;
457 	union {
458 		struct { short h, v; } p;
459 		uint32_t u;
460 	} rfcnt;
461 
462 	switch (hwplanemask) {
463 	case 0xff:
464 		bpp = 8;	/* XXX check monochrome bit in DIPSW */
465 		break;
466 	default:
467 	case 0x0f:
468 		bpp = 4;	/* XXX check monochrome bit in DIPSW */
469 		break;
470 	case 1:
471 		bpp = 1;
472 		break;
473 	}
474 	dc->dc_wid = 1280;
475 	dc->dc_ht = 1024;
476 	dc->dc_depth = bpp;
477 	dc->dc_rowbytes = 2048 / 8;
478 	dc->dc_cmsize = (bpp == 1) ? 0 : 1 << bpp;
479 	dc->dc_videobase = paddr;
480 
481 	omfb_resetcmap(dc);
482 
483 	/* adjust h/v origin on screen */
484 	rfcnt.p.h = 7;
485 	rfcnt.p.v = -27;
486 	/* single write of 0x007ffe6 */
487 	*(volatile uint32_t *)OMFB_RFCNT = rfcnt.u;
488 
489 	/* clear the screen */
490 	*(volatile uint32_t *)OMFB_PLANEMASK = 0xff;
491 	((volatile uint32_t *)OMFB_ROPFUNC)[5] = ~0;	/* ROP copy */
492 	for (i = 0; i < dc->dc_ht * dc->dc_rowbytes / sizeof(uint32_t); i++)
493 		*((volatile uint32_t *)dc->dc_videobase + i) = 0;
494 	*(volatile uint32_t *)OMFB_PLANEMASK = 0x01;
495 
496 	/* initialize the raster */
497 	ri = &dc->dc_ri;
498 	ri->ri_width = dc->dc_wid;
499 	ri->ri_height = dc->dc_ht;
500 	ri->ri_depth = 1;       /* since planes are independently addressed */
501 	ri->ri_stride = dc->dc_rowbytes;
502 	ri->ri_bits = (void *)dc->dc_videobase;
503 	ri->ri_flg = RI_CENTER;
504 	if (dc == &omfb_console_dc)
505 		ri->ri_flg |= RI_NO_AUTO;
506 	ri->ri_hw = dc;
507 
508 	if (bpp == 4 || bpp == 8)
509 		omrasops4_init(ri, 34, 80);
510 	else
511 		omrasops1_init(ri, 34, 80);
512 
513 	omfb_stdscreen.nrows = ri->ri_rows;
514 	omfb_stdscreen.ncols = ri->ri_cols;
515 	omfb_stdscreen.textops = &ri->ri_ops;
516 	omfb_stdscreen.capabilities = ri->ri_caps;
517 	omfb_stdscreen.fontwidth = ri->ri_font->fontwidth;
518 	omfb_stdscreen.fontheight = ri->ri_font->fontheight;
519 }
520 
521 static int
522 omfb_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep,
523     int *curxp, int *curyp, long *attrp)
524 {
525 	struct omfb_softc *sc = v;
526 	struct rasops_info *ri = &sc->sc_dc->dc_ri;
527 
528 	if (sc->sc_nscreens > 0)
529 		return ENOMEM;
530 
531 	*cookiep = ri;
532 	*curxp = 0;
533 	*curyp = 0;
534 	(*ri->ri_ops.allocattr)(ri, 0, 0, 0, attrp);
535 	sc->sc_nscreens++;
536 	return 0;
537 }
538 
539 static void
540 omfb_free_screen(void *v, void *cookie)
541 {
542 	struct omfb_softc *sc = v;
543 
544 	if (sc->sc_dc == &omfb_console_dc)
545 		panic("omfb_free_screen: console");
546 
547 	sc->sc_nscreens--;
548 }
549 
550 static int
551 omfb_show_screen(void *v, void *cookie, int waitok,
552     void (*cb)(void *, int, int), void *cbarg)
553 {
554 
555 	return 0;
556 }
557