1 /* $NetBSD: lunafb.c,v 1.49 2022/10/03 17:42:35 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Tohru Nishimura.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
33
34 __KERNEL_RCSID(0, "$NetBSD: lunafb.c,v 1.49 2022/10/03 17:42:35 tsutsui Exp $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/conf.h>
39 #include <sys/device.h>
40 #include <sys/ioctl.h>
41 #include <sys/kmem.h>
42 #include <sys/mman.h>
43 #include <sys/proc.h>
44 #include <sys/tty.h>
45 #include <sys/errno.h>
46 #include <sys/buf.h>
47
48 #include <uvm/uvm_extern.h>
49
50 #include <dev/wscons/wsconsio.h>
51 #include <dev/wscons/wsdisplayvar.h>
52 #include <dev/rasops/rasops.h>
53
54 #include <machine/cpu.h>
55 #include <machine/autoconf.h>
56
57 #include <arch/luna68k/dev/omrasopsvar.h>
58
59 #include "ioconf.h"
60
61 struct bt454 {
62 volatile uint8_t bt_addr; /* map address register */
63 volatile uint8_t bt_cmap; /* colormap data register */
64 };
65
66 struct bt458 {
67 volatile uint8_t bt_addr; /* map address register */
68 uint8_t pad0[3];
69 volatile uint8_t bt_cmap; /* colormap data register */
70 uint8_t pad1[3];
71 volatile uint8_t bt_ctrl; /* control register */
72 uint8_t pad2[3];
73 volatile uint8_t bt_omap; /* overlay (cursor) map register */
74 uint8_t pad3[3];
75 };
76
77 #define OMFB_RFCNT BMAP_RFCNT /* video h-origin/v-origin */
78 #define OMFB_RAMDAC BMAP_PALLET2 /* Bt454/Bt458 RAMDAC */
79 #define OMFB_FB_WADDR (BMAP_BMP + 8) /* common bitmap plane */
80 #define OMFB_FB_RADDR (BMAP_BMAP0 + 8)/* bitmap plane #0 */
81
82 #define OMFB_SIZE (BMAP_FN0 - BMAP_BMP + PAGE_SIZE)
83
84 struct hwcmap {
85 #define CMAP_SIZE 256
86 uint8_t r[CMAP_SIZE];
87 uint8_t g[CMAP_SIZE];
88 uint8_t b[CMAP_SIZE];
89 };
90
91 static const struct {
92 uint8_t r;
93 uint8_t g;
94 uint8_t b;
95 } ansicmap[16] = {
96 { 0, 0, 0},
97 { 0x80, 0, 0},
98 { 0, 0x80, 0},
99 { 0x80, 0x80, 0},
100 { 0, 0, 0x80},
101 { 0x80, 0, 0x80},
102 { 0, 0x80, 0x80},
103 { 0xc0, 0xc0, 0xc0},
104 { 0x80, 0x80, 0x80},
105 { 0xff, 0, 0},
106 { 0, 0xff, 0},
107 { 0xff, 0xff, 0},
108 { 0, 0, 0xff},
109 { 0xff, 0, 0xff},
110 { 0, 0xff, 0xff},
111 { 0xff, 0xff, 0xff},
112 };
113
114 struct om_hwdevconfig {
115 int dc_wid; /* width of frame buffer */
116 int dc_ht; /* height of frame buffer */
117 int dc_depth; /* depth, bits per pixel */
118 int dc_rowbytes; /* bytes in a FB scan line */
119 int dc_cmsize; /* colormap size */
120 struct hwcmap dc_cmap; /* software copy of colormap */
121 vaddr_t dc_videobase; /* base of flat frame buffer */
122 struct rasops_info dc_ri; /* raster blitter variables */
123 };
124
125 struct omfb_softc {
126 device_t sc_dev; /* base device */
127 struct om_hwdevconfig *sc_dc; /* device configuration */
128 int sc_nscreens;
129 int sc_mode;
130 };
131
132 static int omgetcmap(struct omfb_softc *, struct wsdisplay_cmap *);
133 static int omsetcmap(struct omfb_softc *, struct wsdisplay_cmap *);
134
135 static struct om_hwdevconfig omfb_console_dc;
136 static void omfb_resetcmap(struct om_hwdevconfig *);
137 static void omfb_getdevconfig(paddr_t, struct om_hwdevconfig *);
138
139 static struct wsscreen_descr omfb_stdscreen = {
140 .name = "std"
141 };
142
143 static const struct wsscreen_descr *_omfb_scrlist[] = {
144 &omfb_stdscreen,
145 };
146
147 static const struct wsscreen_list omfb_screenlist = {
148 sizeof(_omfb_scrlist) / sizeof(struct wsscreen_descr *), _omfb_scrlist
149 };
150
151 static int omfbioctl(void *, void *, u_long, void *, int, struct lwp *);
152 static paddr_t omfbmmap(void *, void *, off_t, int);
153 static int omfb_alloc_screen(void *, const struct wsscreen_descr *,
154 void **, int *, int *, long *);
155 static void omfb_free_screen(void *, void *);
156 static int omfb_show_screen(void *, void *, int,
157 void (*) (void *, int, int), void *);
158
159 static const struct wsdisplay_accessops omfb_accessops = {
160 .ioctl = omfbioctl,
161 .mmap = omfbmmap,
162 .alloc_screen = omfb_alloc_screen,
163 .free_screen = omfb_free_screen,
164 .show_screen = omfb_show_screen,
165 .load_font = NULL,
166 .pollc = NULL,
167 .scroll = NULL
168 };
169
170 static int omfbmatch(device_t, cfdata_t, void *);
171 static void omfbattach(device_t, device_t, void *);
172
173 CFATTACH_DECL_NEW(fb, sizeof(struct omfb_softc),
174 omfbmatch, omfbattach, NULL, NULL);
175
176 extern int hwplanemask; /* hardware planemask; retrieved at boot */
177
178 static int omfb_console;
179 int omfb_cnattach(void);
180
181 static int
omfbmatch(device_t parent,cfdata_t cf,void * aux)182 omfbmatch(device_t parent, cfdata_t cf, void *aux)
183 {
184 struct mainbus_attach_args *ma = aux;
185
186 if (strcmp(ma->ma_name, fb_cd.cd_name))
187 return 0;
188 #if 0 /* XXX badaddr() bombs if no framebuffer is installed */
189 if (badaddr((void *)ma->ma_addr, 4))
190 return 0;
191 #else
192 if (hwplanemask == 0)
193 return 0;
194 #endif
195 return 1;
196 }
197
198 static void
omfbattach(device_t parent,device_t self,void * args)199 omfbattach(device_t parent, device_t self, void *args)
200 {
201 struct omfb_softc *sc = device_private(self);
202 struct wsemuldisplaydev_attach_args waa;
203
204 sc->sc_dev = self;
205
206 if (omfb_console) {
207 sc->sc_dc = &omfb_console_dc;
208 sc->sc_nscreens = 1;
209 } else {
210 sc->sc_dc = kmem_zalloc(sizeof(struct om_hwdevconfig),
211 KM_SLEEP);
212 omfb_getdevconfig(OMFB_FB_WADDR, sc->sc_dc);
213 }
214 aprint_normal(": %d x %d, %dbpp\n", sc->sc_dc->dc_wid, sc->sc_dc->dc_ht,
215 sc->sc_dc->dc_depth);
216
217 sc->sc_mode = WSDISPLAYIO_MODE_EMUL;
218 waa.console = omfb_console;
219 waa.scrdata = &omfb_screenlist;
220 waa.accessops = &omfb_accessops;
221 waa.accesscookie = sc;
222
223 config_found(self, &waa, wsemuldisplaydevprint, CFARGS_NONE);
224 }
225
226 /* EXPORT */ int
omfb_cnattach(void)227 omfb_cnattach(void)
228 {
229 struct om_hwdevconfig *dc = &omfb_console_dc;
230 struct rasops_info *ri = &dc->dc_ri;
231 long defattr;
232
233 omfb_getdevconfig(OMFB_FB_WADDR, dc);
234 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr);
235 wsdisplay_cnattach(&omfb_stdscreen, ri, 0, 0, defattr);
236 omfb_console = 1;
237 return 0;
238 }
239
240 static int
omfbioctl(void * v,void * vs,u_long cmd,void * data,int flag,struct lwp * l)241 omfbioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l)
242 {
243 struct omfb_softc *sc = v;
244 struct om_hwdevconfig *dc = sc->sc_dc;
245 int new_mode;
246
247 switch (cmd) {
248 case WSDISPLAYIO_GTYPE:
249 *(u_int *)data = WSDISPLAY_TYPE_LUNA;
250 return 0;
251
252 case WSDISPLAYIO_GINFO:
253 #define wsd_fbip ((struct wsdisplay_fbinfo *)data)
254 wsd_fbip->height = dc->dc_ht;
255 wsd_fbip->width = dc->dc_wid;
256 wsd_fbip->depth = dc->dc_depth;
257 wsd_fbip->cmsize = dc->dc_cmsize;
258 #undef wsd_fbip
259 return 0;
260
261 case WSDISPLAYIO_LINEBYTES:
262 *(u_int *)data = dc->dc_rowbytes;
263 return 0;
264
265 case WSDISPLAYIO_GETCMAP:
266 return omgetcmap(sc, (struct wsdisplay_cmap *)data);
267
268 case WSDISPLAYIO_PUTCMAP:
269 return omsetcmap(sc, (struct wsdisplay_cmap *)data);
270
271 case WSDISPLAYIO_SMODE:
272 new_mode = *(int *)data;
273 if (new_mode != sc->sc_mode) {
274 sc->sc_mode = new_mode;
275 if (new_mode == WSDISPLAYIO_MODE_EMUL)
276 omfb_resetcmap(dc);
277 }
278 return 0;
279
280 case WSDISPLAYIO_SVIDEO:
281 case WSDISPLAYIO_GVIDEO:
282 case WSDISPLAYIO_GCURPOS:
283 case WSDISPLAYIO_SCURPOS:
284 case WSDISPLAYIO_GCURMAX:
285 case WSDISPLAYIO_GCURSOR:
286 case WSDISPLAYIO_SCURSOR:
287 break;
288 }
289 return EPASSTHROUGH;
290 }
291
292 /*
293 * Return the address that would map the given device at the given
294 * offset, allowing for the given protection, or return -1 for error.
295 */
296 static paddr_t
omfbmmap(void * v,void * vs,off_t offset,int prot)297 omfbmmap(void *v, void *vs, off_t offset, int prot)
298 {
299 struct omfb_softc *sc = v;
300 struct om_hwdevconfig *dc = sc->sc_dc;
301 paddr_t cookie = -1;
302
303 switch (sc->sc_mode) {
304 #if 0
305 case WSDISPLAYIO_MODE_MAPPED:
306 if (offset >= 0 && offset < OMFB_SIZE)
307 cookie = m68k_btop(m68k_trunc_page(dc->dc_videobase) +
308 offset);
309 break;
310 #endif
311 case WSDISPLAYIO_MODE_DUMBFB:
312 if (offset >= 0 &&
313 offset < m68k_page_offset(OMFB_FB_RADDR) +
314 dc->dc_rowbytes * dc->dc_ht * dc->dc_depth)
315 cookie = m68k_btop(m68k_trunc_page(OMFB_FB_RADDR) +
316 offset);
317 break;
318 }
319
320 return cookie;
321 }
322
323 static int
omgetcmap(struct omfb_softc * sc,struct wsdisplay_cmap * p)324 omgetcmap(struct omfb_softc *sc, struct wsdisplay_cmap *p)
325 {
326 u_int index = p->index, count = p->count;
327 u_int cmsize;
328 int error;
329
330 cmsize = sc->sc_dc->dc_cmsize;
331 if (index >= cmsize || count > cmsize - index)
332 return EINVAL;
333
334 error = copyout(&sc->sc_dc->dc_cmap.r[index], p->red, count);
335 if (error != 0)
336 return error;
337 error = copyout(&sc->sc_dc->dc_cmap.g[index], p->green, count);
338 if (error != 0)
339 return error;
340 error = copyout(&sc->sc_dc->dc_cmap.b[index], p->blue, count);
341 if (error != 0)
342 return error;
343
344 return 0;
345 }
346
347 static int
omsetcmap(struct omfb_softc * sc,struct wsdisplay_cmap * p)348 omsetcmap(struct omfb_softc *sc, struct wsdisplay_cmap *p)
349 {
350 struct hwcmap cmap;
351 u_int index = p->index, count = p->count;
352 u_int cmsize;
353 int i, error;
354
355 cmsize = sc->sc_dc->dc_cmsize;
356
357 if (index >= cmsize || count > cmsize - index)
358 return EINVAL;
359
360 error = copyin(p->red, &cmap.r[index], count);
361 if (error != 0)
362 return error;
363 error = copyin(p->green, &cmap.g[index], count);
364 if (error != 0)
365 return error;
366 error = copyin(p->blue, &cmap.b[index], count);
367 if (error != 0)
368 return error;
369
370 memcpy(&sc->sc_dc->dc_cmap.r[index], &cmap.r[index], count);
371 memcpy(&sc->sc_dc->dc_cmap.g[index], &cmap.g[index], count);
372 memcpy(&sc->sc_dc->dc_cmap.b[index], &cmap.b[index], count);
373 if (hwplanemask == 0x0f) {
374 struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC;
375 odac->bt_addr = index;
376 for (i = index; i < index + count; i++) {
377 odac->bt_cmap = sc->sc_dc->dc_cmap.r[i];
378 odac->bt_cmap = sc->sc_dc->dc_cmap.g[i];
379 odac->bt_cmap = sc->sc_dc->dc_cmap.b[i];
380 }
381 } else if (hwplanemask == 0xff) {
382 struct bt458 *ndac = (struct bt458 *)OMFB_RAMDAC;
383 ndac->bt_addr = index;
384 for (i = index; i < index + count; i++) {
385 ndac->bt_cmap = sc->sc_dc->dc_cmap.r[i];
386 ndac->bt_cmap = sc->sc_dc->dc_cmap.g[i];
387 ndac->bt_cmap = sc->sc_dc->dc_cmap.b[i];
388 }
389 }
390 return 0;
391 }
392
393 static void
omfb_resetcmap(struct om_hwdevconfig * dc)394 omfb_resetcmap(struct om_hwdevconfig *dc)
395 {
396 int i;
397
398 if (hwplanemask == 0x01) {
399 struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC;
400
401 /*
402 * On 1bpp framebuffer, only plane P0 has framebuffer memory
403 * and other planes seems pulled up, i.e. always 1.
404 * Set white only for a palette (P0,P1,P2,P3) = (1,1,1,1).
405 */
406 odac->bt_addr = 0;
407 for (i = 0; i < 15; i++) {
408 odac->bt_cmap = dc->dc_cmap.r[i] = 0;
409 odac->bt_cmap = dc->dc_cmap.g[i] = 0;
410 odac->bt_cmap = dc->dc_cmap.b[i] = 0;
411 }
412 /*
413 * The B/W video connector is connected to IOG of Bt454,
414 * and IOR and IOB are unused.
415 */
416 odac->bt_cmap = dc->dc_cmap.r[15] = 0;
417 odac->bt_cmap = dc->dc_cmap.g[15] = 255;
418 odac->bt_cmap = dc->dc_cmap.b[15] = 0;
419 } else if (hwplanemask == 0x0f) {
420 struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC;
421
422 odac->bt_addr = 0;
423 for (i = 0; i < 16; i++) {
424 odac->bt_cmap = dc->dc_cmap.r[i] = ansicmap[i].r;
425 odac->bt_cmap = dc->dc_cmap.g[i] = ansicmap[i].g;
426 odac->bt_cmap = dc->dc_cmap.b[i] = ansicmap[i].b;
427 }
428 } else if (hwplanemask == 0xff) {
429 struct bt458 *ndac = (struct bt458 *)OMFB_RAMDAC;
430
431 /*
432 * Initialize the Bt458. When we write to control registers,
433 * the address is not incremented automatically. So we specify
434 * it ourselves for each control register.
435 */
436 ndac->bt_addr = 0x04;
437 ndac->bt_ctrl = 0xff; /* all planes will be read */
438 ndac->bt_addr = 0x05;
439 ndac->bt_ctrl = 0x00; /* all planes have non-blink */
440 ndac->bt_addr = 0x06;
441 ndac->bt_ctrl = 0x40; /* palette enabled, ovly plane disabled */
442 ndac->bt_addr = 0x07;
443 ndac->bt_ctrl = 0x00; /* no test mode */
444
445 /*
446 * Set ANSI 16 colors. We only supports 4bpp console right
447 * now, repeat 16 colors in 256 colormap.
448 */
449 ndac->bt_addr = 0;
450 for (i = 0; i < 256; i++) {
451 ndac->bt_cmap = dc->dc_cmap.r[i] = ansicmap[i % 16].r;
452 ndac->bt_cmap = dc->dc_cmap.g[i] = ansicmap[i % 16].g;
453 ndac->bt_cmap = dc->dc_cmap.b[i] = ansicmap[i % 16].b;
454 }
455 }
456 }
457
458 static void
omfb_getdevconfig(paddr_t paddr,struct om_hwdevconfig * dc)459 omfb_getdevconfig(paddr_t paddr, struct om_hwdevconfig *dc)
460 {
461 int bpp, i;
462 struct rasops_info *ri;
463 union {
464 struct { short h, v; } p;
465 uint32_t u;
466 } rfcnt;
467
468 switch (hwplanemask) {
469 case 0xff:
470 bpp = 8; /* XXX check monochrome bit in DIPSW */
471 break;
472 default:
473 case 0x0f:
474 bpp = 4; /* XXX check monochrome bit in DIPSW */
475 break;
476 case 1:
477 bpp = 1;
478 break;
479 }
480 dc->dc_wid = 1280;
481 dc->dc_ht = 1024;
482 dc->dc_depth = bpp;
483 dc->dc_rowbytes = 2048 / 8;
484 dc->dc_cmsize = (bpp == 1) ? 0 : 1 << bpp;
485 dc->dc_videobase = paddr;
486
487 omfb_resetcmap(dc);
488
489 /* adjust h/v origin on screen */
490 rfcnt.p.h = 7;
491 rfcnt.p.v = -27;
492 /* single write of 0x007ffe6 */
493 *(volatile uint32_t *)OMFB_RFCNT = rfcnt.u;
494
495 /* clear the screen */
496 *(volatile uint32_t *)OMFB_PLANEMASK = 0xff;
497 ((volatile uint32_t *)OMFB_ROPFUNC)[5] = ~0; /* ROP copy */
498 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes / sizeof(uint32_t); i++)
499 *((volatile uint32_t *)dc->dc_videobase + i) = 0;
500 *(volatile uint32_t *)OMFB_PLANEMASK = 0x01;
501
502 /* initialize the raster */
503 ri = &dc->dc_ri;
504 ri->ri_width = dc->dc_wid;
505 ri->ri_height = dc->dc_ht;
506 ri->ri_depth = dc->dc_depth;
507 ri->ri_stride = dc->dc_rowbytes;
508 ri->ri_bits = (void *)dc->dc_videobase;
509 ri->ri_flg = RI_CENTER;
510 if (dc == &omfb_console_dc)
511 ri->ri_flg |= RI_NO_AUTO;
512 ri->ri_hw = dc;
513
514 if (bpp == 4 || bpp == 8)
515 omrasops4_init(ri, 34, 80);
516 else
517 omrasops1_init(ri, 34, 80);
518
519 omfb_stdscreen.nrows = ri->ri_rows;
520 omfb_stdscreen.ncols = ri->ri_cols;
521 omfb_stdscreen.textops = &ri->ri_ops;
522 omfb_stdscreen.capabilities = ri->ri_caps;
523 omfb_stdscreen.fontwidth = ri->ri_font->fontwidth;
524 omfb_stdscreen.fontheight = ri->ri_font->fontheight;
525 }
526
527 static int
omfb_alloc_screen(void * v,const struct wsscreen_descr * type,void ** cookiep,int * curxp,int * curyp,long * attrp)528 omfb_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep,
529 int *curxp, int *curyp, long *attrp)
530 {
531 struct omfb_softc *sc = v;
532 struct rasops_info *ri = &sc->sc_dc->dc_ri;
533
534 if (sc->sc_nscreens > 0)
535 return ENOMEM;
536
537 *cookiep = ri;
538 *curxp = 0;
539 *curyp = 0;
540 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, attrp);
541 sc->sc_nscreens++;
542 return 0;
543 }
544
545 static void
omfb_free_screen(void * v,void * cookie)546 omfb_free_screen(void *v, void *cookie)
547 {
548 struct omfb_softc *sc = v;
549
550 if (sc->sc_dc == &omfb_console_dc)
551 panic("omfb_free_screen: console");
552
553 sc->sc_nscreens--;
554 }
555
556 static int
omfb_show_screen(void * v,void * cookie,int waitok,void (* cb)(void *,int,int),void * cbarg)557 omfb_show_screen(void *v, void *cookie, int waitok,
558 void (*cb)(void *, int, int), void *cbarg)
559 {
560
561 return 0;
562 }
563