xref: /netbsd-src/sys/arch/i386/pnpbios/pciide_pnpbios.c (revision a6ce3504542ed8b086b0b8c7681fff4540e0cdd8)
1 /*	$NetBSD: pciide_pnpbios.c,v 1.35 2023/12/20 15:00:08 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 1999 Soren S. Jorvang.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions, and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 /*
29  * Handle the weird "almost PCI" IDE on Toshiba Porteges.
30  */
31 
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: pciide_pnpbios.c,v 1.35 2023/12/20 15:00:08 thorpej Exp $");
34 
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/device.h>
38 
39 #include <sys/bus.h>
40 
41 #include <dev/ic/wdcreg.h>
42 #include <dev/isa/isavar.h>
43 #include <dev/isa/isadmavar.h>
44 
45 #include <i386/pnpbios/pnpbiosvar.h>
46 
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcidevs.h>
50 
51 #include <dev/pci/pciidereg.h>
52 #include <dev/pci/pciidevar.h>
53 
54 static int	pciide_pnpbios_match(device_t, cfdata_t, void *);
55 static void	pciide_pnpbios_attach(device_t, device_t, void *);
56 
57 extern void	pciide_channel_dma_setup(struct pciide_channel *);
58 extern int	pciide_dma_init(void *, int, int, void *, size_t, int);
59 extern void	pciide_dma_start(void *, int, int);
60 extern int	pciide_dma_finish(void *, int, int, int);
61 extern int	pciide_compat_intr (void *);
62 
63 CFATTACH_DECL_NEW(pciide_pnpbios, sizeof(struct pciide_softc),
64     pciide_pnpbios_match, pciide_pnpbios_attach, NULL, NULL);
65 
66 int
pciide_pnpbios_match(device_t parent,cfdata_t match,void * aux)67 pciide_pnpbios_match(device_t parent, cfdata_t match, void *aux)
68 {
69 	struct pnpbiosdev_attach_args *aa = aux;
70 
71 	if (strcmp(aa->idstr, "TOS7300") == 0)
72 		return 1;
73 
74 	return 0;
75 }
76 
77 void
pciide_pnpbios_attach(device_t parent,device_t self,void * aux)78 pciide_pnpbios_attach(device_t parent, device_t self, void *aux)
79 {
80 	struct pciide_softc *sc = device_private(self);
81 	struct pnpbiosdev_attach_args *aa = aux;
82 	struct pciide_channel *cp;
83 	struct ata_channel *wdc_cp;
84 	struct wdc_regs *wdr;
85 	bus_space_tag_t compat_iot;
86 	bus_space_handle_t cmd_baseioh, ctl_ioh;
87 	int i, drive, size;
88 	uint8_t idedma_ctl;
89 
90 	sc->sc_wdcdev.sc_atac.atac_dev = self;
91 
92 	aprint_naive(": disk controller\n");
93 	aprint_normal("\n");
94 	pnpbios_print_devres(self, aa);
95 
96 	aprint_normal_dev(self, "Toshiba Extended IDE Controller\n");
97 
98 	if (pnpbios_io_map(aa->pbt, aa->resc, 2, &sc->sc_dma_iot,
99 	    &sc->sc_dma_ioh) != 0) {
100 		aprint_error_dev(self, "unable to map DMA registers\n");
101 		return;
102 	}
103 	if (pnpbios_io_map(aa->pbt, aa->resc, 0, &compat_iot,
104 	    &cmd_baseioh) != 0) {
105 		aprint_error_dev(self, "unable to map command registers\n");
106 		return;
107 	}
108 	if (pnpbios_io_map(aa->pbt, aa->resc, 1, &compat_iot,
109 	    &ctl_ioh) != 0) {
110 		aprint_error_dev(self, "unable to map control register\n");
111 		return;
112 	}
113 
114 	sc->sc_dmat = &pci_bus_dma_tag;
115 
116 	cp = &sc->pciide_channels[0];
117 	sc->wdc_chanarray[0] = &cp->ata_channel;
118 	cp->ata_channel.ch_channel = 0;
119 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
120 
121 	sc->sc_dma_ok = 1;
122 	for (i = 0; i < IDEDMA_NREGS; i++) {
123 		size = 4;
124 		if (size > (IDEDMA_SCH_OFFSET - i))
125 			size = IDEDMA_SCH_OFFSET - i;
126 		if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
127 		    i, size, &cp->dma_iohs[i]) != 0) {
128 			aprint_error_dev(self, "can't subregion offset %d "
129 			    "size %lu", i, (u_long)size);
130 			return;
131 		}
132 	}
133 	sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
134 	sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
135 	sc->sc_wdcdev.dma_arg = sc;
136 	sc->sc_wdcdev.dma_init = pciide_dma_init;
137 	sc->sc_wdcdev.dma_start = pciide_dma_start;
138 	sc->sc_wdcdev.dma_finish = pciide_dma_finish;
139 	sc->sc_wdcdev.irqack = pciide_irqack;
140 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
141 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
142 	sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
143 	sc->sc_wdcdev.wdc_maxdrives = 2;
144 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
145 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
146 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 0;		/* XXX */
147 	sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;	/* XXX */
148 
149 	wdc_allocate_regs(&sc->sc_wdcdev);
150 
151 	wdc_cp = &cp->ata_channel;
152 	wdr = CHAN_TO_WDC_REGS(wdc_cp);
153 	wdr->cmd_iot = compat_iot;
154 	wdr->cmd_baseioh = cmd_baseioh;
155 
156 	for (i = 0; i < WDC_NREG; i++) {
157 		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
158 		    i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
159 			    aprint_error_dev(self, "unable to subregion "
160 				"control register\n");
161 			    return;
162 		}
163 	}
164 	wdc_init_shadow_regs(wdr);
165 
166 	wdr->ctl_iot = wdr->data32iot = compat_iot;
167 	wdr->ctl_ioh = wdr->data32ioh = ctl_ioh;
168 
169 	cp->compat = 1;
170 
171 	cp->ih = pnpbios_intr_establish(aa->pbt, aa->resc, 0, IPL_BIO,
172 					pciide_compat_intr, cp);
173 
174 	wdcattach(wdc_cp);
175 
176 	idedma_ctl = 0;
177 	for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
178 		/*
179 		 * we have not probed the drives yet,
180 		 * allocate resources for all of them.
181 		 */
182 		if (pciide_dma_table_setup(sc, 0, drive) != 0) {
183 			/* Abort DMA setup */
184 			aprint_error(
185 			    "%s:%d:%d: can't allocate DMA maps, "
186 			    "using PIO transfers\n",
187 			    device_xname(self), 0, drive);
188 			sc->sc_dma_ok = 0;
189 			sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
190 			sc->sc_wdcdev.irqack = NULL;
191 			idedma_ctl = 0;
192 			break;
193 		}
194 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
195 	}
196 	if (idedma_ctl != 0) {
197 		/* Add software bits in status register */
198 		bus_space_write_1(sc->sc_dma_iot,
199 		    cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl);
200 	}
201 }
202