1 /* $NetBSD: mipssim_intr.c,v 1.2 2021/02/15 22:39:46 reinoud Exp $ */
2
3 /*-
4 * Copyright (c) 2014 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: mipssim_intr.c,v 1.2 2021/02/15 22:39:46 reinoud Exp $");
31
32 #define __INTR_PRIVATE
33
34 #include <sys/param.h>
35 #include <sys/cpu.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/kmem.h>
39
40 #include <mips/locore.h>
41 #include <machine/intr.h>
42
43 /*
44 * This is a mask of bits to clear in the SR when we go to a
45 * given hardware interrupt priority level.
46 */
47 static const struct ipl_sr_map mipssim_ipl_sr_map = {
48 .sr_bits = {
49 [IPL_NONE] = 0,
50 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
51 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
52 [IPL_VM] = MIPS_SOFT_INT_MASK
53 | MIPS_INT_MASK_0 | MIPS_INT_MASK_1
54 | MIPS_INT_MASK_2,
55 [IPL_SCHED] = MIPS_SOFT_INT_MASK
56 | MIPS_INT_MASK_0 | MIPS_INT_MASK_1
57 | MIPS_INT_MASK_2 | MIPS_INT_MASK_5,
58 [IPL_DDB] = MIPS_INT_MASK,
59 [IPL_HIGH] = MIPS_INT_MASK,
60 },
61 };
62
63 /* XXX - add evcnt bits to <machine/intr.h> struct evbmips_intrhand */
64 struct intrhand {
65 LIST_ENTRY(intrhand) ih_q;
66 int (*ih_func)(void *);
67 void *ih_arg;
68 int ih_irq;
69 };
70
71
72 /*
73 * Use CPU interrupts INT0 .. INT4. Clock interrupts (INT5)
74 * are handled in cpu_intr() before evbmips_iointr() is called.
75 */
76 #define NINTR 5 /* MIPS INT0 - INT4 */
77
LIST_HEAD(intrlist,intrhand)78 LIST_HEAD(intrlist, intrhand) intrs[NINTR];
79 struct evcnt ih_count[NINTR];
80
81 const char * const intrnames[NINTR] = {
82 "int 0 (mipsnet)",
83 "int 1 (virtio)",
84 "int 2 (uart)",
85 "int 3 (unused)",
86 "int 4 (unused)",
87 };
88
89 void mipssim_irq(int);
90
91 void
evbmips_intr_init(void)92 evbmips_intr_init(void)
93 {
94 int i;
95
96 ipl_sr_map = mipssim_ipl_sr_map;
97
98 /* zero all handlers */
99 for (i = 0; i < NINTR; i++) {
100 LIST_INIT(&intrs[i]);
101 evcnt_attach_dynamic(&ih_count[i], EVCNT_TYPE_INTR,
102 NULL, "cpu", intrnames[i]);
103 }
104 }
105
106 void
evbmips_iointr(int ipl,uint32_t ipending,struct clockframe * cf)107 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
108 {
109 struct intrlist *list;
110
111 for (int level = NINTR - 1; level >= 0; level--) {
112 struct intrhand *ih;
113
114 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
115 continue;
116
117 ih_count[level].ev_count++;
118 list = &intrs[level];
119
120 LIST_FOREACH(ih, list, ih_q) {
121 if (ih->ih_func) {
122 (*ih->ih_func)(ih->ih_arg);
123 }
124 }
125 }
126 }
127
128 void *
evbmips_intr_establish(int irq,int (* func)(void *),void * arg)129 evbmips_intr_establish(int irq, int (*func)(void *), void *arg)
130 {
131 struct intrlist *list;
132 struct intrhand *ih;
133 int s;
134
135 if ((irq < 0) || (irq >= NINTR)) {
136 aprint_error("%s: invalid irq %d\n", __func__, irq);
137 return NULL;
138 }
139
140 list = &intrs[irq];
141 ih = kmem_alloc(sizeof(struct intrhand), KM_SLEEP);
142
143 s = splhigh();
144
145 ih->ih_func = func;
146 ih->ih_arg = arg;
147 ih->ih_irq = irq;
148 LIST_INSERT_HEAD(list, ih, ih_q);
149
150 /* now enable the IRQ (nothing to do here?) */
151
152 splx(s);
153
154 return ih;
155 }
156
157 void
evbmips_intr_disestablish(void * cookie)158 evbmips_intr_disestablish(void *cookie)
159 {
160 panic("untested %s", __func__); /* XXX! */
161
162 struct intrhand *ih = cookie;
163 int s;
164
165 s = splhigh();
166
167 /* now disable the IRQ (nothing to do here?) */
168
169 ih->ih_func = NULL;
170 ih->ih_arg = NULL;
171 LIST_REMOVE(ih, ih_q);
172 kmem_free(ih, sizeof(struct intrhand));
173
174 splx(s);
175 }
176