1 /* $NetBSD: if_mipsnetreg.h,v 1.1 2021/01/27 05:24:16 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2021 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Simon Burge. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * MIPSSIM emulator MIPSNET ethernet registers 34 */ 35 36 #define MN_DEVID0 0x00 /* device info */ 37 #define MN_DEVID1 0x00 /* device info */ 38 #define MN_BUSY 0x08 /* rx/tx in progress */ 39 #define MN_RXDATACOUNT 0x0c /* bytes in rx data buffer */ 40 #define MN_TXDATACOUNT 0x10 /* bytes for tx data buffer */ 41 #define MN_INTR 0x14 /* interrupt control */ 42 #define MN_INTR_TXDONE __BIT(0) /* tx done interrupt */ 43 #define MN_INTR_RXDONE __BIT(1) /* rx data available interrupt */ 44 #define MN_INTR_TEST __BIT(31) /* interrupt test */ 45 #define MN_INTRINFO 0x18 /* core-specific interrupt info */ 46 #define MN_RXDATA 0x1c /* rx data fifo */ 47 #define MN_TXDATA 0x20 /* tx data fifo */ 48 49 #define MN_NPORTS 0x24 /* size to map for registers */ 50 51 #define MN_MAXDATA 32768 /* largest transfer size */ 52 53 #define MIPSNET_DEVID0 0x4d495053 /* ascii "MIPS" */ 54 #define MIPSNET_DEVID1 0x4e455430 /* ascii "NET0" */ 55