xref: /netbsd-src/sys/arch/evbarm/stand/board/sscom.c (revision 8e6ab8837d8d6b9198e67c1c445300b483e2f304)
1 /*	$NetBSD: sscom.c,v 1.1 2003/07/30 18:54:21 bsh Exp $ */
2 
3 
4 /*
5  * Copyright (c) 2002, 2003 Fujitsu Component Limited
6  * Copyright (c) 2002, 2003 Genetec Corporation
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. Neither the name of The Fujitsu Component Limited nor the name of
18  *    Genetec corporation may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
22  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
23  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
26  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  */
35 /* derived from ns16550.c */
36 /*
37  * Copyright (c) 2002 Wasabi Systems, Inc.
38  * All rights reserved.
39  *
40  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
41  *
42  * Redistribution and use in source and binary forms, with or without
43  * modification, are permitted provided that the following conditions
44  * are met:
45  * 1. Redistributions of source code must retain the above copyright
46  *    notice, this list of conditions and the following disclaimer.
47  * 2. Redistributions in binary form must reproduce the above copyright
48  *    notice, this list of conditions and the following disclaimer in the
49  *    documentation and/or other materials provided with the distribution.
50  * 3. All advertising materials mentioning features or use of this software
51  *    must display the following acknowledgement:
52  *	This product includes software developed for the NetBSD Project by
53  *	Wasabi Systems, Inc.
54  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
55  *    or promote products derived from this software without specific prior
56  *    written permission.
57  *
58  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
59  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
60  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
61  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
62  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
63  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
64  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
65  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
66  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
67  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
68  * POSSIBILITY OF SUCH DAMAGE.
69  */
70 /*
71  * This file provides the cons_init() function and console I/O routines
72  * for boards that use built-in UART of Samsung's S3C2xx0 CPUs.
73  */
74 
75 #include <sys/types.h>
76 #include <arch/arm/s3c2xx0/s3c2xx0reg.h>
77 #include <arch/arm/s3c2xx0/s3c2800reg.h>
78 #include <lib/libsa/stand.h>
79 
80 #include "board.h"
81 
82 #ifndef XTAL_CLK
83 #error XTAL_CLK is not defined
84 #endif
85 
86 #ifndef SSCOM_TOLERANCE
87 #define	SSCOM_TOLERANCE	30	/* XXX: baud rate tolerance, in 0.1% units */
88 #endif
89 
90 #define	INB(x)		*((__volatile uint8_t *) ((CONADDR) + (x)))
91 #define	INW(x)		*((__volatile uint16_t *) ((CONADDR) + (x)))
92 #define	OUTB(x, v)	(*((__volatile uint8_t *) ((CONADDR) + (x))) = (v))
93 #define	OUTW(x, v)	(*((__volatile uint16_t *) ((CONADDR) + (x))) = (v))
94 
95 #define	ISSET(t,f)	((t) & (f))
96 
97 long get_com_freq(void);
98 long
99 get_com_freq(void)
100 {
101 	long clk;
102 	uint16_t clkcon = *(volatile uint16_t*)(S3C2800_CLKMAN_BASE+CLKMAN_CLKCON);
103 	uint32_t pllcon = *(volatile uint32_t*)(S3C2800_CLKMAN_BASE+CLKMAN_PLLCON);
104 
105 	int mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
106 	int pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
107 	int sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
108 
109 #if XTAL_CLK < 1000   /* in MHz */
110 	clk = (XTAL_CLK * 1000000 * (8 + mdiv)) / ((pdiv + 2) << sdiv);
111 #else /* in Hz */
112 	clk = (XTAL_CLK * (8 + mdiv)) / ((pdiv + 2) << sdiv);
113 #endif
114 
115 	/*printf( "M=%d P=%d S=%d\n", mdiv, pdiv, sdiv);*/
116 
117 	if (clkcon & CLKCON_HCLK)
118 		clk /= 2;
119 	if (clkcon & CLKCON_PCLK)
120 		clk /= 2;
121 
122 	return clk;
123 }
124 
125 static int
126 sscomspeed(long speed)
127 {
128 #define	divrnd(n, q)	(((n)*2/(q)+1)/2)	/* divide and round off */
129 
130 	int x, err;
131 	long pclk = get_com_freq();
132 
133 	if (speed <= 0)
134 		return -1;
135 	x = divrnd(pclk / 16, speed);
136 	if (x <= 0)
137 		return -1;
138 	err = divrnd(((quad_t)pclk) * 1000 / 16, speed * x) - 1000;
139 	if (err < 0)
140 		err = -err;
141 	if (err > SSCOM_TOLERANCE)
142 		return -1;
143 	return x-1;
144 
145 #undef	divrnd
146 }
147 
148 void
149 cons_init(void)
150 {
151 	int rate;
152 
153 	OUTW(SSCOM_UCON, 0);
154 	OUTB(SSCOM_UFCON, UFCON_TXTRIGGER_8 | UFCON_RXTRIGGER_8 |
155 	    UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET |
156 	    UFCON_FIFO_ENABLE);
157 
158 	rate = sscomspeed(CONSPEED);
159 	OUTW(SSCOM_UBRDIV, rate);
160 	OUTW(SSCOM_ULCON, ULCON_PARITY_NONE|ULCON_LENGTH_8);
161 
162 	/* enable UART */
163 	OUTW(SSCOM_UCON, UCON_TXMODE_INT|UCON_RXMODE_INT);
164 	OUTW(SSCOM_UMCON, UMCON_RTS);
165 }
166 
167 #define sscom_rxrdy() (INB(SSCOM_UTRSTAT) & UTRSTAT_RXREADY)
168 
169 int
170 getchar(void)
171 {
172 	uint8_t stat;
173 	int c;
174 
175 	while (!sscom_rxrdy())
176 		/* spin */ ;
177 	c = INB(SSCOM_URXH);
178 	stat = INB(SSCOM_UERSTAT);	/* XXX */
179 
180 	return c;
181 }
182 
183 static void
184 iputchar(int c)
185 {
186 	uint16_t stat;
187 	int timo;
188 
189 	/* Wait for any pending transmission to finish. */
190 	timo = 50000;
191 	while (ISSET(stat = INW(SSCOM_UFSTAT), UFSTAT_TXFULL) && --timo)
192 		/* spin */ ;
193 
194 	OUTB(SSCOM_UTXH, c);
195 
196 #if 0
197 	/* Wait for this transmission to complete. */
198 	timo = 1500000;
199 	while (!ISSET(stat = INW(SSCOM_UFSTAT), UFSTAT_TXFULL) && --timo)
200 		/* spin */ ;
201 #endif
202 }
203 
204 void
205 putchar(int c)
206 {
207 
208 	if (c == '\n')
209 		iputchar('\r');
210 	iputchar(c);
211 }
212