1 /* $NetBSD: sscom.c,v 1.7 2022/09/05 14:14:42 tsutsui Exp $ */
2
3
4 /*
5 * Copyright (c) 2002, 2003 Fujitsu Component Limited
6 * Copyright (c) 2002, 2003 Genetec Corporation
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of The Fujitsu Component Limited nor the name of
18 * Genetec corporation may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
22 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
26 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35 /* derived from ns16550.c */
36 /*
37 * Copyright (c) 2002 Wasabi Systems, Inc.
38 * All rights reserved.
39 *
40 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
44 * are met:
45 * 1. Redistributions of source code must retain the above copyright
46 * notice, this list of conditions and the following disclaimer.
47 * 2. Redistributions in binary form must reproduce the above copyright
48 * notice, this list of conditions and the following disclaimer in the
49 * documentation and/or other materials provided with the distribution.
50 * 3. All advertising materials mentioning features or use of this software
51 * must display the following acknowledgement:
52 * This product includes software developed for the NetBSD Project by
53 * Wasabi Systems, Inc.
54 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
55 * or promote products derived from this software without specific prior
56 * written permission.
57 *
58 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
59 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
60 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
61 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
62 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
65 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
66 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
67 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
68 * POSSIBILITY OF SUCH DAMAGE.
69 */
70 /*
71 * This file provides the cons_init() function and console I/O routines
72 * for boards that use built-in UART of Samsung's S3C2xx0 CPUs.
73 */
74
75 #include <sys/types.h>
76 #include <arch/arm/s3c2xx0/s3c2xx0reg.h>
77 #ifdef CPU_S3C2410
78 #include <arch/arm/s3c2xx0/s3c2410reg.h>
79 #endif
80 #ifdef CPU_S3C2800
81 #include <arch/arm/s3c2xx0/s3c2800reg.h>
82 #endif
83 #include <lib/libsa/stand.h>
84
85 #include "board.h"
86
87 #ifndef SSCOM_TOLERANCE
88 #define SSCOM_TOLERANCE 30 /* XXX: baud rate tolerance, in 0.1% units */
89 #endif
90
91 #define INB(x) *((volatile uint8_t *) ((CONADDR) + (x)))
92 #define INW(x) *((volatile uint32_t *) ((CONADDR) + (x)))
93 #define OUTB(x, v) (*((volatile uint8_t *) ((CONADDR) + (x))) = (v))
94 #define OUTW(x, v) (*((volatile uint32_t *) ((CONADDR) + (x))) = (v))
95
96 static long get_com_freq(void);
97
98 static int
sscomspeed(long speed)99 sscomspeed(long speed)
100 {
101 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
102
103 int x, err;
104 long pclk = get_com_freq();
105
106 if (speed <= 0)
107 return -1;
108 x = divrnd(pclk / 16, speed);
109 if (x <= 0)
110 return -1;
111 err = divrnd(((quad_t)pclk) * 1000 / 16, speed * x) - 1000;
112 if (err < 0)
113 err = -err;
114 if (err > SSCOM_TOLERANCE)
115 return -1;
116 return x-1;
117
118 #undef divrnd
119 }
120
121 void
cons_init(void)122 cons_init(void)
123 {
124 int rate;
125
126 OUTW(SSCOM_UCON, 0);
127 OUTB(SSCOM_UFCON, UFCON_TXTRIGGER_8 | UFCON_RXTRIGGER_8 |
128 UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET |
129 UFCON_FIFO_ENABLE);
130
131 rate = sscomspeed(CONSPEED);
132 OUTW(SSCOM_UBRDIV, rate);
133 OUTW(SSCOM_ULCON, ULCON_PARITY_NONE|ULCON_LENGTH_8);
134
135 /* enable UART */
136 OUTW(SSCOM_UCON, UCON_TXMODE_INT|UCON_RXMODE_INT);
137 OUTW(SSCOM_UMCON, UMCON_RTS);
138 }
139
140 #define sscom_rxrdy() (INB(SSCOM_UTRSTAT) & UTRSTAT_RXREADY)
141
142 int
getchar(void)143 getchar(void)
144 {
145 uint8_t stat __unused;
146 int c;
147
148 while (!sscom_rxrdy())
149 /* spin */ ;
150 c = INB(SSCOM_URXH);
151 stat = INB(SSCOM_UERSTAT); /* XXX */
152
153 return c;
154 }
155
156 static void
iputchar(int c)157 iputchar(int c)
158 {
159 uint32_t stat;
160 int timo;
161
162 /* Wait for any pending transmission to finish. */
163 timo = 50000;
164 while (ISSET(stat = INW(SSCOM_UFSTAT), UFSTAT_TXFULL) && --timo)
165 /* spin */ ;
166
167 OUTB(SSCOM_UTXH, c);
168
169 #if 0
170 /* Wait for this transmission to complete. */
171 timo = 1500000;
172 while (!ISSET(stat = INW(SSCOM_UFSTAT), UFSTAT_TXFULL) && --timo)
173 /* spin */ ;
174 #endif
175 }
176
177 void
putchar(int c)178 putchar(int c)
179 {
180
181 if (c == '\n')
182 iputchar('\r');
183 iputchar(c);
184 }
185
186
187 #define read_reg(addr) (*(volatile uint32_t *)(addr))
188
189 static long
get_com_freq(void)190 get_com_freq(void)
191 {
192 long clk;
193 #ifdef CPU_S3C2800
194 uint32_t pllcon = read_reg(S3C2800_CLKMAN_BASE+CLKMAN_PLLCON);
195 uint32_t div = read_reg(S3C2800_CLKMAN_BASE+CLKMAN_CLKCON);
196 #define HDIV CLKCON_HCLK
197 #define PDIV CLKCON_PCLK
198 #endif
199 #ifdef CPU_S3C2410
200 uint32_t pllcon = read_reg(S3C2410_CLKMAN_BASE+CLKMAN_MPLLCON);
201 uint32_t div = read_reg(S3C2410_CLKMAN_BASE+CLKMAN_CLKDIVN);
202 #define HDIV CLKDIVN_HDIVN
203 #define PDIV CLKDIVN_PDIVN
204 #endif
205
206 int mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
207 int pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
208 int sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
209
210 #if XTAL_CLK < 1000 /* in MHz */
211 clk = (XTAL_CLK * 1000000 * (8 + mdiv)) / ((pdiv + 2) << sdiv);
212 #else /* in Hz */
213 clk = (XTAL_CLK * (8 + mdiv)) / ((pdiv + 2) << sdiv);
214 #endif
215
216 /*printf( "M=%d P=%d S=%d\n", mdiv, pdiv, sdiv);*/
217
218 if (div & HDIV)
219 clk /= 2;
220 if (div & PDIV)
221 clk /= 2;
222
223 return clk;
224 }
225