1 /* $NetBSD: i80321_mainbus.c,v 1.1 2019/02/14 21:47:52 macallan Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Iyonix front-end for the i80321 I/O Processor. We take care
40 * of setting up the i80321 memory map, PCI interrupt routing, etc.,
41 * which are all specific to the board the i80321 is wired up to.
42 */
43
44 #include <sys/cdefs.h>
45 __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.1 2019/02/14 21:47:52 macallan Exp $");
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/device.h>
50
51 #include <machine/autoconf.h>
52 #include <sys/bus.h>
53
54 #include <evbarm/iyonix/iyonixreg.h>
55 #include <evbarm/iyonix/iyonixvar.h>
56
57 #include <arm/xscale/i80321reg.h>
58 #include <arm/xscale/i80321var.h>
59
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcidevs.h>
62
63 int i80321_mainbus_match(device_t, cfdata_t, void *);
64 void i80321_mainbus_attach(device_t, device_t, void *);
65
66 CFATTACH_DECL_NEW(iopxs_mainbus, sizeof(struct i80321_softc),
67 i80321_mainbus_match, i80321_mainbus_attach, NULL, NULL);
68
69 /* There can be only one. */
70 int i80321_mainbus_found;
71
72 int
i80321_mainbus_match(device_t parent,cfdata_t cf,void * aux)73 i80321_mainbus_match(device_t parent, cfdata_t cf, void *aux)
74 {
75 #if 0
76 struct mainbus_attach_args *ma = aux;
77 #endif
78
79 if (i80321_mainbus_found)
80 return (0);
81
82 #if 1
83 /* XXX Shoot arch/arm/mainbus in the head. */
84 return (1);
85 #else
86 if (strcmp(cf->cf_name, ma->ma_name) == 0)
87 return (1);
88
89 return (0);
90 #endif
91 }
92
93 void
i80321_mainbus_attach(device_t parent,device_t self,void * aux)94 i80321_mainbus_attach(device_t parent, device_t self, void *aux)
95 {
96 struct i80321_softc *sc = device_private(self);
97 pcireg_t b0u, b0l, b1u, b1l;
98 paddr_t memstart;
99 psize_t memsize;
100
101 i80321_mainbus_found = 1;
102 sc->sc_dev = self;
103
104 /*
105 * Fill in the space tag for the i80321's own devices,
106 * and hand-craft the space handle for it (the device
107 * was mapped during early bootstrap).
108 */
109 i80321_bs_init(&i80321_bs_tag, sc);
110 sc->sc_st = &i80321_bs_tag;
111 sc->sc_sh = IYONIX_80321_VBASE;
112
113 /*
114 * Slice off a subregion for the Memory Controller -- we need it
115 * here in order read the memory size.
116 */
117 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE,
118 VERDE_MCU_SIZE, &sc->sc_mcu_sh))
119 panic("%s: unable to subregion MCU registers",
120 device_xname(self));
121
122 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE,
123 VERDE_ATU_SIZE, &sc->sc_atu_sh))
124 panic("%s: unable to subregion ATU registers",
125 device_xname(self));
126
127 /*
128 * We have mapped the PCI I/O windows in the early bootstrap phase.
129 */
130 sc->sc_iow_vaddr = IYONIX_IOW_VBASE;
131
132 /*
133 * Check the configuration of the ATU to see if another BIOS
134 * has configured us. If a PC BIOS didn't configure us, then
135 * BAR0 is 00000000.0000000c and BAR1 is 00000000.8000000c. If
136 * a BIOS has configured us, at least one of those should be
137 * different.
138 */
139 b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0);
140 b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4);
141 b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8);
142 b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc);
143
144 if ((b0u != b1u) || (b0l != 0x0000000c) || (b1l != 0x8000000cU))
145 sc->sc_is_host = 0;
146 else
147 sc->sc_is_host = 1;
148
149 sc->sc_is_host = 1;
150
151 aprint_naive(": i80321 I/O Processor\n");
152 aprint_normal(": i80321 I/O Processor, acting as PCI %s\n",
153 sc->sc_is_host ? "host" : "slave");
154
155 i80321_intr_evcnt_attach();
156
157 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
158
159 /*
160 * We set up the Inbound Windows as follows:
161 *
162 * 0 Access to i80321 PMMRs
163 *
164 * 1 Reserve space for private devices
165 *
166 * 2 RAM access
167 *
168 * 3 Unused.
169 *
170 * This chunk needs to be customized for each IOP321 application.
171 */
172
173 if (sc->sc_is_host) {
174 /* Map PCI:Local 1:1. */
175
176 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
177 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
178 PCI_MAPREG_MEM_TYPE_64BIT;
179 sc->sc_iwin[1].iwin_base_hi = 0;
180 } else {
181 sc->sc_iwin[1].iwin_base_lo = 0;
182 sc->sc_iwin[1].iwin_base_hi = 0;
183 }
184 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
185 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
186
187 if (sc->sc_is_host) {
188 sc->sc_iwin[2].iwin_base_lo = memstart |
189 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
190 PCI_MAPREG_MEM_TYPE_64BIT;
191 sc->sc_iwin[2].iwin_base_hi = 0;
192 } else {
193 sc->sc_iwin[2].iwin_base_lo = 0;
194 sc->sc_iwin[2].iwin_base_hi = 0;
195 }
196 sc->sc_iwin[2].iwin_xlate = memstart;
197 sc->sc_iwin[2].iwin_size = memsize;
198
199 if (sc->sc_is_host) {
200 sc->sc_iwin[3].iwin_base_lo = 0 |
201 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
202 PCI_MAPREG_MEM_TYPE_64BIT;
203 } else {
204 sc->sc_iwin[3].iwin_base_lo = 0;
205 }
206 sc->sc_iwin[3].iwin_base_hi = 0;
207 sc->sc_iwin[3].iwin_xlate = 0;
208 sc->sc_iwin[3].iwin_size = 0;
209
210 /*
211 * We set up the Outbound Windows as follows:
212 *
213 * 0 Access to private PCI space.
214 *
215 * 1 Unused.
216 */
217 sc->sc_owin[0].owin_xlate_lo =
218 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
219 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
220
221 /*
222 * Set the Secondary Outbound I/O window to map
223 * to PCI address 0 for all 64K of the I/O space.
224 */
225 sc->sc_ioout_xlate = 0;
226 sc->sc_ioout_xlate_offset = 0;
227
228 /*
229 * Initialize the interrupt part of our PCI chipset tag.
230 */
231 iyonix_pci_init(&sc->sc_pci_chipset, sc);
232
233 i80321_attach(sc);
234 }
235