1 /* $NetBSD: ixdp425_pci.c,v 1.13 2019/01/09 07:49:22 msaitoh Exp $ */
2 #define PCI_DEBUG
3 /*
4 * Copyright (c) 2003
5 * Ichiro FUKUHARA <ichiro@ichiro.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: ixdp425_pci.c,v 1.13 2019/01/09 07:49:22 msaitoh Exp $");
32
33 /*
34 * IXDP425 PCI interrupt support.
35 */
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/device.h>
40
41 #include <machine/autoconf.h>
42 #include <sys/bus.h>
43
44 #include <evbarm/ixdp425/ixdp425reg.h>
45 #include <evbarm/ixdp425/ixdp425var.h>
46
47 #include <arm/xscale/ixp425reg.h>
48 #include <arm/xscale/ixp425var.h>
49
50 #include <dev/pci/pcidevs.h>
51 #include <dev/pci/ppbreg.h>
52
53 static int ixdp425_pci_intr_map(const struct pci_attach_args *,
54 pci_intr_handle_t *);
55 static const char *ixdp425_pci_intr_string(void *, pci_intr_handle_t, char *, size_t);
56 static const struct evcnt *ixdp425_pci_intr_evcnt(void *, pci_intr_handle_t);
57 static void *ixdp425_pci_intr_establish(void *, pci_intr_handle_t, int,
58 int (*func)(void *), void *, const char *);
59 static void ixdp425_pci_intr_disestablish(void *, void *);
60
61 void
ixp425_md_pci_init(struct ixp425_softc * sc)62 ixp425_md_pci_init(struct ixp425_softc *sc)
63 {
64 pci_chipset_tag_t pc = &sc->ia_pci_chipset;
65 uint32_t reg;
66
67 /*
68 * PCI initialization
69 */
70 pc->pc_intr_v = sc;
71 pc->pc_intr_map = ixdp425_pci_intr_map;
72 pc->pc_intr_string = ixdp425_pci_intr_string;
73 pc->pc_intr_evcnt = ixdp425_pci_intr_evcnt;
74 pc->pc_intr_establish = ixdp425_pci_intr_establish;
75 pc->pc_intr_disestablish = ixdp425_pci_intr_disestablish;
76
77 /* PCI Reset Assert */
78 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
79 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET));
80
81 /* PCI Clock Disable */
82 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
83 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14);
84
85 /*
86 * set GPIO Direction
87 * Output: PCI_CLK, PCI_RESET
88 * Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
89 */
90 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
91 reg &= ~(1U << GPIO_PCI_CLK);
92 reg &= ~(1U << GPIO_PCI_RESET);
93 reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
94 (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
95 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
96
97 /* clear ISR */
98 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
99 (1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
100 (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
101
102 /* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
103 DELAY(1000);
104 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
105 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg |
106 (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT));
107
108 /* PCI Clock Enable */
109 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
110 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
111
112 /*
113 * wait 100us to satisfy "minimum reset assertion time from clock stable
114 * requirement of the PCI spec
115 */
116 DELAY(100);
117 /* PCI Reset deassert */
118 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
119 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
120
121 /*
122 * AHB->PCI address translation
123 * PCI Memory Map allocation in 0x48000000 (64MB)
124 * see. IXP425_PCI_MEM_HWBASE
125 */
126 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
127
128 /*
129 * PCI->AHB address translation
130 * begin at the physical memory start + OFFSET
131 */
132 #define AHB_OFFSET 0x10000000UL
133 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
134 (AHB_OFFSET & 0xFF000000) +
135 ((AHB_OFFSET & 0xFF000000) >> 8) +
136 ((AHB_OFFSET & 0xFF000000) >> 16) +
137 ((AHB_OFFSET & 0xFF000000) >> 24) +
138 0x00010203);
139
140 /* write Mapping registers PCI Configuration Registers */
141 /* Base Address 0 - 3 */
142 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
143 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
144 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
145 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
146
147 /* Base Address 4 */
148 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff);
149
150 /* Base Address 5 */
151 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000);
152
153 /* assert some PCI errors */
154 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
155
156 /*
157 * Set up byte lane swapping between little-endian PCI
158 * and the big-endian AHB bus
159 */
160 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
161
162 /*
163 * Enable bus mastering and I/O,memory access
164 */
165 ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG,
166 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
167 PCI_COMMAND_MASTER_ENABLE);
168 }
169
170 void
ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc,int bus,int dev,int pin,int swiz,int * ilinep)171 ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
172 int swiz, int *ilinep)
173 {
174
175 if (bus == 0)
176 *ilinep = ((swiz + (dev + pin - 1)) & 3);
177 else
178 panic("ixp425_md_pci_conf_interrupt: unsupported bus number");
179 }
180
181 #define IXP425_MAX_DEV 4
182 #define IXP425_MAX_LINE 4
183 static int
ixdp425_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)184 ixdp425_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
185 {
186 static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] =
187 {
188 {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
189 {PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A},
190 {PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B},
191 {PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C},
192 };
193
194 int pin = pa->pa_intrpin;
195 int dev = pa->pa_device;
196
197 #ifdef PCI_DEBUG
198 void *v = pa->pa_pc;
199 int line = pa->pa_intrline;
200 pcitag_t intrtag = pa->pa_intrtag;
201
202 printf("ixdp425_pci_intr_map: v=%p, tag=%08lx intrpin=%d line=%d dev=%d\n",
203 v, intrtag, pin, line, dev);
204 #endif
205
206 if (pin >= 1 && pin <= IXP425_MAX_LINE &&
207 dev >= 1 && dev <= IXP425_MAX_DEV) {
208 *ihp = ixp425_pci_table[dev - 1][pin - 1];
209 return (0);
210 } else {
211 printf("ixdp425_pci_intr_map: no mapping for %d/%d/%d\n",
212 pa->pa_bus, pa->pa_device, pa->pa_function);
213 return (1);
214 }
215 }
216
217 static const char *
ixdp425_pci_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)218 ixdp425_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
219 {
220 snprintf(buf, len, "ixp425 irq %" PRIu64, ih);
221 return buf;
222 }
223
224 static const struct evcnt *
ixdp425_pci_intr_evcnt(void * v,pci_intr_handle_t ih)225 ixdp425_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
226 {
227 return (NULL);
228 }
229
230 static void *
ixdp425_pci_intr_establish(void * v,pci_intr_handle_t ih,int ipl,int (* func)(void *),void * arg,const char * xname)231 ixdp425_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
232 int (*func)(void *), void *arg, const char *xname)
233 {
234 #ifdef PCI_DEBUG
235 printf("ixdp425_pci_intr_establish(v=%p, irq=%d, ipl=%d, func=%p, arg=%p)\n",
236 v, (int) ih, ipl, func, arg);
237 #endif
238
239 return (ixp425_intr_establish(ih, ipl, func, arg));
240 }
241
242 static void
ixdp425_pci_intr_disestablish(void * v,void * cookie)243 ixdp425_pci_intr_disestablish(void *v, void *cookie)
244 {
245 #ifdef PCI_DEBUG
246 printf("ixdp425_pci_intr_disestablish(v=%p, cookie=%p)\n",
247 v, cookie);
248 #endif
249
250 ixp425_intr_disestablish(cookie);
251 }
252