1/* $NetBSD: imx31lk_start.S,v 1.2 2008/04/27 18:58:46 matt Exp $ */ 2 3#include <machine/asm.h> 4#include <arm/armreg.h> 5#include <arm/arm32/pmap.h> 6#include <arm/arm32/pte.h> 7 8 9/* 10 */ 11 12#define CPWAIT_BRANCH \ 13 sub pc, pc, #4 14 15#define CPWAIT(tmp) \ 16 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 17 mov tmp, tmp /* wait for it to complete */ ;\ 18 CPWAIT_BRANCH /* branch to next insn */ 19 20 21#ifndef SDRAM_START 22#define SDRAM_START 0x80000000 23#endif 24 25#define IXM31_DCACHE_SIZE 0x4000 /* 16KB L1 */ 26 27 28 29 .text 30 31 .global _C_LABEL(imx31lk_start) 32_C_LABEL(imx31lk_start): 33 /* Figure out where we want to jump to when the time comes */ 34 adr r8, .Lstart 35 ldr r8, [r8] 36 37 /* 38 * set up virtual address space mapping 39 * for initial bootstrap. 40 */ 41 mov r2, #(L1_S_SIZE) /* 1MB chunks */ 42 43 /* 44 * Firmware already mapped SDRAM VA == PA. at 0x800.. 45 * now map SDRAM also at VA 0x800... 46 */ 47 mrc p15, 0, r0, c2, c0, 0 /* L1 addr into r0 */ 48 add r0, r0, #(0x800 * 4) /* offset to 0x80000000 */ 49 50 mov r3, #SDRAM_START /* map to 0x800.. */ 51 orr r3, r3, #(L1_S_AP(AP_KRW)) /* the usual perms & stuff */ 52 orr r3, r3, #(L1_TYPE_S) 53 orr r3, r3, #(L1_S_DOM(PMAP_DOMAIN_KERNEL)) 54 55 mov r1, #0x80 /* 128 1MB entries */ 561: 57 /* and looplooploop */ 58 str r3, [r0], #4 59 add r3, r3, r2 60 subs r1, r1, #1 61 bgt 1b 62 63 /* 64 * Map an L1 section for each device to make this easy. 65 */ 66 /* UART1 */ 67 mrc p15, 0, r0, c2, c0, 0 /* Get L1 */ 68 add r0, r0, #(0xfd0 * 4) /* offset to 0xfd000000 */ 69 70 mov r3, #0x43000000 71 orr r3, r3, #0x00f00000 72 orr r3, r3, #(L1_S_AP(AP_KRW)) 73 orr r3, r3, #(L1_TYPE_S) 74 orr r3, r3, #(L1_S_DOM(PMAP_DOMAIN_KERNEL)) 75 str r3, [r0], #4 /* note autoinc */ 76 77 /* etc, TBD... */ 78 79 /* 80 * Make domain control go full art. 81 */ 82 mov r0, #0xffffffff 83 mcr p15, 0, r0, c3, c0, 0 84 85 /* 86 * Now let's clean the cache again to make sure everything 87 * is in place. 88 * 89 * XXX: should this take into account the XScale cache clean bug? 90 */ 91 mov r3, #(IXM31_DCACHE_SIZE) 92 subs r3, r3, #32 931: 94 mcr p15, 0, r3, c7, c10, 2 95 subs r3, r3, #32 96 bne 1b 97 CPWAIT(r3) 98 99 /* Drain write buffer */ 100 mcr p15, 0, r6, c7, c10, 4 101 102 /* Invalidate TLBs just to be sure */ 103 mcr p15, 0, r0, c8, c7, 0 104 105 /* 106 * You are standing at the gate to NetBSD. --More-- 107 * Unspeakable cruelty and harm lurk down there. --More-- 108 * Are you sure you want to enter? 109 */ 110 adr r8, .Lstart 111 ldr r8, [r8] 112 mov pc, r8 /* So be it */ 113 114/* symbol to use for address calculation in the right VA */ 115.Lstart: 116 .word start 117 118 119/* 120 * Calculate size of kernel to copy. Don't bother to copy bss, 121 * although I guess the CPU could use the warmup exercise ... 122 */ 123.Lcopy_size: 124 .word _edata - _C_LABEL(imx31lk_start) 125 126