1 /* $NetBSD: plcom_ifpga.c,v 1.16 2013/02/19 10:57:10 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* Interface to plcom (PL010) serial driver. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: plcom_ifpga.c,v 1.16 2013/02/19 10:57:10 skrll Exp $"); 36 37 #include <sys/types.h> 38 #include <sys/device.h> 39 #include <sys/systm.h> 40 #include <sys/param.h> 41 #include <sys/malloc.h> 42 43 #include <sys/termios.h> 44 45 #include <machine/intr.h> 46 #include <sys/bus.h> 47 48 #include <evbarm/dev/plcomreg.h> 49 #include <evbarm/dev/plcomvar.h> 50 51 #include <evbarm/ifpga/plcom_ifpgavar.h> 52 53 #include <evbarm/ifpga/ifpgareg.h> 54 #include <evbarm/ifpga/ifpgavar.h> 55 56 static int plcom_ifpga_match(device_t, cfdata_t, void *); 57 static void plcom_ifpga_attach(device_t, device_t, void *); 58 static void plcom_ifpga_set_mcr(void *, int, u_int); 59 60 CFATTACH_DECL_NEW(plcom_ifpga, sizeof(struct plcom_ifpga_softc), 61 plcom_ifpga_match, plcom_ifpga_attach, NULL, NULL); 62 63 static int 64 plcom_ifpga_match(device_t parent, cfdata_t cf, void *aux) 65 { 66 return 1; 67 } 68 69 static void 70 plcom_ifpga_attach(device_t parent, device_t self, void *aux) 71 { 72 struct plcom_ifpga_softc *isc = device_private(self); 73 struct plcom_softc *sc = &isc->sc_plcom; 74 struct ifpga_attach_args *ifa = aux; 75 76 isc->sc_iot = ifa->ifa_iot; 77 isc->sc_ioh = ifa->ifa_sc_ioh; 78 79 sc->sc_dev = self; 80 #if defined(INTEGRATOR_CP) 81 sc->sc_pi.pi_type = PLCOM_TYPE_PL011; 82 #else 83 sc->sc_pi.pi_type = PLCOM_TYPE_PL010; 84 #endif 85 sc->sc_pi.pi_iot = ifa->ifa_iot; 86 sc->sc_pi.pi_iobase = ifa->ifa_addr; 87 sc->sc_pi.pi_size = IFPGA_UART_SIZE; 88 sc->sc_frequency = IFPGA_UART_CLK; 89 sc->sc_hwflags = 0; 90 sc->sc_swflags = 0; 91 sc->sc_set_mcr = plcom_ifpga_set_mcr; 92 sc->sc_set_mcr_arg = (void *)isc; 93 94 if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, IFPGA_UART_SIZE, 0, 95 &sc->sc_pi.pi_ioh)) { 96 printf("%s: unable to map device\n", device_xname(sc->sc_dev)); 97 return; 98 } 99 100 plcom_attach_subr(sc); 101 isc->sc_ih = ifpga_intr_establish(ifa->ifa_irq, IPL_SERIAL, 102 plcomintr, sc); 103 if (isc->sc_ih == NULL) 104 panic("%s: cannot install interrupt handler", 105 device_xname(sc->sc_dev)); 106 } 107 108 static void plcom_ifpga_set_mcr(void *aux, int unit, u_int mcr) 109 { 110 struct plcom_ifpga_softc *isc = aux; 111 u_int set, clr; 112 113 set = clr = 0; 114 115 switch (unit) { 116 case 0: 117 if (mcr & PL01X_MCR_RTS) 118 set |= IFPGA_SC_CTRL_UART0RTS; 119 else 120 clr |= IFPGA_SC_CTRL_UART0RTS; 121 if (mcr & PL01X_MCR_DTR) 122 set |= IFPGA_SC_CTRL_UART0DTR; 123 else 124 clr |= IFPGA_SC_CTRL_UART0DTR; 125 case 1: 126 if (mcr & PL01X_MCR_RTS) 127 set |= IFPGA_SC_CTRL_UART1RTS; 128 else 129 clr |= IFPGA_SC_CTRL_UART1RTS; 130 if (mcr & PL01X_MCR_DTR) 131 set |= IFPGA_SC_CTRL_UART1DTR; 132 else 133 clr |= IFPGA_SC_CTRL_UART1DTR; 134 default: 135 return; 136 } 137 138 if (set) 139 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLS, 140 set); 141 if (clr) 142 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLC, 143 clr); 144 } 145