1 /* $NetBSD: plcom_ifpga.c,v 1.18 2021/07/27 21:13:41 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2001 ARM Ltd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /* Interface to plcom (PL010) serial driver. */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: plcom_ifpga.c,v 1.18 2021/07/27 21:13:41 skrll Exp $");
36
37 #include <sys/param.h>
38 #include <sys/types.h>
39
40 #include <sys/bus.h>
41 #include <sys/device.h>
42 #include <sys/systm.h>
43 #include <sys/termios.h>
44
45 #include <machine/intr.h>
46
47 #include <evbarm/dev/plcomreg.h>
48 #include <evbarm/dev/plcomvar.h>
49
50 #include <evbarm/ifpga/plcom_ifpgavar.h>
51
52 #include <evbarm/ifpga/ifpgareg.h>
53 #include <evbarm/ifpga/ifpgavar.h>
54
55 static int plcom_ifpga_match(device_t, cfdata_t, void *);
56 static void plcom_ifpga_attach(device_t, device_t, void *);
57 static void plcom_ifpga_set_mcr(void *, int, u_int);
58
59 CFATTACH_DECL_NEW(plcom_ifpga, sizeof(struct plcom_ifpga_softc),
60 plcom_ifpga_match, plcom_ifpga_attach, NULL, NULL);
61
62 static int
plcom_ifpga_match(device_t parent,cfdata_t cf,void * aux)63 plcom_ifpga_match(device_t parent, cfdata_t cf, void *aux)
64 {
65 return 1;
66 }
67
68 static void
plcom_ifpga_attach(device_t parent,device_t self,void * aux)69 plcom_ifpga_attach(device_t parent, device_t self, void *aux)
70 {
71 struct plcom_ifpga_softc *isc = device_private(self);
72 struct plcom_softc *sc = &isc->sc_plcom;
73 struct ifpga_attach_args *ifa = aux;
74
75 isc->sc_iot = ifa->ifa_iot;
76 isc->sc_ioh = ifa->ifa_sc_ioh;
77
78 sc->sc_dev = self;
79 #if defined(INTEGRATOR_CP)
80 sc->sc_pi.pi_type = PLCOM_TYPE_PL011;
81 #else
82 sc->sc_pi.pi_type = PLCOM_TYPE_PL010;
83 #endif
84 sc->sc_pi.pi_iot = ifa->ifa_iot;
85 sc->sc_pi.pi_iobase = ifa->ifa_addr;
86 sc->sc_pi.pi_size = IFPGA_UART_SIZE;
87 sc->sc_frequency = IFPGA_UART_CLK;
88 sc->sc_hwflags = 0;
89 sc->sc_swflags = 0;
90 sc->sc_set_mcr = plcom_ifpga_set_mcr;
91 sc->sc_set_mcr_arg = (void *)isc;
92
93 if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, IFPGA_UART_SIZE, 0,
94 &sc->sc_pi.pi_ioh)) {
95 printf("%s: unable to map device\n", device_xname(sc->sc_dev));
96 return;
97 }
98
99 aprint_naive("\n");
100 aprint_normal("\n");
101
102 plcom_attach_subr(sc);
103 isc->sc_ih = ifpga_intr_establish(ifa->ifa_irq, IPL_SERIAL,
104 plcomintr, sc);
105 if (isc->sc_ih == NULL)
106 panic("%s: cannot install interrupt handler",
107 device_xname(sc->sc_dev));
108 }
109
plcom_ifpga_set_mcr(void * aux,int unit,u_int mcr)110 static void plcom_ifpga_set_mcr(void *aux, int unit, u_int mcr)
111 {
112 struct plcom_ifpga_softc *isc = aux;
113 u_int set, clr;
114
115 set = clr = 0;
116
117 switch (unit) {
118 case 0:
119 if (mcr & PL01X_MCR_RTS)
120 set |= IFPGA_SC_CTRL_UART0RTS;
121 else
122 clr |= IFPGA_SC_CTRL_UART0RTS;
123 if (mcr & PL01X_MCR_DTR)
124 set |= IFPGA_SC_CTRL_UART0DTR;
125 else
126 clr |= IFPGA_SC_CTRL_UART0DTR;
127 case 1:
128 if (mcr & PL01X_MCR_RTS)
129 set |= IFPGA_SC_CTRL_UART1RTS;
130 else
131 clr |= IFPGA_SC_CTRL_UART1RTS;
132 if (mcr & PL01X_MCR_DTR)
133 set |= IFPGA_SC_CTRL_UART1DTR;
134 else
135 clr |= IFPGA_SC_CTRL_UART1DTR;
136 default:
137 return;
138 }
139
140 if (set)
141 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLS,
142 set);
143 if (clr)
144 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLC,
145 clr);
146 }
147