xref: /netbsd-src/sys/arch/arm/xscale/pxa2x0_ohci.c (revision 8ecbf5f02b752fcb7debe1a8fab1dc82602bc760)
1 /*	$NetBSD: pxa2x0_ohci.c,v 1.11 2018/04/09 16:21:09 jakllsch Exp $	*/
2 /*	$OpenBSD: pxa2x0_ohci.c,v 1.19 2005/04/08 02:32:54 dlg Exp $ */
3 
4 /*
5  * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <sys/param.h>
21 #include <sys/systm.h>
22 #include <sys/device.h>
23 #include <sys/kernel.h>
24 
25 #include <machine/intr.h>
26 #include <sys/bus.h>
27 
28 #include <dev/usb/usb.h>
29 #include <dev/usb/usbdi.h>
30 #include <dev/usb/usbdivar.h>
31 #include <dev/usb/usb_mem.h>
32 
33 #include <dev/usb/ohcireg.h>
34 #include <dev/usb/ohcivar.h>
35 
36 #include <arm/xscale/pxa2x0cpu.h>
37 #include <arm/xscale/pxa2x0reg.h>
38 #include <arm/xscale/pxa2x0var.h>
39 #include <arm/xscale/pxa2x0_gpio.h>
40 
41 struct pxaohci_softc {
42 	ohci_softc_t	sc;
43 
44 	void		*sc_ih;
45 };
46 
47 #if 0
48 static void	pxaohci_power(int, void *);
49 #endif
50 static void	pxaohci_enable(struct pxaohci_softc *);
51 static void	pxaohci_disable(struct pxaohci_softc *);
52 
53 #define	HREAD4(sc,r)	bus_space_read_4((sc)->sc.iot, (sc)->sc.ioh, (r))
54 #define	HWRITE4(sc,r,v)	bus_space_write_4((sc)->sc.iot, (sc)->sc.ioh, (r), (v))
55 
56 static int
57 pxaohci_match(device_t parent, struct cfdata *cf, void *aux)
58 {
59 	struct pxaip_attach_args *pxa = aux;
60 
61 	if (CPU_IS_PXA270 && strcmp(pxa->pxa_name, cf->cf_name) == 0) {
62 		pxa->pxa_size = PXA2X0_USBHC_SIZE;
63 		return 1;
64 	}
65 	return 0;
66 }
67 
68 static void
69 pxaohci_attach(device_t parent, device_t self, void *aux)
70 {
71 	struct pxaohci_softc *sc = device_private(self);
72 	struct pxaip_attach_args *pxa = aux;
73 
74 #ifdef USB_DEBUG
75 	{
76 		//extern int ohcidebug;
77 		//ohcidebug = 16;
78 	}
79 #endif
80 
81 	sc->sc.iot = pxa->pxa_iot;
82 	sc->sc.sc_bus.ub_dmatag = pxa->pxa_dmat;
83 	sc->sc.sc_size = 0;
84 	sc->sc_ih = NULL;
85 	sc->sc.sc_dev = self;
86 	sc->sc.sc_bus.ub_hcpriv = sc;
87 
88 	aprint_normal("\n");
89 	aprint_naive("\n");
90 
91 	/* Map I/O space */
92 	if (bus_space_map(sc->sc.iot, pxa->pxa_addr, pxa->pxa_size, 0,
93 	    &sc->sc.ioh)) {
94 		aprint_error_dev(sc->sc.sc_dev, "couldn't map memory space\n");
95 		return;
96 	}
97 	sc->sc.sc_size = pxa->pxa_size;
98 
99 	/* XXX copied from ohci_pci.c. needed? */
100 	bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size,
101 	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
102 
103 	/* start the usb clock */
104 	pxa2x0_clkman_config(CKEN_USBHC, 1);
105 	pxaohci_enable(sc);
106 
107 	/* Disable interrupts, so we don't get any spurious ones. */
108 	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
109 	    OHCI_MIE);
110 
111 	sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_USBH1, IPL_USB,
112 	    ohci_intr, &sc->sc);
113 	if (sc->sc_ih == NULL) {
114 		aprint_error_dev(sc->sc.sc_dev,
115 		    "unable to establish interrupt\n");
116 		goto free_map;
117 	}
118 
119 	int err = ohci_init(&sc->sc);
120 	if (err) {
121 		aprint_error_dev(sc->sc.sc_dev, "init failed, error=%d\n", err);
122 		goto free_intr;
123 	}
124 
125 #if 0
126 	sc->sc.sc_powerhook = powerhook_establish(device_xname(sc->sc.sc_bus.bdev),
127 	    pxaohci_power, sc);
128 	if (sc->sc.sc_powerhook == NULL) {
129 		aprint_error_dev(sc->sc.sc_dev->sc_bus.bdev, "cannot establish powerhook\n");
130 	}
131 #endif
132 
133 	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
134 
135 	return;
136 
137 free_intr:
138 	pxa2x0_intr_disestablish(sc->sc_ih);
139 	sc->sc_ih = NULL;
140 free_map:
141 	pxaohci_disable(sc);
142 	pxa2x0_clkman_config(CKEN_USBHC, 0);
143 	bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
144 	sc->sc.sc_size = 0;
145 }
146 
147 static int
148 pxaohci_detach(device_t self, int flags)
149 {
150 	struct pxaohci_softc *sc = device_private(self);
151 	int error;
152 
153 	error = ohci_detach(&sc->sc, flags);
154 	if (error)
155 		return error;
156 
157 #if 0
158 	if (sc->sc.sc_powerhook) {
159 		powerhook_disestablish(sc->sc.sc_powerhook);
160 		sc->sc.sc_powerhook = NULL;
161 	}
162 #endif
163 
164 	if (sc->sc_ih) {
165 		pxa2x0_intr_disestablish(sc->sc_ih);
166 		sc->sc_ih = NULL;
167 	}
168 
169 	pxaohci_disable(sc);
170 
171 	/* stop clock */
172 	pxa2x0_clkman_config(CKEN_USBHC, 0);
173 
174 	if (sc->sc.sc_size) {
175 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
176 		sc->sc.sc_size = 0;
177 	}
178 
179 	return 0;
180 }
181 
182 #if 0
183 static void
184 pxaohci_power(int why, void *arg)
185 {
186 	struct pxaohci_softc *sc = (struct pxaohci_softc *)arg;
187 	int s;
188 
189 	s = splhardusb();
190 	sc->sc.sc_bus.ub_usepolling++;
191 	switch (why) {
192 	case PWR_STANDBY:
193 	case PWR_SUSPEND:
194 #if 0
195 		ohci_power(why, &sc->sc);
196 #endif
197 		pxa2x0_clkman_config(CKEN_USBHC, 0);
198 		break;
199 
200 	case PWR_RESUME:
201 		pxa2x0_clkman_config(CKEN_USBHC, 1);
202 		pxaohci_enable(sc);
203 #if 0
204 		ohci_power(why, &sc->sc);
205 #endif
206 		break;
207 	}
208 	sc->sc.sc_bus.ub_usepolling--;
209 	splx(s);
210 }
211 #endif
212 
213 static void
214 pxaohci_enable(struct pxaohci_softc *sc)
215 {
216 	uint32_t hr;
217 
218 	/* Full host reset */
219 	hr = HREAD4(sc, USBHC_HR);
220 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
221 
222 	DELAY(USBHC_RST_WAIT);
223 
224 	hr = HREAD4(sc, USBHC_HR);
225 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
226 
227 	/* Force system bus interface reset */
228 	hr = HREAD4(sc, USBHC_HR);
229 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);
230 
231 	while (HREAD4(sc, USBHC_HR) & USBHC_HR_FSBIR)
232 		DELAY(3);
233 
234 	/* Enable the ports (physically only one, only enable that one?) */
235 	hr = HREAD4(sc, USBHC_HR);
236 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
237 	hr = HREAD4(sc, USBHC_HR);
238 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) &
239 			~(USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | USBHC_HR_SSEP3));
240 	HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE);
241 
242 	hr = HREAD4(sc, USBHC_UHCRHDA);
243 }
244 
245 static void
246 pxaohci_disable(struct pxaohci_softc *sc)
247 {
248 	uint32_t hr;
249 
250 	/* Full host reset */
251 	hr = HREAD4(sc, USBHC_HR);
252 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
253 
254 	DELAY(USBHC_RST_WAIT);
255 
256 	hr = HREAD4(sc, USBHC_HR);
257 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
258 }
259 
260 
261 CFATTACH_DECL2_NEW(pxaohci, sizeof(struct pxaohci_softc),
262     pxaohci_match, pxaohci_attach, pxaohci_detach, ohci_activate, NULL,
263     ohci_childdet);
264