1 /* $NetBSD: pxa2x0_ohci.c,v 1.13 2021/08/07 16:18:46 thorpej Exp $ */
2 /* $OpenBSD: pxa2x0_ohci.c,v 1.19 2005/04/08 02:32:54 dlg Exp $ */
3
4 /*
5 * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <sys/param.h>
21 #include <sys/systm.h>
22 #include <sys/device.h>
23 #include <sys/kernel.h>
24
25 #include <machine/intr.h>
26 #include <sys/bus.h>
27
28 #include <dev/usb/usb.h>
29 #include <dev/usb/usbdi.h>
30 #include <dev/usb/usbdivar.h>
31 #include <dev/usb/usb_mem.h>
32
33 #include <dev/usb/ohcireg.h>
34 #include <dev/usb/ohcivar.h>
35
36 #include <arm/xscale/pxa2x0cpu.h>
37 #include <arm/xscale/pxa2x0reg.h>
38 #include <arm/xscale/pxa2x0var.h>
39 #include <arm/xscale/pxa2x0_gpio.h>
40
41 struct pxaohci_softc {
42 ohci_softc_t sc;
43
44 void *sc_ih;
45 };
46
47 #if 0
48 static void pxaohci_power(int, void *);
49 #endif
50 static void pxaohci_enable(struct pxaohci_softc *);
51 static void pxaohci_disable(struct pxaohci_softc *);
52
53 #define HREAD4(sc,r) bus_space_read_4((sc)->sc.iot, (sc)->sc.ioh, (r))
54 #define HWRITE4(sc,r,v) bus_space_write_4((sc)->sc.iot, (sc)->sc.ioh, (r), (v))
55
56 static int
pxaohci_match(device_t parent,struct cfdata * cf,void * aux)57 pxaohci_match(device_t parent, struct cfdata *cf, void *aux)
58 {
59 struct pxaip_attach_args *pxa = aux;
60
61 if (CPU_IS_PXA270 && strcmp(pxa->pxa_name, cf->cf_name) == 0) {
62 pxa->pxa_size = PXA2X0_USBHC_SIZE;
63 return 1;
64 }
65 return 0;
66 }
67
68 static void
pxaohci_attach(device_t parent,device_t self,void * aux)69 pxaohci_attach(device_t parent, device_t self, void *aux)
70 {
71 struct pxaohci_softc *sc = device_private(self);
72 struct pxaip_attach_args *pxa = aux;
73
74 #ifdef USB_DEBUG
75 {
76 //extern int ohcidebug;
77 //ohcidebug = 16;
78 }
79 #endif
80
81 sc->sc.iot = pxa->pxa_iot;
82 sc->sc.sc_bus.ub_dmatag = pxa->pxa_dmat;
83 sc->sc.sc_size = 0;
84 sc->sc_ih = NULL;
85 sc->sc.sc_dev = self;
86 sc->sc.sc_bus.ub_hcpriv = sc;
87
88 aprint_normal("\n");
89 aprint_naive("\n");
90
91 /* Map I/O space */
92 if (bus_space_map(sc->sc.iot, pxa->pxa_addr, pxa->pxa_size, 0,
93 &sc->sc.ioh)) {
94 aprint_error_dev(sc->sc.sc_dev, "couldn't map memory space\n");
95 return;
96 }
97 sc->sc.sc_size = pxa->pxa_size;
98
99 /* XXX copied from ohci_pci.c. needed? */
100 bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size,
101 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
102
103 /* start the usb clock */
104 pxa2x0_clkman_config(CKEN_USBHC, 1);
105 pxaohci_enable(sc);
106
107 /* Disable interrupts, so we don't get any spurious ones. */
108 bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
109 OHCI_MIE);
110
111 sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_USBH1, IPL_USB,
112 ohci_intr, &sc->sc);
113 if (sc->sc_ih == NULL) {
114 aprint_error_dev(sc->sc.sc_dev,
115 "unable to establish interrupt\n");
116 goto free_map;
117 }
118
119 int err = ohci_init(&sc->sc);
120 if (err) {
121 aprint_error_dev(sc->sc.sc_dev, "init failed, error=%d\n", err);
122 goto free_intr;
123 }
124
125 #if 0
126 sc->sc.sc_powerhook = powerhook_establish(device_xname(sc->sc.sc_bus.bdev),
127 pxaohci_power, sc);
128 if (sc->sc.sc_powerhook == NULL) {
129 aprint_error_dev(sc->sc.sc_dev->sc_bus.bdev, "cannot establish powerhook\n");
130 }
131 #endif
132
133 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
134 CFARGS_NONE);
135
136 return;
137
138 free_intr:
139 pxa2x0_intr_disestablish(sc->sc_ih);
140 sc->sc_ih = NULL;
141 free_map:
142 pxaohci_disable(sc);
143 pxa2x0_clkman_config(CKEN_USBHC, 0);
144 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
145 sc->sc.sc_size = 0;
146 }
147
148 static int
pxaohci_detach(device_t self,int flags)149 pxaohci_detach(device_t self, int flags)
150 {
151 struct pxaohci_softc *sc = device_private(self);
152 int error;
153
154 error = ohci_detach(&sc->sc, flags);
155 if (error)
156 return error;
157
158 #if 0
159 if (sc->sc.sc_powerhook) {
160 powerhook_disestablish(sc->sc.sc_powerhook);
161 sc->sc.sc_powerhook = NULL;
162 }
163 #endif
164
165 if (sc->sc_ih) {
166 pxa2x0_intr_disestablish(sc->sc_ih);
167 sc->sc_ih = NULL;
168 }
169
170 pxaohci_disable(sc);
171
172 /* stop clock */
173 pxa2x0_clkman_config(CKEN_USBHC, 0);
174
175 if (sc->sc.sc_size) {
176 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
177 sc->sc.sc_size = 0;
178 }
179
180 return 0;
181 }
182
183 #if 0
184 static void
185 pxaohci_power(int why, void *arg)
186 {
187 struct pxaohci_softc *sc = (struct pxaohci_softc *)arg;
188 int s;
189
190 s = splhardusb();
191 sc->sc.sc_bus.ub_usepolling++;
192 switch (why) {
193 case PWR_STANDBY:
194 case PWR_SUSPEND:
195 #if 0
196 ohci_power(why, &sc->sc);
197 #endif
198 pxa2x0_clkman_config(CKEN_USBHC, 0);
199 break;
200
201 case PWR_RESUME:
202 pxa2x0_clkman_config(CKEN_USBHC, 1);
203 pxaohci_enable(sc);
204 #if 0
205 ohci_power(why, &sc->sc);
206 #endif
207 break;
208 }
209 sc->sc.sc_bus.ub_usepolling--;
210 splx(s);
211 }
212 #endif
213
214 static void
pxaohci_enable(struct pxaohci_softc * sc)215 pxaohci_enable(struct pxaohci_softc *sc)
216 {
217 uint32_t hr;
218
219 /* Full host reset */
220 hr = HREAD4(sc, USBHC_HR);
221 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
222
223 DELAY(USBHC_RST_WAIT);
224
225 hr = HREAD4(sc, USBHC_HR);
226 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
227
228 /* Force system bus interface reset */
229 hr = HREAD4(sc, USBHC_HR);
230 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);
231
232 while (HREAD4(sc, USBHC_HR) & USBHC_HR_FSBIR)
233 DELAY(3);
234
235 /* Enable the ports (physically only one, only enable that one?) */
236 hr = HREAD4(sc, USBHC_HR);
237 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
238 hr = HREAD4(sc, USBHC_HR);
239 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) &
240 ~(USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | USBHC_HR_SSEP3));
241 HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE);
242
243 hr = HREAD4(sc, USBHC_UHCRHDA);
244 }
245
246 static void
pxaohci_disable(struct pxaohci_softc * sc)247 pxaohci_disable(struct pxaohci_softc *sc)
248 {
249 uint32_t hr;
250
251 /* Full host reset */
252 hr = HREAD4(sc, USBHC_HR);
253 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
254
255 DELAY(USBHC_RST_WAIT);
256
257 hr = HREAD4(sc, USBHC_HR);
258 HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
259 }
260
261
262 CFATTACH_DECL2_NEW(pxaohci, sizeof(struct pxaohci_softc),
263 pxaohci_match, pxaohci_attach, pxaohci_detach, ohci_activate, NULL,
264 ohci_childdet);
265