1 /* $NetBSD: pxa2x0_ac97.c,v 1.20 2021/02/06 12:53:36 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 2003, 2005 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/select.h> 44 #include <sys/audioio.h> 45 #include <sys/kmem.h> 46 47 #include <machine/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/audio/audio_if.h> 51 #include <dev/ic/ac97reg.h> 52 #include <dev/ic/ac97var.h> 53 54 #include <arm/xscale/pxa2x0cpu.h> 55 #include <arm/xscale/pxa2x0reg.h> 56 #include <arm/xscale/pxa2x0var.h> 57 #include <arm/xscale/pxa2x0_gpio.h> 58 #include <arm/xscale/pxa2x0_dmac.h> 59 60 #include "locators.h" 61 62 struct acu_dma { 63 bus_dmamap_t ad_map; 64 void *ad_addr; 65 #define ACU_N_SEGS 1 /* XXX: We don't support > 1 */ 66 bus_dma_segment_t ad_segs[ACU_N_SEGS]; 67 int ad_nsegs; 68 size_t ad_size; 69 struct dmac_xfer *ad_dx; 70 struct acu_dma *ad_next; 71 }; 72 73 #define KERNADDR(ad) ((void *)((ad)->ad_addr)) 74 75 struct acu_softc { 76 device_t sc_dev; 77 bus_space_tag_t sc_bust; 78 bus_dma_tag_t sc_dmat; 79 bus_space_handle_t sc_bush; 80 void *sc_irqcookie; 81 int sc_in_reset; 82 u_int sc_dac_rate; 83 u_int sc_adc_rate; 84 85 /* List of DMA ring-buffers allocated by acu_malloc() */ 86 struct acu_dma *sc_dmas; 87 88 /* Dummy DMA segment which points to the AC97 PCM Fifo register */ 89 bus_dma_segment_t sc_dr; 90 91 /* PCM Output (Tx) state */ 92 dmac_peripheral_t sc_txp; 93 struct acu_dma *sc_txdma; 94 void (*sc_txfunc)(void *); 95 void *sc_txarg; 96 97 /* PCM Input (Rx) state */ 98 dmac_peripheral_t sc_rxp; 99 struct acu_dma *sc_rxdma; 100 void (*sc_rxfunc)(void *); 101 void *sc_rxarg; 102 103 /* AC97 Codec State */ 104 struct ac97_codec_if *sc_codec_if; 105 struct ac97_host_if sc_host_if; 106 107 /* Child audio(4) device */ 108 device_t sc_audiodev; 109 110 /* MPSAFE interfaces */ 111 kmutex_t sc_lock; 112 kmutex_t sc_intr_lock; 113 }; 114 115 static int pxaacu_match(device_t, cfdata_t, void *); 116 static void pxaacu_attach(device_t, device_t, void *); 117 118 CFATTACH_DECL_NEW(pxaacu, sizeof(struct acu_softc), 119 pxaacu_match, pxaacu_attach, NULL, NULL); 120 121 static int acu_codec_attach(void *, struct ac97_codec_if *); 122 static int acu_codec_read(void *, uint8_t, uint16_t *); 123 static int acu_codec_write(void *, uint8_t, uint16_t); 124 static int acu_codec_reset(void *); 125 static int acu_intr(void *); 126 127 static int acu_open(void *, int); 128 static void acu_close(void *); 129 static int acu_query_format(void *, audio_format_query_t *); 130 static int acu_set_format(void *, int, 131 const audio_params_t *, const audio_params_t *, 132 audio_filter_reg_t *, audio_filter_reg_t *); 133 static int acu_round_blocksize(void *, int, int, const audio_params_t *); 134 static int acu_halt_output(void *); 135 static int acu_halt_input(void *); 136 static int acu_trigger_output(void *, void *, void *, int, void (*)(void *), 137 void *, const audio_params_t *); 138 static int acu_trigger_input(void *, void *, void *, int, void (*)(void *), 139 void *, const audio_params_t *); 140 static void acu_tx_loop_segment(struct dmac_xfer *, int); 141 static void acu_rx_loop_segment(struct dmac_xfer *, int); 142 static int acu_getdev(void *, struct audio_device *); 143 static int acu_mixer_set_port(void *, mixer_ctrl_t *); 144 static int acu_mixer_get_port(void *, mixer_ctrl_t *); 145 static int acu_query_devinfo(void *, mixer_devinfo_t *); 146 static void *acu_malloc(void *, int, size_t); 147 static void acu_free(void *, void *, size_t); 148 static int acu_get_props(void *); 149 static void acu_get_locks(void *, kmutex_t **, kmutex_t **); 150 151 struct audio_hw_if acu_hw_if = { 152 .open = acu_open, 153 .close = acu_close, 154 .query_format = acu_query_format, 155 .set_format = acu_set_format, 156 .round_blocksize = acu_round_blocksize, 157 .halt_output = acu_halt_output, 158 .halt_input = acu_halt_input, 159 .getdev = acu_getdev, 160 .set_port = acu_mixer_set_port, 161 .get_port = acu_mixer_get_port, 162 .query_devinfo = acu_query_devinfo, 163 .allocm = acu_malloc, 164 .freem = acu_free, 165 .get_props = acu_get_props, 166 .trigger_output = acu_trigger_output, 167 .trigger_input = acu_trigger_input, 168 .get_locks = acu_get_locks, 169 }; 170 171 struct audio_device acu_device = { 172 "PXA250 AC97", 173 "", 174 "acu" 175 }; 176 177 static const struct audio_format acu_formats[] = { 178 { 179 .mode = AUMODE_PLAY | AUMODE_RECORD, 180 .encoding = AUDIO_ENCODING_SLINEAR_LE, 181 .validbits = 16, 182 .precision = 16, 183 .channels = 2, 184 .channel_mask = AUFMT_STEREO, 185 .frequency_type = 0, 186 /* XXX Need an accurate list of frequencies. */ 187 .frequency = { 4000, 48000 }, 188 }, 189 }; 190 #define ACU_NFORMATS (sizeof(acu_formats) / sizeof(struct audio_format)) 191 192 static inline uint32_t 193 acu_reg_read(struct acu_softc *sc, int reg) 194 { 195 196 return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)); 197 } 198 199 static inline void 200 acu_reg_write(struct acu_softc *sc, int reg, uint32_t val) 201 { 202 203 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val); 204 } 205 206 static inline int 207 acu_codec_ready(struct acu_softc *sc) 208 { 209 210 return (acu_reg_read(sc, AC97_GSR) & GSR_PCR); 211 } 212 213 static inline int 214 acu_wait_gsr(struct acu_softc *sc, uint32_t bit) 215 { 216 int timeout; 217 uint32_t rv; 218 219 for (timeout = 5000; timeout; timeout--) { 220 if ((rv = acu_reg_read(sc, AC97_GSR)) & bit) { 221 acu_reg_write(sc, AC97_GSR, rv | bit); 222 return (0); 223 } 224 delay(1); 225 } 226 227 return (1); 228 } 229 230 static int 231 pxaacu_match(device_t parent, cfdata_t cf, void *aux) 232 { 233 struct pxaip_attach_args *pxa = aux; 234 struct pxa2x0_gpioconf *gpioconf; 235 u_int gpio; 236 int i; 237 238 if (pxa->pxa_addr != PXA2X0_AC97_BASE || 239 pxa->pxa_intr != PXA2X0_INT_AC97) 240 return (0); 241 242 gpioconf = CPU_IS_PXA250 ? pxa25x_pxaacu_gpioconf : 243 pxa27x_pxaacu_gpioconf; 244 for (i = 0; gpioconf[i].pin != -1; i++) { 245 gpio = pxa2x0_gpio_get_function(gpioconf[i].pin); 246 if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) || 247 GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value)) 248 return (0); 249 } 250 251 pxa->pxa_size = PXA2X0_AC97_SIZE; 252 253 return (1); 254 } 255 256 static void 257 pxaacu_attach(device_t parent, device_t self, void *aux) 258 { 259 struct acu_softc *sc = device_private(self); 260 struct pxaip_attach_args *pxa = aux; 261 262 sc->sc_dev = self; 263 sc->sc_bust = pxa->pxa_iot; 264 sc->sc_dmat = pxa->pxa_dmat; 265 266 aprint_naive("\n"); 267 aprint_normal(": AC97 Controller\n"); 268 269 if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0, 270 &sc->sc_bush)) { 271 aprint_error_dev(self, "Can't map registers!\n"); 272 return; 273 } 274 275 sc->sc_irqcookie = pxa2x0_intr_establish(pxa->pxa_intr, IPL_AUDIO, 276 acu_intr, sc); 277 KASSERT(sc->sc_irqcookie != NULL); 278 279 /* Make sure the AC97 clock is enabled */ 280 pxa2x0_clkman_config(CKEN_AC97, true); 281 delay(100); 282 283 /* Do a cold reset */ 284 acu_reg_write(sc, AC97_GCR, 0); 285 delay(100); 286 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST); 287 delay(100); 288 acu_reg_write(sc, AC97_CAR, 0); 289 290 if (acu_wait_gsr(sc, GSR_PCR)) { 291 acu_reg_write(sc, AC97_GCR, 0); 292 delay(100); 293 pxa2x0_clkman_config(CKEN_AC97, false); 294 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size); 295 aprint_error_dev(self, "Primary codec not ready\n"); 296 return; 297 } 298 299 sc->sc_dr.ds_addr = pxa->pxa_addr + AC97_PCDR; 300 sc->sc_dr.ds_len = 4; 301 302 sc->sc_codec_if = NULL; 303 sc->sc_host_if.arg = sc; 304 sc->sc_host_if.attach = acu_codec_attach; 305 sc->sc_host_if.read = acu_codec_read; 306 sc->sc_host_if.write = acu_codec_write; 307 sc->sc_host_if.reset = acu_codec_reset; 308 sc->sc_host_if.flags = NULL; 309 sc->sc_in_reset = 0; 310 sc->sc_dac_rate = sc->sc_adc_rate = 0; 311 312 if (ac97_attach(&sc->sc_host_if, sc->sc_dev, &sc->sc_lock)) { 313 aprint_error_dev(self, "Failed to attach primary codec\n"); 314 acu_reg_write(sc, AC97_GCR, 0); 315 delay(100); 316 pxa2x0_clkman_config(CKEN_AC97, false); 317 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size); 318 return; 319 } 320 321 sc->sc_audiodev = audio_attach_mi(&acu_hw_if, sc, sc->sc_dev); 322 323 /* 324 * As a work-around for braindamage in the PXA250's AC97 controller 325 * (see errata #125), we hold the ACUNIT/Codec in Cold Reset until 326 * acu_open() is called. acu_close() also puts the controller into 327 * Cold Reset. 328 * 329 * While this won't necessarily prevent Rx FIFO overruns, it at least 330 * allows the user to recover by closing then re-opening the audio 331 * device. 332 */ 333 acu_reg_write(sc, AC97_GCR, 0); 334 sc->sc_in_reset = 1; 335 } 336 337 static int 338 acu_codec_attach(void *arg, struct ac97_codec_if *aci) 339 { 340 struct acu_softc *sc = arg; 341 342 sc->sc_codec_if = aci; 343 return (0); 344 } 345 346 static int 347 acu_codec_read(void *arg, uint8_t codec_reg, uint16_t *valp) 348 { 349 struct acu_softc *sc = arg; 350 uint32_t val; 351 int reg, rv = 1; 352 353 /* 354 * If we're currently closed, return non-zero. The ac97 frontend 355 * will use its cached copy of the register instead. 356 */ 357 if (sc->sc_in_reset) 358 return (1); 359 360 reg = AC97_CODEC_BASE(0) + codec_reg * 2; 361 362 mutex_spin_enter(&sc->sc_intr_lock); 363 364 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) 365 goto out_nocar; 366 367 val = acu_reg_read(sc, AC97_GSR); 368 val |= GSR_RDCS | GSR_SDONE; 369 acu_reg_write(sc, AC97_GSR, val); 370 371 /* 372 * Dummy read to initiate the real read access 373 */ 374 (void) acu_reg_read(sc, reg); 375 if (acu_wait_gsr(sc, GSR_SDONE)) 376 goto out; 377 378 (void) acu_reg_read(sc, reg); 379 if (acu_wait_gsr(sc, GSR_SDONE)) 380 goto out; 381 382 val = acu_reg_read(sc, AC97_GSR); 383 if (val & GSR_RDCS) 384 goto out; 385 386 *valp = acu_reg_read(sc, reg); 387 if (acu_wait_gsr(sc, GSR_SDONE)) 388 goto out; 389 390 rv = 0; 391 392 out: 393 acu_reg_write(sc, AC97_CAR, 0); 394 out_nocar: 395 mutex_spin_exit(&sc->sc_intr_lock); 396 delay(10); 397 return (rv); 398 } 399 400 static int 401 acu_codec_write(void *arg, uint8_t codec_reg, uint16_t val) 402 { 403 struct acu_softc *sc = arg; 404 uint16_t rv; 405 406 /* 407 * If we're currently closed, chances are the user is just 408 * tweaking mixer settings. Pretend the write succeeded. 409 * The ac97 frontend will cache the value anyway, and it'll 410 * be written correctly when the driver is opened. 411 */ 412 if (sc->sc_in_reset) 413 return (0); 414 415 mutex_spin_enter(&sc->sc_intr_lock); 416 417 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) { 418 mutex_spin_exit(&sc->sc_intr_lock); 419 return (1); 420 } 421 422 rv = acu_reg_read(sc, AC97_GSR); 423 rv |= GSR_RDCS | GSR_CDONE; 424 acu_reg_write(sc, AC97_GSR, rv); 425 426 acu_reg_write(sc, AC97_CODEC_BASE(0) + codec_reg * 2, val); 427 428 /* 429 * Wait for the write to complete 430 */ 431 (void) acu_wait_gsr(sc, GSR_CDONE); 432 acu_reg_write(sc, AC97_CAR, 0); 433 434 mutex_spin_exit(&sc->sc_intr_lock); 435 delay(10); 436 return (0); 437 } 438 439 static int 440 acu_codec_reset(void *arg) 441 { 442 struct acu_softc *sc = arg; 443 uint32_t rv; 444 445 rv = acu_reg_read(sc, AC97_GCR); 446 acu_reg_write(sc, AC97_GCR, rv | GCR_WARM_RST); 447 delay(100); 448 acu_reg_write(sc, AC97_GCR, rv); 449 delay(100); 450 451 if (acu_wait_gsr(sc, GSR_PCR)) { 452 aprint_error_dev(sc->sc_dev, 453 "acu_codec_reset: failed to ready after reset\n"); 454 return (ETIMEDOUT); 455 } 456 457 return (0); 458 } 459 460 static int 461 acu_intr(void *arg) 462 { 463 struct acu_softc *sc = arg; 464 uint32_t gsr, reg; 465 466 mutex_spin_enter(&sc->sc_intr_lock); 467 gsr = acu_reg_read(sc, AC97_GSR); 468 469 /* 470 * Tx FIFO underruns are no big deal. Just log it and ignore and 471 * subsequent underruns until the next time acu_trigger_output() 472 * is called. 473 */ 474 if ((gsr & GSR_POINT) && (acu_reg_read(sc, AC97_POCR) & AC97_FEFIE)) { 475 acu_reg_write(sc, AC97_POCR, 0); 476 reg = acu_reg_read(sc, AC97_POSR); 477 acu_reg_write(sc, AC97_POSR, reg); 478 aprint_error_dev(sc->sc_dev, "Tx PCM Fifo underrun\n"); 479 } 480 481 /* 482 * Rx FIFO overruns are a different story. See PAX250 Errata #125 483 * for the gory details. 484 * I don't see any way to gracefully recover from this problem, 485 * other than a issuing a Cold Reset in acu_close(). 486 * The best we can do here is to report the problem on the console. 487 */ 488 if ((gsr & GSR_PIINT) && (acu_reg_read(sc, AC97_PICR) & AC97_FEFIE)) { 489 acu_reg_write(sc, AC97_PICR, 0); 490 reg = acu_reg_read(sc, AC97_PISR); 491 acu_reg_write(sc, AC97_PISR, reg); 492 aprint_error_dev(sc->sc_dev, "Rx PCM Fifo overrun\n"); 493 } 494 495 mutex_spin_exit(&sc->sc_intr_lock); 496 497 return (1); 498 } 499 500 static int 501 acu_open(void *arg, int flags) 502 { 503 struct acu_softc *sc = arg; 504 505 /* 506 * Deassert Cold Reset 507 */ 508 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST); 509 delay(100); 510 acu_reg_write(sc, AC97_CAR, 0); 511 512 /* 513 * Wait for the primary codec to become ready 514 */ 515 if (acu_wait_gsr(sc, GSR_PCR)) 516 return (EIO); 517 sc->sc_in_reset = 0; 518 519 /* 520 * Restore the codec port settings 521 */ 522 sc->sc_codec_if->vtbl->restore_ports(sc->sc_codec_if); 523 524 /* 525 * Need to reprogram the sample rates, since 'restore_ports' 526 * doesn't do it. 527 * 528 * XXX: These aren't the only two sample rate registers ... 529 */ 530 if (sc->sc_dac_rate) 531 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 532 AC97_REG_PCM_FRONT_DAC_RATE, &sc->sc_dac_rate); 533 if (sc->sc_adc_rate) 534 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 535 AC97_REG_PCM_LR_ADC_RATE, &sc->sc_adc_rate); 536 537 return (0); 538 } 539 540 static void 541 acu_close(void *arg) 542 { 543 struct acu_softc *sc = arg; 544 545 /* 546 * Make sure the hardware is quiescent 547 */ 548 delay(100); 549 550 /* Assert Cold Reset */ 551 acu_reg_write(sc, AC97_GCR, 0); 552 sc->sc_in_reset = 1; 553 } 554 555 static int 556 acu_query_format(void *arg, audio_format_query_t *afp) 557 { 558 559 return audio_query_format(acu_formats, ACU_NFORMATS, afp); 560 } 561 562 static int 563 acu_set_format(void *arg, int setmode, 564 const audio_params_t *play, const audio_params_t *rec, 565 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 566 { 567 struct acu_softc *sc = arg; 568 int rate; 569 int err; 570 571 if ((setmode & AUMODE_PLAY)) { 572 rate = play->sample_rate; 573 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 574 AC97_REG_PCM_FRONT_DAC_RATE, &rate); 575 if (err) 576 return EINVAL; 577 sc->sc_dac_rate = play->sample_rate; 578 } 579 if ((setmode & AUMODE_RECORD)) { 580 rate = rec->sample_rate; 581 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if, 582 AC97_REG_PCM_LR_ADC_RATE, &rate); 583 if (err) 584 return EINVAL; 585 sc->sc_adc_rate = rec->sample_rate; 586 } 587 return 0; 588 } 589 590 static int 591 acu_round_blocksize(void *arg, int blk, int mode, const audio_params_t *param) 592 { 593 594 blk = (blk & ~0x1f); 595 if (blk < 0x20) 596 blk = 0x20; 597 return blk; 598 } 599 600 static int 601 acu_getdev(void *addr, struct audio_device *retp) 602 { 603 604 *retp = acu_device; 605 return (0); 606 } 607 608 static int 609 acu_mixer_set_port(void *arg, mixer_ctrl_t *cp) 610 { 611 struct acu_softc *sc = arg; 612 613 return (sc->sc_codec_if->vtbl->mixer_set_port(sc->sc_codec_if, cp)); 614 } 615 616 static int 617 acu_mixer_get_port(void *arg, mixer_ctrl_t *cp) 618 { 619 struct acu_softc *sc = arg; 620 621 return (sc->sc_codec_if->vtbl->mixer_get_port(sc->sc_codec_if, cp)); 622 } 623 624 static int 625 acu_query_devinfo(void *arg, mixer_devinfo_t *dip) 626 { 627 struct acu_softc *sc = arg; 628 629 return (sc->sc_codec_if->vtbl->query_devinfo(sc->sc_codec_if, dip)); 630 } 631 632 static void * 633 acu_malloc(void *arg, int direction, size_t size) 634 { 635 struct acu_softc *sc = arg; 636 struct acu_dma *ad; 637 int error; 638 639 ad = kmem_alloc(sizeof(*ad), KM_SLEEP); 640 641 /* XXX */ 642 if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer()) == NULL) 643 goto error; 644 645 ad->ad_size = size; 646 647 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs, 648 ACU_N_SEGS, &ad->ad_nsegs, BUS_DMA_WAITOK); 649 if (error) 650 goto free_xfer; 651 652 error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size, 653 &ad->ad_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 654 if (error) 655 goto free_dmamem; 656 657 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 658 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &ad->ad_map); 659 if (error) 660 goto unmap_dmamem; 661 662 error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size, 663 NULL, BUS_DMA_WAITOK); 664 if (error) { 665 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map); 666 unmap_dmamem: bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size); 667 free_dmamem: bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs); 668 free_xfer: pxa2x0_dmac_free_xfer(ad->ad_dx); 669 error: kmem_free(ad, sizeof(*ad)); 670 return (NULL); 671 } 672 673 ad->ad_dx->dx_cookie = sc; 674 ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH; 675 ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4; 676 ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32; 677 678 ad->ad_next = sc->sc_dmas; 679 sc->sc_dmas = ad; 680 return (KERNADDR(ad)); 681 } 682 683 static void 684 acu_free(void *arg, void *ptr, size_t size) 685 { 686 struct acu_softc *sc = arg; 687 struct acu_dma *ad, **adp; 688 689 for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) { 690 if (KERNADDR(ad) == ptr) { 691 pxa2x0_dmac_abort_xfer(ad->ad_dx); 692 pxa2x0_dmac_free_xfer(ad->ad_dx); 693 ad->ad_segs[0].ds_len = ad->ad_size; /* XXX */ 694 bus_dmamap_unload(sc->sc_dmat, ad->ad_map); 695 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map); 696 bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size); 697 bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs); 698 *adp = ad->ad_next; 699 kmem_free(ad, sizeof(*ad)); 700 return; 701 } 702 } 703 } 704 705 static int 706 acu_get_props(void *arg) 707 { 708 709 return (AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 710 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 711 } 712 713 static void 714 acu_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread) 715 { 716 struct acu_softc *sc = opaque; 717 718 *intr = &sc->sc_intr_lock; 719 *thread = &sc->sc_lock; 720 } 721 722 static int 723 acu_halt_output(void *arg) 724 { 725 struct acu_softc *sc = arg; 726 727 if (sc->sc_txdma) { 728 acu_reg_write(sc, AC97_POCR, 0); 729 acu_reg_write(sc, AC97_POSR, AC97_FIFOE); 730 pxa2x0_dmac_abort_xfer(sc->sc_txdma->ad_dx); 731 sc->sc_txdma = NULL; 732 } 733 return (0); 734 } 735 736 static int 737 acu_halt_input(void *arg) 738 { 739 struct acu_softc *sc = arg; 740 741 if (sc->sc_rxdma) { 742 acu_reg_write(sc, AC97_PICR, 0); 743 acu_reg_write(sc, AC97_PISR, AC97_FIFOE); 744 pxa2x0_dmac_abort_xfer(sc->sc_rxdma->ad_dx); 745 sc->sc_rxdma = NULL; 746 } 747 return (0); 748 } 749 750 static int 751 acu_trigger_output(void *arg, void *start, void *end, int blksize, 752 void (*tx_func)(void *), void *tx_arg, const audio_params_t *param) 753 { 754 struct acu_softc *sc = arg; 755 struct dmac_xfer *dx; 756 struct acu_dma *ad; 757 int rv; 758 759 if (sc->sc_txdma) 760 return (EBUSY); 761 762 sc->sc_txfunc = tx_func; 763 sc->sc_txarg = tx_arg; 764 765 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next) 766 ; 767 if (ad == NULL) { 768 printf("acu_trigger_output: bad addr %p\n", start); 769 return (EINVAL); 770 } 771 772 sc->sc_txdma = ad; 773 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr; 774 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start; 775 776 /* 777 * Fix up a looping DMA request. 778 * The 'done' function will be called for every 'blksize' bytes 779 * transferred by the DMA engine. 780 */ 781 dx = ad->ad_dx; 782 dx->dx_done = acu_tx_loop_segment; 783 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIOTX; 784 dx->dx_flow = DMAC_FLOW_CTRL_DEST; 785 dx->dx_loop_notify = blksize; 786 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false; 787 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs; 788 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs; 789 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true; 790 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 791 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr; 792 793 rv = pxa2x0_dmac_start_xfer(dx); 794 if (rv == 0) { 795 /* 796 * XXX: We should only do this once the request has been 797 * loaded into a DMAC channel. 798 */ 799 acu_reg_write(sc, AC97_POSR, AC97_FIFOE); 800 acu_reg_write(sc, AC97_POCR, AC97_FEFIE); 801 } 802 803 return (rv); 804 } 805 806 static int 807 acu_trigger_input(void *arg, void *start, void *end, int blksize, 808 void (*rx_func)(void *), void *rx_arg, const audio_params_t *param) 809 { 810 struct acu_softc *sc = arg; 811 struct dmac_xfer *dx; 812 struct acu_dma *ad; 813 int rv; 814 815 if (sc->sc_rxdma) 816 return (EBUSY); 817 818 sc->sc_rxfunc = rx_func; 819 sc->sc_rxarg = rx_arg; 820 821 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next) 822 ; 823 if (ad == NULL) { 824 printf("acu_trigger_input: bad addr %p\n", start); 825 return (EINVAL); 826 } 827 828 sc->sc_rxdma = ad; 829 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr; 830 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start; 831 832 /* 833 * Fix up a looping DMA request. 834 * The 'done' function will be called for every 'blksize' bytes 835 * transferred by the DMA engine. 836 */ 837 dx = ad->ad_dx; 838 dx->dx_done = acu_rx_loop_segment; 839 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIORX; 840 dx->dx_flow = DMAC_FLOW_CTRL_SRC; 841 dx->dx_loop_notify = blksize; 842 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false; 843 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs; 844 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs; 845 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true; 846 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 847 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr; 848 849 rv = pxa2x0_dmac_start_xfer(dx); 850 851 if (rv == 0) { 852 /* 853 * XXX: We should only do this once the request has been 854 * loaded into a DMAC channel. 855 */ 856 acu_reg_write(sc, AC97_PISR, AC97_FIFOE); 857 acu_reg_write(sc, AC97_PICR, AC97_FEFIE); 858 } 859 860 return (rv); 861 } 862 863 static void 864 acu_tx_loop_segment(struct dmac_xfer *dx, int status) 865 { 866 struct acu_softc *sc = dx->dx_cookie; 867 struct acu_dma *ad; 868 869 if ((ad = sc->sc_txdma) == NULL) 870 panic("acu_tx_loop_segment: bad TX dma descriptor!"); 871 872 if (ad->ad_dx != dx) 873 panic("acu_tx_loop_segment: xfer mismatch!"); 874 875 if (status) { 876 aprint_error_dev(sc->sc_dev, 877 "acu_tx_loop_segment: non-zero completion status %d\n", 878 status); 879 } 880 881 mutex_spin_enter(&sc->sc_intr_lock); 882 (sc->sc_txfunc)(sc->sc_txarg); 883 mutex_spin_exit(&sc->sc_intr_lock); 884 } 885 886 static void 887 acu_rx_loop_segment(struct dmac_xfer *dx, int status) 888 { 889 struct acu_softc *sc = dx->dx_cookie; 890 struct acu_dma *ad; 891 892 if ((ad = sc->sc_rxdma) == NULL) 893 panic("acu_rx_loop_segment: bad RX dma descriptor!"); 894 895 if (ad->ad_dx != dx) 896 panic("acu_rx_loop_segment: xfer mismatch!"); 897 898 if (status) { 899 aprint_error_dev(sc->sc_dev, 900 "acu_rx_loop_segment: non-zero completion status %d\n", 901 status); 902 } 903 904 mutex_spin_enter(&sc->sc_intr_lock); 905 (sc->sc_rxfunc)(sc->sc_rxarg); 906 mutex_spin_exit(&sc->sc_intr_lock); 907 } 908