1 /* $NetBSD: pxa2x0_ac97.c,v 1.21 2022/09/27 06:36:43 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2003, 2005 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41 #include <sys/kernel.h>
42 #include <sys/select.h>
43 #include <sys/audioio.h>
44 #include <sys/kmem.h>
45
46 #include <machine/intr.h>
47 #include <sys/bus.h>
48
49 #include <dev/audio/audio_if.h>
50 #include <dev/ic/ac97reg.h>
51 #include <dev/ic/ac97var.h>
52
53 #include <arm/xscale/pxa2x0cpu.h>
54 #include <arm/xscale/pxa2x0reg.h>
55 #include <arm/xscale/pxa2x0var.h>
56 #include <arm/xscale/pxa2x0_gpio.h>
57 #include <arm/xscale/pxa2x0_dmac.h>
58
59 #include "locators.h"
60
61 struct acu_dma {
62 bus_dmamap_t ad_map;
63 void *ad_addr;
64 #define ACU_N_SEGS 1 /* XXX: We don't support > 1 */
65 bus_dma_segment_t ad_segs[ACU_N_SEGS];
66 int ad_nsegs;
67 size_t ad_size;
68 struct dmac_xfer *ad_dx;
69 struct acu_dma *ad_next;
70 };
71
72 #define KERNADDR(ad) ((void *)((ad)->ad_addr))
73
74 struct acu_softc {
75 device_t sc_dev;
76 bus_space_tag_t sc_bust;
77 bus_dma_tag_t sc_dmat;
78 bus_space_handle_t sc_bush;
79 void *sc_irqcookie;
80 int sc_in_reset;
81 u_int sc_dac_rate;
82 u_int sc_adc_rate;
83
84 /* List of DMA ring-buffers allocated by acu_malloc() */
85 struct acu_dma *sc_dmas;
86
87 /* Dummy DMA segment which points to the AC97 PCM Fifo register */
88 bus_dma_segment_t sc_dr;
89
90 /* PCM Output (Tx) state */
91 dmac_peripheral_t sc_txp;
92 struct acu_dma *sc_txdma;
93 void (*sc_txfunc)(void *);
94 void *sc_txarg;
95
96 /* PCM Input (Rx) state */
97 dmac_peripheral_t sc_rxp;
98 struct acu_dma *sc_rxdma;
99 void (*sc_rxfunc)(void *);
100 void *sc_rxarg;
101
102 /* AC97 Codec State */
103 struct ac97_codec_if *sc_codec_if;
104 struct ac97_host_if sc_host_if;
105
106 /* Child audio(4) device */
107 device_t sc_audiodev;
108
109 /* MPSAFE interfaces */
110 kmutex_t sc_lock;
111 kmutex_t sc_intr_lock;
112 };
113
114 static int pxaacu_match(device_t, cfdata_t, void *);
115 static void pxaacu_attach(device_t, device_t, void *);
116
117 CFATTACH_DECL_NEW(pxaacu, sizeof(struct acu_softc),
118 pxaacu_match, pxaacu_attach, NULL, NULL);
119
120 static int acu_codec_attach(void *, struct ac97_codec_if *);
121 static int acu_codec_read(void *, uint8_t, uint16_t *);
122 static int acu_codec_write(void *, uint8_t, uint16_t);
123 static int acu_codec_reset(void *);
124 static int acu_intr(void *);
125
126 static int acu_open(void *, int);
127 static void acu_close(void *);
128 static int acu_query_format(void *, audio_format_query_t *);
129 static int acu_set_format(void *, int,
130 const audio_params_t *, const audio_params_t *,
131 audio_filter_reg_t *, audio_filter_reg_t *);
132 static int acu_round_blocksize(void *, int, int, const audio_params_t *);
133 static int acu_halt_output(void *);
134 static int acu_halt_input(void *);
135 static int acu_trigger_output(void *, void *, void *, int, void (*)(void *),
136 void *, const audio_params_t *);
137 static int acu_trigger_input(void *, void *, void *, int, void (*)(void *),
138 void *, const audio_params_t *);
139 static void acu_tx_loop_segment(struct dmac_xfer *, int);
140 static void acu_rx_loop_segment(struct dmac_xfer *, int);
141 static int acu_getdev(void *, struct audio_device *);
142 static int acu_mixer_set_port(void *, mixer_ctrl_t *);
143 static int acu_mixer_get_port(void *, mixer_ctrl_t *);
144 static int acu_query_devinfo(void *, mixer_devinfo_t *);
145 static void *acu_malloc(void *, int, size_t);
146 static void acu_free(void *, void *, size_t);
147 static int acu_get_props(void *);
148 static void acu_get_locks(void *, kmutex_t **, kmutex_t **);
149
150 struct audio_hw_if acu_hw_if = {
151 .open = acu_open,
152 .close = acu_close,
153 .query_format = acu_query_format,
154 .set_format = acu_set_format,
155 .round_blocksize = acu_round_blocksize,
156 .halt_output = acu_halt_output,
157 .halt_input = acu_halt_input,
158 .getdev = acu_getdev,
159 .set_port = acu_mixer_set_port,
160 .get_port = acu_mixer_get_port,
161 .query_devinfo = acu_query_devinfo,
162 .allocm = acu_malloc,
163 .freem = acu_free,
164 .get_props = acu_get_props,
165 .trigger_output = acu_trigger_output,
166 .trigger_input = acu_trigger_input,
167 .get_locks = acu_get_locks,
168 };
169
170 struct audio_device acu_device = {
171 "PXA250 AC97",
172 "",
173 "acu"
174 };
175
176 static const struct audio_format acu_formats[] = {
177 {
178 .mode = AUMODE_PLAY | AUMODE_RECORD,
179 .encoding = AUDIO_ENCODING_SLINEAR_LE,
180 .validbits = 16,
181 .precision = 16,
182 .channels = 2,
183 .channel_mask = AUFMT_STEREO,
184 .frequency_type = 0,
185 /* XXX Need an accurate list of frequencies. */
186 .frequency = { 4000, 48000 },
187 },
188 };
189 #define ACU_NFORMATS (sizeof(acu_formats) / sizeof(struct audio_format))
190
191 static inline uint32_t
acu_reg_read(struct acu_softc * sc,int reg)192 acu_reg_read(struct acu_softc *sc, int reg)
193 {
194
195 return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));
196 }
197
198 static inline void
acu_reg_write(struct acu_softc * sc,int reg,uint32_t val)199 acu_reg_write(struct acu_softc *sc, int reg, uint32_t val)
200 {
201
202 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
203 }
204
205 static inline int
acu_codec_ready(struct acu_softc * sc)206 acu_codec_ready(struct acu_softc *sc)
207 {
208
209 return (acu_reg_read(sc, AC97_GSR) & GSR_PCR);
210 }
211
212 static inline int
acu_wait_gsr(struct acu_softc * sc,uint32_t bit)213 acu_wait_gsr(struct acu_softc *sc, uint32_t bit)
214 {
215 int timeout;
216 uint32_t rv;
217
218 for (timeout = 5000; timeout; timeout--) {
219 if ((rv = acu_reg_read(sc, AC97_GSR)) & bit) {
220 acu_reg_write(sc, AC97_GSR, rv | bit);
221 return (0);
222 }
223 delay(1);
224 }
225
226 return (1);
227 }
228
229 static int
pxaacu_match(device_t parent,cfdata_t cf,void * aux)230 pxaacu_match(device_t parent, cfdata_t cf, void *aux)
231 {
232 struct pxaip_attach_args *pxa = aux;
233 struct pxa2x0_gpioconf *gpioconf;
234 u_int gpio;
235 int i;
236
237 if (pxa->pxa_addr != PXA2X0_AC97_BASE ||
238 pxa->pxa_intr != PXA2X0_INT_AC97)
239 return (0);
240
241 gpioconf = CPU_IS_PXA250 ? pxa25x_pxaacu_gpioconf :
242 pxa27x_pxaacu_gpioconf;
243 for (i = 0; gpioconf[i].pin != -1; i++) {
244 gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
245 if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
246 GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
247 return (0);
248 }
249
250 pxa->pxa_size = PXA2X0_AC97_SIZE;
251
252 return (1);
253 }
254
255 static void
pxaacu_attach(device_t parent,device_t self,void * aux)256 pxaacu_attach(device_t parent, device_t self, void *aux)
257 {
258 struct acu_softc *sc = device_private(self);
259 struct pxaip_attach_args *pxa = aux;
260
261 sc->sc_dev = self;
262 sc->sc_bust = pxa->pxa_iot;
263 sc->sc_dmat = pxa->pxa_dmat;
264
265 aprint_naive("\n");
266 aprint_normal(": AC97 Controller\n");
267
268 if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0,
269 &sc->sc_bush)) {
270 aprint_error_dev(self, "Can't map registers!\n");
271 return;
272 }
273
274 sc->sc_irqcookie = pxa2x0_intr_establish(pxa->pxa_intr, IPL_AUDIO,
275 acu_intr, sc);
276 KASSERT(sc->sc_irqcookie != NULL);
277
278 /* Make sure the AC97 clock is enabled */
279 pxa2x0_clkman_config(CKEN_AC97, true);
280 delay(100);
281
282 /* Do a cold reset */
283 acu_reg_write(sc, AC97_GCR, 0);
284 delay(100);
285 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
286 delay(100);
287 acu_reg_write(sc, AC97_CAR, 0);
288
289 if (acu_wait_gsr(sc, GSR_PCR)) {
290 acu_reg_write(sc, AC97_GCR, 0);
291 delay(100);
292 pxa2x0_clkman_config(CKEN_AC97, false);
293 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
294 aprint_error_dev(self, "Primary codec not ready\n");
295 return;
296 }
297
298 sc->sc_dr.ds_addr = pxa->pxa_addr + AC97_PCDR;
299 sc->sc_dr.ds_len = 4;
300
301 sc->sc_codec_if = NULL;
302 sc->sc_host_if.arg = sc;
303 sc->sc_host_if.attach = acu_codec_attach;
304 sc->sc_host_if.read = acu_codec_read;
305 sc->sc_host_if.write = acu_codec_write;
306 sc->sc_host_if.reset = acu_codec_reset;
307 sc->sc_host_if.flags = NULL;
308 sc->sc_in_reset = 0;
309 sc->sc_dac_rate = sc->sc_adc_rate = 0;
310
311 if (ac97_attach(&sc->sc_host_if, sc->sc_dev, &sc->sc_lock)) {
312 aprint_error_dev(self, "Failed to attach primary codec\n");
313 acu_reg_write(sc, AC97_GCR, 0);
314 delay(100);
315 pxa2x0_clkman_config(CKEN_AC97, false);
316 bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
317 return;
318 }
319
320 sc->sc_audiodev = audio_attach_mi(&acu_hw_if, sc, sc->sc_dev);
321
322 /*
323 * As a work-around for braindamage in the PXA250's AC97 controller
324 * (see errata #125), we hold the ACUNIT/Codec in Cold Reset until
325 * acu_open() is called. acu_close() also puts the controller into
326 * Cold Reset.
327 *
328 * While this won't necessarily prevent Rx FIFO overruns, it at least
329 * allows the user to recover by closing then re-opening the audio
330 * device.
331 */
332 acu_reg_write(sc, AC97_GCR, 0);
333 sc->sc_in_reset = 1;
334 }
335
336 static int
acu_codec_attach(void * arg,struct ac97_codec_if * aci)337 acu_codec_attach(void *arg, struct ac97_codec_if *aci)
338 {
339 struct acu_softc *sc = arg;
340
341 sc->sc_codec_if = aci;
342 return (0);
343 }
344
345 static int
acu_codec_read(void * arg,uint8_t codec_reg,uint16_t * valp)346 acu_codec_read(void *arg, uint8_t codec_reg, uint16_t *valp)
347 {
348 struct acu_softc *sc = arg;
349 uint32_t val;
350 int reg, rv = 1;
351
352 /*
353 * If we're currently closed, return non-zero. The ac97 frontend
354 * will use its cached copy of the register instead.
355 */
356 if (sc->sc_in_reset)
357 return (1);
358
359 reg = AC97_CODEC_BASE(0) + codec_reg * 2;
360
361 mutex_spin_enter(&sc->sc_intr_lock);
362
363 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP))
364 goto out_nocar;
365
366 val = acu_reg_read(sc, AC97_GSR);
367 val |= GSR_RDCS | GSR_SDONE;
368 acu_reg_write(sc, AC97_GSR, val);
369
370 /*
371 * Dummy read to initiate the real read access
372 */
373 (void) acu_reg_read(sc, reg);
374 if (acu_wait_gsr(sc, GSR_SDONE))
375 goto out;
376
377 (void) acu_reg_read(sc, reg);
378 if (acu_wait_gsr(sc, GSR_SDONE))
379 goto out;
380
381 val = acu_reg_read(sc, AC97_GSR);
382 if (val & GSR_RDCS)
383 goto out;
384
385 *valp = acu_reg_read(sc, reg);
386 if (acu_wait_gsr(sc, GSR_SDONE))
387 goto out;
388
389 rv = 0;
390
391 out:
392 acu_reg_write(sc, AC97_CAR, 0);
393 out_nocar:
394 mutex_spin_exit(&sc->sc_intr_lock);
395 delay(10);
396 return (rv);
397 }
398
399 static int
acu_codec_write(void * arg,uint8_t codec_reg,uint16_t val)400 acu_codec_write(void *arg, uint8_t codec_reg, uint16_t val)
401 {
402 struct acu_softc *sc = arg;
403 uint16_t rv;
404
405 /*
406 * If we're currently closed, chances are the user is just
407 * tweaking mixer settings. Pretend the write succeeded.
408 * The ac97 frontend will cache the value anyway, and it'll
409 * be written correctly when the driver is opened.
410 */
411 if (sc->sc_in_reset)
412 return (0);
413
414 mutex_spin_enter(&sc->sc_intr_lock);
415
416 if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) {
417 mutex_spin_exit(&sc->sc_intr_lock);
418 return (1);
419 }
420
421 rv = acu_reg_read(sc, AC97_GSR);
422 rv |= GSR_RDCS | GSR_CDONE;
423 acu_reg_write(sc, AC97_GSR, rv);
424
425 acu_reg_write(sc, AC97_CODEC_BASE(0) + codec_reg * 2, val);
426
427 /*
428 * Wait for the write to complete
429 */
430 (void) acu_wait_gsr(sc, GSR_CDONE);
431 acu_reg_write(sc, AC97_CAR, 0);
432
433 mutex_spin_exit(&sc->sc_intr_lock);
434 delay(10);
435 return (0);
436 }
437
438 static int
acu_codec_reset(void * arg)439 acu_codec_reset(void *arg)
440 {
441 struct acu_softc *sc = arg;
442 uint32_t rv;
443
444 rv = acu_reg_read(sc, AC97_GCR);
445 acu_reg_write(sc, AC97_GCR, rv | GCR_WARM_RST);
446 delay(100);
447 acu_reg_write(sc, AC97_GCR, rv);
448 delay(100);
449
450 if (acu_wait_gsr(sc, GSR_PCR)) {
451 aprint_error_dev(sc->sc_dev,
452 "acu_codec_reset: failed to ready after reset\n");
453 return (ETIMEDOUT);
454 }
455
456 return (0);
457 }
458
459 static int
acu_intr(void * arg)460 acu_intr(void *arg)
461 {
462 struct acu_softc *sc = arg;
463 uint32_t gsr, reg;
464
465 mutex_spin_enter(&sc->sc_intr_lock);
466 gsr = acu_reg_read(sc, AC97_GSR);
467
468 /*
469 * Tx FIFO underruns are no big deal. Just log it and ignore and
470 * subsequent underruns until the next time acu_trigger_output()
471 * is called.
472 */
473 if ((gsr & GSR_POINT) && (acu_reg_read(sc, AC97_POCR) & AC97_FEFIE)) {
474 acu_reg_write(sc, AC97_POCR, 0);
475 reg = acu_reg_read(sc, AC97_POSR);
476 acu_reg_write(sc, AC97_POSR, reg);
477 aprint_error_dev(sc->sc_dev, "Tx PCM Fifo underrun\n");
478 }
479
480 /*
481 * Rx FIFO overruns are a different story. See PAX250 Errata #125
482 * for the gory details.
483 * I don't see any way to gracefully recover from this problem,
484 * other than a issuing a Cold Reset in acu_close().
485 * The best we can do here is to report the problem on the console.
486 */
487 if ((gsr & GSR_PIINT) && (acu_reg_read(sc, AC97_PICR) & AC97_FEFIE)) {
488 acu_reg_write(sc, AC97_PICR, 0);
489 reg = acu_reg_read(sc, AC97_PISR);
490 acu_reg_write(sc, AC97_PISR, reg);
491 aprint_error_dev(sc->sc_dev, "Rx PCM Fifo overrun\n");
492 }
493
494 mutex_spin_exit(&sc->sc_intr_lock);
495
496 return (1);
497 }
498
499 static int
acu_open(void * arg,int flags)500 acu_open(void *arg, int flags)
501 {
502 struct acu_softc *sc = arg;
503
504 /*
505 * Deassert Cold Reset
506 */
507 acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
508 delay(100);
509 acu_reg_write(sc, AC97_CAR, 0);
510
511 /*
512 * Wait for the primary codec to become ready
513 */
514 if (acu_wait_gsr(sc, GSR_PCR))
515 return (EIO);
516 sc->sc_in_reset = 0;
517
518 /*
519 * Restore the codec port settings
520 */
521 sc->sc_codec_if->vtbl->restore_ports(sc->sc_codec_if);
522
523 /*
524 * Need to reprogram the sample rates, since 'restore_ports'
525 * doesn't do it.
526 *
527 * XXX: These aren't the only two sample rate registers ...
528 */
529 if (sc->sc_dac_rate)
530 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
531 AC97_REG_PCM_FRONT_DAC_RATE, &sc->sc_dac_rate);
532 if (sc->sc_adc_rate)
533 (void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
534 AC97_REG_PCM_LR_ADC_RATE, &sc->sc_adc_rate);
535
536 return (0);
537 }
538
539 static void
acu_close(void * arg)540 acu_close(void *arg)
541 {
542 struct acu_softc *sc = arg;
543
544 /*
545 * Make sure the hardware is quiescent
546 */
547 delay(100);
548
549 /* Assert Cold Reset */
550 acu_reg_write(sc, AC97_GCR, 0);
551 sc->sc_in_reset = 1;
552 }
553
554 static int
acu_query_format(void * arg,audio_format_query_t * afp)555 acu_query_format(void *arg, audio_format_query_t *afp)
556 {
557
558 return audio_query_format(acu_formats, ACU_NFORMATS, afp);
559 }
560
561 static int
acu_set_format(void * arg,int setmode,const audio_params_t * play,const audio_params_t * rec,audio_filter_reg_t * pfil,audio_filter_reg_t * rfil)562 acu_set_format(void *arg, int setmode,
563 const audio_params_t *play, const audio_params_t *rec,
564 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
565 {
566 struct acu_softc *sc = arg;
567 int rate;
568 int err;
569
570 if ((setmode & AUMODE_PLAY)) {
571 rate = play->sample_rate;
572 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
573 AC97_REG_PCM_FRONT_DAC_RATE, &rate);
574 if (err)
575 return EINVAL;
576 sc->sc_dac_rate = play->sample_rate;
577 }
578 if ((setmode & AUMODE_RECORD)) {
579 rate = rec->sample_rate;
580 err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
581 AC97_REG_PCM_LR_ADC_RATE, &rate);
582 if (err)
583 return EINVAL;
584 sc->sc_adc_rate = rec->sample_rate;
585 }
586 return 0;
587 }
588
589 static int
acu_round_blocksize(void * arg,int blk,int mode,const audio_params_t * param)590 acu_round_blocksize(void *arg, int blk, int mode, const audio_params_t *param)
591 {
592
593 blk = (blk & ~0x1f);
594 if (blk < 0x20)
595 blk = 0x20;
596 return blk;
597 }
598
599 static int
acu_getdev(void * addr,struct audio_device * retp)600 acu_getdev(void *addr, struct audio_device *retp)
601 {
602
603 *retp = acu_device;
604 return (0);
605 }
606
607 static int
acu_mixer_set_port(void * arg,mixer_ctrl_t * cp)608 acu_mixer_set_port(void *arg, mixer_ctrl_t *cp)
609 {
610 struct acu_softc *sc = arg;
611
612 return (sc->sc_codec_if->vtbl->mixer_set_port(sc->sc_codec_if, cp));
613 }
614
615 static int
acu_mixer_get_port(void * arg,mixer_ctrl_t * cp)616 acu_mixer_get_port(void *arg, mixer_ctrl_t *cp)
617 {
618 struct acu_softc *sc = arg;
619
620 return (sc->sc_codec_if->vtbl->mixer_get_port(sc->sc_codec_if, cp));
621 }
622
623 static int
acu_query_devinfo(void * arg,mixer_devinfo_t * dip)624 acu_query_devinfo(void *arg, mixer_devinfo_t *dip)
625 {
626 struct acu_softc *sc = arg;
627
628 return (sc->sc_codec_if->vtbl->query_devinfo(sc->sc_codec_if, dip));
629 }
630
631 static void *
acu_malloc(void * arg,int direction,size_t size)632 acu_malloc(void *arg, int direction, size_t size)
633 {
634 struct acu_softc *sc = arg;
635 struct acu_dma *ad;
636 int error;
637
638 ad = kmem_alloc(sizeof(*ad), KM_SLEEP);
639
640 /* XXX */
641 if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer()) == NULL)
642 goto error;
643
644 ad->ad_size = size;
645
646 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs,
647 ACU_N_SEGS, &ad->ad_nsegs, BUS_DMA_WAITOK);
648 if (error)
649 goto free_xfer;
650
651 error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size,
652 &ad->ad_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
653 if (error)
654 goto free_dmamem;
655
656 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
657 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &ad->ad_map);
658 if (error)
659 goto unmap_dmamem;
660
661 error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size,
662 NULL, BUS_DMA_WAITOK);
663 if (error) {
664 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
665 unmap_dmamem: bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size);
666 free_dmamem: bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
667 free_xfer: pxa2x0_dmac_free_xfer(ad->ad_dx);
668 error: kmem_free(ad, sizeof(*ad));
669 return (NULL);
670 }
671
672 ad->ad_dx->dx_cookie = sc;
673 ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH;
674 ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4;
675 ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32;
676
677 ad->ad_next = sc->sc_dmas;
678 sc->sc_dmas = ad;
679 return (KERNADDR(ad));
680 }
681
682 static void
acu_free(void * arg,void * ptr,size_t size)683 acu_free(void *arg, void *ptr, size_t size)
684 {
685 struct acu_softc *sc = arg;
686 struct acu_dma *ad, **adp;
687
688 for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) {
689 if (KERNADDR(ad) == ptr) {
690 pxa2x0_dmac_abort_xfer(ad->ad_dx);
691 pxa2x0_dmac_free_xfer(ad->ad_dx);
692 ad->ad_segs[0].ds_len = ad->ad_size; /* XXX */
693 bus_dmamap_unload(sc->sc_dmat, ad->ad_map);
694 bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
695 bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size);
696 bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
697 *adp = ad->ad_next;
698 kmem_free(ad, sizeof(*ad));
699 return;
700 }
701 }
702 }
703
704 static int
acu_get_props(void * arg)705 acu_get_props(void *arg)
706 {
707
708 return (AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE |
709 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX);
710 }
711
712 static void
acu_get_locks(void * opaque,kmutex_t ** intr,kmutex_t ** thread)713 acu_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread)
714 {
715 struct acu_softc *sc = opaque;
716
717 *intr = &sc->sc_intr_lock;
718 *thread = &sc->sc_lock;
719 }
720
721 static int
acu_halt_output(void * arg)722 acu_halt_output(void *arg)
723 {
724 struct acu_softc *sc = arg;
725
726 if (sc->sc_txdma) {
727 acu_reg_write(sc, AC97_POCR, 0);
728 acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
729 pxa2x0_dmac_abort_xfer(sc->sc_txdma->ad_dx);
730 sc->sc_txdma = NULL;
731 }
732 return (0);
733 }
734
735 static int
acu_halt_input(void * arg)736 acu_halt_input(void *arg)
737 {
738 struct acu_softc *sc = arg;
739
740 if (sc->sc_rxdma) {
741 acu_reg_write(sc, AC97_PICR, 0);
742 acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
743 pxa2x0_dmac_abort_xfer(sc->sc_rxdma->ad_dx);
744 sc->sc_rxdma = NULL;
745 }
746 return (0);
747 }
748
749 static int
acu_trigger_output(void * arg,void * start,void * end,int blksize,void (* tx_func)(void *),void * tx_arg,const audio_params_t * param)750 acu_trigger_output(void *arg, void *start, void *end, int blksize,
751 void (*tx_func)(void *), void *tx_arg, const audio_params_t *param)
752 {
753 struct acu_softc *sc = arg;
754 struct dmac_xfer *dx;
755 struct acu_dma *ad;
756 int rv;
757
758 if (sc->sc_txdma)
759 return (EBUSY);
760
761 sc->sc_txfunc = tx_func;
762 sc->sc_txarg = tx_arg;
763
764 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
765 ;
766 if (ad == NULL) {
767 printf("acu_trigger_output: bad addr %p\n", start);
768 return (EINVAL);
769 }
770
771 sc->sc_txdma = ad;
772 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
773 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
774
775 /*
776 * Fix up a looping DMA request.
777 * The 'done' function will be called for every 'blksize' bytes
778 * transferred by the DMA engine.
779 */
780 dx = ad->ad_dx;
781 dx->dx_done = acu_tx_loop_segment;
782 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIOTX;
783 dx->dx_flow = DMAC_FLOW_CTRL_DEST;
784 dx->dx_loop_notify = blksize;
785 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
786 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs;
787 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs;
788 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
789 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
790 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
791
792 rv = pxa2x0_dmac_start_xfer(dx);
793 if (rv == 0) {
794 /*
795 * XXX: We should only do this once the request has been
796 * loaded into a DMAC channel.
797 */
798 acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
799 acu_reg_write(sc, AC97_POCR, AC97_FEFIE);
800 }
801
802 return (rv);
803 }
804
805 static int
acu_trigger_input(void * arg,void * start,void * end,int blksize,void (* rx_func)(void *),void * rx_arg,const audio_params_t * param)806 acu_trigger_input(void *arg, void *start, void *end, int blksize,
807 void (*rx_func)(void *), void *rx_arg, const audio_params_t *param)
808 {
809 struct acu_softc *sc = arg;
810 struct dmac_xfer *dx;
811 struct acu_dma *ad;
812 int rv;
813
814 if (sc->sc_rxdma)
815 return (EBUSY);
816
817 sc->sc_rxfunc = rx_func;
818 sc->sc_rxarg = rx_arg;
819
820 for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
821 ;
822 if (ad == NULL) {
823 printf("acu_trigger_input: bad addr %p\n", start);
824 return (EINVAL);
825 }
826
827 sc->sc_rxdma = ad;
828 ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
829 ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
830
831 /*
832 * Fix up a looping DMA request.
833 * The 'done' function will be called for every 'blksize' bytes
834 * transferred by the DMA engine.
835 */
836 dx = ad->ad_dx;
837 dx->dx_done = acu_rx_loop_segment;
838 dx->dx_peripheral = DMAC_PERIPH_AC97AUDIORX;
839 dx->dx_flow = DMAC_FLOW_CTRL_SRC;
840 dx->dx_loop_notify = blksize;
841 dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
842 dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs;
843 dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs;
844 dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
845 dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
846 dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
847
848 rv = pxa2x0_dmac_start_xfer(dx);
849
850 if (rv == 0) {
851 /*
852 * XXX: We should only do this once the request has been
853 * loaded into a DMAC channel.
854 */
855 acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
856 acu_reg_write(sc, AC97_PICR, AC97_FEFIE);
857 }
858
859 return (rv);
860 }
861
862 static void
acu_tx_loop_segment(struct dmac_xfer * dx,int status)863 acu_tx_loop_segment(struct dmac_xfer *dx, int status)
864 {
865 struct acu_softc *sc = dx->dx_cookie;
866 struct acu_dma *ad;
867
868 if ((ad = sc->sc_txdma) == NULL)
869 panic("acu_tx_loop_segment: bad TX dma descriptor!");
870
871 if (ad->ad_dx != dx)
872 panic("acu_tx_loop_segment: xfer mismatch!");
873
874 if (status) {
875 aprint_error_dev(sc->sc_dev,
876 "acu_tx_loop_segment: non-zero completion status %d\n",
877 status);
878 }
879
880 mutex_spin_enter(&sc->sc_intr_lock);
881 (sc->sc_txfunc)(sc->sc_txarg);
882 mutex_spin_exit(&sc->sc_intr_lock);
883 }
884
885 static void
acu_rx_loop_segment(struct dmac_xfer * dx,int status)886 acu_rx_loop_segment(struct dmac_xfer *dx, int status)
887 {
888 struct acu_softc *sc = dx->dx_cookie;
889 struct acu_dma *ad;
890
891 if ((ad = sc->sc_rxdma) == NULL)
892 panic("acu_rx_loop_segment: bad RX dma descriptor!");
893
894 if (ad->ad_dx != dx)
895 panic("acu_rx_loop_segment: xfer mismatch!");
896
897 if (status) {
898 aprint_error_dev(sc->sc_dev,
899 "acu_rx_loop_segment: non-zero completion status %d\n",
900 status);
901 }
902
903 mutex_spin_enter(&sc->sc_intr_lock);
904 (sc->sc_rxfunc)(sc->sc_rxarg);
905 mutex_spin_exit(&sc->sc_intr_lock);
906 }
907