1 /* $NetBSD: sunxi_mmc.h,v 1.3 2017/09/11 22:00:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_SUNXI_MMC_H 30 #define _ARM_SUNXI_MMC_H 31 32 #define SUNXI_MMC_GCTRL 0x0000 33 #define SUNXI_MMC_CLKCR 0x0004 34 #define SUNXI_MMC_TIMEOUT 0x0008 35 #define SUNXI_MMC_WIDTH 0x000C 36 #define SUNXI_MMC_BLKSZ 0x0010 37 #define SUNXI_MMC_BYTECNT 0x0014 38 #define SUNXI_MMC_CMD 0x0018 39 #define SUNXI_MMC_ARG 0x001C 40 #define SUNXI_MMC_RESP0 0x0020 41 #define SUNXI_MMC_RESP1 0x0024 42 #define SUNXI_MMC_RESP2 0x0028 43 #define SUNXI_MMC_RESP3 0x002C 44 #define SUNXI_MMC_IMASK 0x0030 45 #define SUNXI_MMC_MINT 0x0034 46 #define SUNXI_MMC_RINT 0x0038 47 #define SUNXI_MMC_STATUS 0x003C 48 #define SUNXI_MMC_FTRGLEVEL 0x0040 49 #define SUNXI_MMC_FUNCSEL 0x0044 50 #define SUNXI_MMC_CBCR 0x0048 51 #define SUNXI_MMC_BBCR 0x004C 52 #define SUNXI_MMC_DBGC 0x0050 53 #define SUNXI_MMC_A12A 0x0058 /* A80 */ 54 #define SUNXI_MMC_NTSR 0x005C 55 #define SUNXI_MMC_HWRST 0x0078 /* A80 */ 56 #define SUNXI_MMC_DMAC 0x0080 57 #define SUNXI_MMC_DLBA 0x0084 58 #define SUNXI_MMC_IDST 0x0088 59 #define SUNXI_MMC_IDIE 0x008C 60 #define SUNXI_MMC_CHDA 0x0090 61 #define SUNXI_MMC_CBDA 0x0094 62 #define SUNXI_MMC_SAMP_DL 0x0144 63 64 #define SUNXI_MMC_GCTRL_ACCESS_BY_AHB __BIT(31) 65 #define SUNXI_MMC_GCTRL_WAIT_MEM_ACCESS_DONE __BIT(30) 66 #define SUNXI_MMC_GCTRL_DDR_MODE __BIT(10) 67 #define SUNXI_MMC_GCTRL_DEBOUNCEEN __BIT(8) 68 #define SUNXI_MMC_GCTRL_DMAEN __BIT(5) 69 #define SUNXI_MMC_GCTRL_INTEN __BIT(4) 70 #define SUNXI_MMC_GCTRL_DMARESET __BIT(2) 71 #define SUNXI_MMC_GCTRL_FIFORESET __BIT(1) 72 #define SUNXI_MMC_GCTRL_SOFTRESET __BIT(0) 73 #define SUNXI_MMC_GCTRL_RESET \ 74 (SUNXI_MMC_GCTRL_SOFTRESET | SUNXI_MMC_GCTRL_FIFORESET | \ 75 SUNXI_MMC_GCTRL_DMARESET) 76 #define SUNXI_MMC_CLKCR_MASK_DATA0 __BIT(31) 77 #define SUNXI_MMC_CLKCR_LOWPOWERON __BIT(17) 78 #define SUNXI_MMC_CLKCR_CARDCLKON __BIT(16) 79 #define SUNXI_MMC_CLKCR_DIV __BITS(7,0) 80 #define SUNXI_MMC_WIDTH_1 0 81 #define SUNXI_MMC_WIDTH_4 1 82 #define SUNXI_MMC_WIDTH_8 2 83 #define SUNXI_MMC_CMD_START __BIT(31) 84 #define SUNXI_MMC_CMD_USE_HOLD_REG __BIT(29) 85 #define SUNXI_MMC_CMD_VOL_SWITCH __BIT(28) 86 #define SUNXI_MMC_CMD_BOOT_ABORT __BIT(27) 87 #define SUNXI_MMC_CMD_BOOT_ACK_EXP __BIT(26) 88 #define SUNXI_MMC_CMD_ALT_BOOT_OPT __BIT(25) 89 #define SUNXI_MMC_CMD_ENBOOT __BIT(24) 90 #define SUNXI_MMC_CMD_CCS_EXP __BIT(23) 91 #define SUNXI_MMC_CMD_RD_CEATA_DEV __BIT(22) 92 #define SUNXI_MMC_CMD_UPCLK_ONLY __BIT(21) 93 #define SUNXI_MMC_CMD_SEND_INIT_SEQ __BIT(15) 94 #define SUNXI_MMC_CMD_STOP_ABORT_CMD __BIT(14) 95 #define SUNXI_MMC_CMD_WAIT_PRE_OVER __BIT(13) 96 #define SUNXI_MMC_CMD_SEND_AUTO_STOP __BIT(12) 97 #define SUNXI_MMC_CMD_SEQMOD __BIT(11) 98 #define SUNXI_MMC_CMD_WRITE __BIT(10) 99 #define SUNXI_MMC_CMD_DATA_EXP __BIT(9) 100 #define SUNXI_MMC_CMD_CHECK_RSP_CRC __BIT(8) 101 #define SUNXI_MMC_CMD_LONG_RSP __BIT(7) 102 #define SUNXI_MMC_CMD_RSP_EXP __BIT(6) 103 #define SUNXI_MMC_INT_CARD_REMOVE __BIT(31) 104 #define SUNXI_MMC_INT_CARD_INSERT __BIT(30) 105 #define SUNXI_MMC_INT_SDIO_INT __BIT(16) 106 #define SUNXI_MMC_INT_END_BIT_ERR __BIT(15) 107 #define SUNXI_MMC_INT_AUTO_CMD_DONE __BIT(14) 108 #define SUNXI_MMC_INT_START_BIT_ERR __BIT(13) 109 #define SUNXI_MMC_INT_HW_LOCKED __BIT(12) 110 #define SUNXI_MMC_INT_FIFO_RUN_ERR __BIT(11) 111 #define SUNXI_MMC_INT_VOL_CHG_DONE __BIT(10) 112 #define SUNXI_MMC_INT_DATA_STARVE __BIT(10) 113 #define SUNXI_MMC_INT_BOOT_START __BIT(9) 114 #define SUNXI_MMC_INT_DATA_TIMEOUT __BIT(9) 115 #define SUNXI_MMC_INT_ACK_RCV __BIT(8) 116 #define SUNXI_MMC_INT_RESP_TIMEOUT __BIT(8) 117 #define SUNXI_MMC_INT_DATA_CRC_ERR __BIT(7) 118 #define SUNXI_MMC_INT_RESP_CRC_ERR __BIT(6) 119 #define SUNXI_MMC_INT_RX_DATA_REQ __BIT(5) 120 #define SUNXI_MMC_INT_TX_DATA_REQ __BIT(4) 121 #define SUNXI_MMC_INT_DATA_OVER __BIT(3) 122 #define SUNXI_MMC_INT_CMD_DONE __BIT(2) 123 #define SUNXI_MMC_INT_RESP_ERR __BIT(1) 124 #define SUNXI_MMC_INT_ERROR \ 125 (SUNXI_MMC_INT_RESP_ERR | SUNXI_MMC_INT_RESP_CRC_ERR | \ 126 SUNXI_MMC_INT_DATA_CRC_ERR | SUNXI_MMC_INT_RESP_TIMEOUT | \ 127 SUNXI_MMC_INT_FIFO_RUN_ERR | SUNXI_MMC_INT_HW_LOCKED | \ 128 SUNXI_MMC_INT_START_BIT_ERR | SUNXI_MMC_INT_END_BIT_ERR) 129 #define SUNXI_MMC_STATUS_DMAREQ __BIT(31) 130 #define SUNXI_MMC_STATUS_DATA_FSM_BUSY __BIT(10) 131 #define SUNXI_MMC_STATUS_CARD_DATA_BUSY __BIT(9) 132 #define SUNXI_MMC_STATUS_CARD_PRESENT __BIT(8) 133 #define SUNXI_MMC_STATUS_FIFO_FULL __BIT(3) 134 #define SUNXI_MMC_STATUS_FIFO_EMPTY __BIT(2) 135 #define SUNXI_MMC_STATUS_TXWL_FLAG __BIT(1) 136 #define SUNXI_MMC_STATUS_RXWL_FLAG __BIT(0) 137 #define SUNXI_MMC_FUNCSEL_CEATA_DEV_INTEN __BIT(10) 138 #define SUNXI_MMC_FUNCSEL_SEND_AUTO_STOP_CCSD __BIT(9) 139 #define SUNXI_MMC_FUNCSEL_SEND_CCSD __BIT(8) 140 #define SUNXI_MMC_FUNCSEL_ABT_RD_DATA __BIT(2) 141 #define SUNXI_MMC_FUNCSEL_SDIO_RD_WAIT __BIT(1) 142 #define SUNXI_MMC_FUNCSEL_SEND_IRQ_RSP __BIT(0) 143 #define SUNXI_MMC_NTSR_MODE_SELECT __BIT(31) 144 #define SUNXI_MMC_NTSR_SAMPLE_PHASE __BITS(30,6) 145 #define SUNXI_MMC_NTSR_OUTPUT_PHASE __BITS(1,0) 146 #define SUNXI_MMC_DMAC_REFETCH_DES __BIT(31) 147 #define SUNXI_MMC_DMAC_IDMA_ON __BIT(7) 148 #define SUNXI_MMC_DMAC_FIX_BURST __BIT(1) 149 #define SUNXI_MMC_DMAC_SOFTRESET __BIT(0) 150 #define SUNXI_MMC_IDST_HOST_ABT __BIT(10) 151 #define SUNXI_MMC_IDST_ABNORMAL_INT_SUM __BIT(9) 152 #define SUNXI_MMC_IDST_NORMAL_INT_SUM __BIT(8) 153 #define SUNXI_MMC_IDST_CARD_ERR_SUM __BIT(5) 154 #define SUNXI_MMC_IDST_DES_INVALID __BIT(4) 155 #define SUNXI_MMC_IDST_FATAL_BUS_ERR __BIT(2) 156 #define SUNXI_MMC_IDST_RECEIVE_INT __BIT(1) 157 #define SUNXI_MMC_IDST_TRANSMIT_INT __BIT(0) 158 #define SUNXI_MMC_IDST_ERROR \ 159 (SUNXI_MMC_IDST_ABNORMAL_INT_SUM | SUNXI_MMC_IDST_CARD_ERR_SUM | \ 160 SUNXI_MMC_IDST_DES_INVALID | SUNXI_MMC_IDST_FATAL_BUS_ERR) 161 #define SUNXI_MMC_IDST_COMPLETE \ 162 (SUNXI_MMC_IDST_RECEIVE_INT | SUNXI_MMC_IDST_TRANSMIT_INT) 163 #define SUNXI_MMC_IDMA_CONFIG_DIC __BIT(1) 164 #define SUNXI_MMC_IDMA_CONFIG_LD __BIT(2) 165 #define SUNXI_MMC_IDMA_CONFIG_FD __BIT(3) 166 #define SUNXI_MMC_IDMA_CONFIG_CH __BIT(4) 167 #define SUNXI_MMC_IDMA_CONFIG_ER __BIT(5) 168 #define SUNXI_MMC_IDMA_CONFIG_CES __BIT(30) 169 #define SUNXI_MMC_IDMA_CONFIG_OWN __BIT(31) 170 #define SUNXI_MMC_SAMP_DL_SW_EN __BIT(7) 171 172 struct sunxi_mmc_idma_descriptor { 173 uint32_t dma_config; 174 #define SUNXI_MMC_IDMA_CONFIG_DIC __BIT(1) 175 #define SUNXI_MMC_IDMA_CONFIG_LD __BIT(2) 176 #define SUNXI_MMC_IDMA_CONFIG_FD __BIT(3) 177 #define SUNXI_MMC_IDMA_CONFIG_CH __BIT(4) 178 #define SUNXI_MMC_IDMA_CONFIG_ER __BIT(5) 179 #define SUNXI_MMC_IDMA_CONFIG_CES __BIT(30) 180 #define SUNXI_MMC_IDMA_CONFIG_OWN __BIT(31) 181 uint32_t dma_buf_size; 182 uint32_t dma_buf_addr; 183 uint32_t dma_next; 184 } __packed; 185 186 #endif /* _ARM_SUNXI_MMC_H */ 187