1 /* $NetBSD: sunxi_lradc.c,v 1.6 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2016, 2018 Manuel Bouyer
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: sunxi_lradc.c,v 1.6 2021/01/27 03:10:20 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/select.h>
39 #include <sys/mutex.h>
40 #include <sys/kmem.h>
41
42 #include <dev/sysmon/sysmonvar.h>
43 #include <dev/sysmon/sysmon_taskq.h>
44
45 #include <dev/fdt/fdtvar.h>
46
47 #include <arm/sunxi/sunxi_lradc.h>
48
49 struct sunxi_lradc_softc {
50 device_t sc_dev;
51 bus_space_tag_t sc_bst;
52 bus_space_handle_t sc_bsh;
53 kmutex_t sc_lock;
54 void *sc_ih;
55 struct fdtbus_regulator *sc_supply;
56 int sc_vref;
57 uint8_t sc_chans;
58 uint8_t sc_level[2][32];
59 const char *sc_name[2][32];
60 int sc_nlevels[2];
61 int sc_lastlevel[2];
62 struct sysmon_pswitch *sc_switches[2];
63 uint32_t sc_ints; /* pending interrupts */
64 };
65
66 #define ADC_READ(sc, reg) \
67 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
68 #define ADC_WRITE(sc, reg, val) \
69 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
70
71 static int sunxi_lradc_match(device_t, cfdata_t, void *);
72 static void sunxi_lradc_attach(device_t, device_t, void *);
73 static int sunxi_lradc_intr(void *);
74 static void sunxi_lradc_get_levels(struct sunxi_lradc_softc *, int, int);
75 static void sunxi_lradc_print_levels(struct sunxi_lradc_softc *, int);
76 static bool sunxi_lradc_register_switches(struct sunxi_lradc_softc *, int);
77
78 static const struct device_compatible_entry compat_data[] = {
79 { .compat = "allwinner,sun4i-a10-lradc-keys" },
80 DEVICE_COMPAT_EOL
81 };
82
83
84 CFATTACH_DECL_NEW(sunxi_lradc, sizeof(struct sunxi_lradc_softc),
85 sunxi_lradc_match, sunxi_lradc_attach, NULL, NULL);
86
87 static int
sunxi_lradc_match(device_t parent,cfdata_t cf,void * aux)88 sunxi_lradc_match(device_t parent, cfdata_t cf, void *aux)
89 {
90 struct fdt_attach_args * const faa = aux;
91
92 return of_compatible_match(faa->faa_phandle, compat_data);
93 }
94
95 static void
sunxi_lradc_attach(device_t parent,device_t self,void * aux)96 sunxi_lradc_attach(device_t parent, device_t self, void *aux)
97 {
98 struct sunxi_lradc_softc *sc = device_private(self);
99 struct fdt_attach_args * const faa = aux;
100 const int phandle = faa->faa_phandle;
101 int i, error;
102 uint32_t intc = 0;
103 bus_addr_t addr;
104 bus_size_t size;
105 char intrstr[128];
106 struct clk *clk;
107 struct fdtbus_reset *rst;
108
109 sc->sc_dev = self;
110 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
111
112 sc->sc_bst = faa->faa_bst;
113 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
114 aprint_error(": couldn't get registers\n");
115 return;
116 }
117
118 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
119 aprint_error(": couldn't map registers\n");
120 return;
121 }
122
123 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
124 aprint_error(": failed to decode interrupt\n");
125 return;
126 }
127
128 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) {
129 if (clk_enable(clk) != 0) {
130 aprint_error(": couldn't enable clock\n");
131 return;
132 }
133 }
134
135 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) {
136 if (fdtbus_reset_deassert(rst) != 0) {
137 aprint_error(": couldn't de-assert reset\n");
138 return;
139 }
140 }
141
142 sc->sc_chans = -1;
143 aprint_naive("\n");
144 aprint_normal(": LRADC, ");
145 if (of_hasprop(phandle, "vref-supply")) {
146 sc->sc_supply =
147 fdtbus_regulator_acquire(phandle, "vref-supply");
148 if (sc->sc_supply == NULL) {
149 aprint_error(": couldn't acquire vref-supply\n");
150 return;
151 }
152 } else {
153 aprint_normal("disabled (no vref-supply)\n");
154 return;
155 }
156 error = fdtbus_regulator_get_voltage(sc->sc_supply, &sc->sc_vref);
157 if (error) {
158 aprint_error(": couldn't get vref (%d)\n", error);
159 return;
160 }
161
162 for (i = 0; i < 2; i++)
163 sunxi_lradc_get_levels(sc, phandle, i);
164
165 switch (sc->sc_chans) {
166 case 0:
167 aprint_normal("channel 0 enabled\n");
168 break;
169 case 1:
170 aprint_normal("channel 1 enabled\n");
171 break;
172 case 2:
173 aprint_normal("channel 0 & 1 enabled\n");
174 break;
175 default:
176 aprint_normal("no channel enabled\n");
177 break;
178 }
179
180 if (sc->sc_chans == 0 || sc->sc_chans == 2) {
181 sunxi_lradc_print_levels(sc, 0);
182 }
183 if (sc->sc_chans == 1 || sc->sc_chans == 2) {
184 sunxi_lradc_print_levels(sc, 1);
185 }
186
187 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
188 FDT_INTR_MPSAFE, sunxi_lradc_intr, sc, device_xname(self));
189 if (sc->sc_ih == NULL) {
190 aprint_error_dev(self, "couldn't establish interrupt on %s\n",
191 intrstr);
192 return;
193 }
194 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
195 if (sc->sc_chans == 0 || sc->sc_chans == 2) {
196 if (!sunxi_lradc_register_switches(sc, 0)) {
197 aprint_error_dev(self, "can't register switches\n");
198 return;
199 }
200 }
201 if (sc->sc_chans == 1 || sc->sc_chans == 2) {
202 if (!sunxi_lradc_register_switches(sc, 1)) {
203 aprint_error_dev(self, "can't register switches\n");
204 return;
205 }
206 }
207
208 /*
209 * init and enable LRADC
210 * 250Hz, wait 2 cycles (8ms) on key press and release
211 */
212 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_LRADC_CTRL_REG,
213 (2 << AWIN_LRADC_CTRL_FIRSTCONV_SHIFT) |
214 (1 << AWIN_LRADC_CTRL_LV_A_B_CNT_SHIFT) |
215 AWIN_LRADC_CTRL_HOLD_EN |
216 AWIN_LRADC_CTRL_RATE_250 |
217 (sc->sc_chans << AWIN_LRADC_CTRL_CHAN_SHIFT) |
218 AWIN_LRADC_CTRL_EN);
219 switch(sc->sc_chans) {
220 case 0:
221 intc = AWIN_LRADC_INT_KEY0 | AWIN_LRADC_INT_KEYUP0;
222 break;
223 case 1:
224 intc = AWIN_LRADC_INT_KEY1 | AWIN_LRADC_INT_KEYUP1;
225 break;
226 case 2:
227 intc = AWIN_LRADC_INT_KEY0 | AWIN_LRADC_INT_KEYUP0 |
228 AWIN_LRADC_INT_KEY1 | AWIN_LRADC_INT_KEYUP1;
229 break;
230 }
231 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_LRADC_INTC_REG, intc);
232 }
233
234 static void
sunxi_lradc_get_levels(struct sunxi_lradc_softc * sc,int phandle,int chan)235 sunxi_lradc_get_levels(struct sunxi_lradc_softc *sc, int phandle, int chan)
236 {
237 int i;
238 int this_chan;
239 int child;
240 int32_t level;
241 const char *name;
242 const int vref = sc->sc_vref * 2 / 3;
243
244 for (child = OF_child(phandle), i = 0; child; child = OF_peer(child)) {
245 if (of_getprop_uint32(child, "channel", &this_chan) != 0)
246 continue;
247 if (this_chan != chan)
248 continue;
249 if (of_getprop_uint32(child, "voltage", &level) != 0)
250 continue;
251 name = fdtbus_get_string(child, "label");
252 if (name == NULL)
253 continue;
254 sc->sc_level[chan][i] = level * 63 / vref;
255 sc->sc_name[chan][i] = name;
256 i++;
257 }
258 if (i > 0) {
259 switch(chan) {
260 case 0:
261 if (sc->sc_chans == 1)
262 sc->sc_chans = 2;
263 else
264 sc->sc_chans = 0;
265 break;
266 case 1:
267 if (sc->sc_chans == 0)
268 sc->sc_chans = 2;
269 else
270 sc->sc_chans = 1;
271 break;
272 default:
273 panic("lradc: chan %d", chan);
274 }
275 sc->sc_nlevels[chan] = i;
276 }
277 }
278
279 static void
sunxi_lradc_print_levels(struct sunxi_lradc_softc * sc,int chan)280 sunxi_lradc_print_levels(struct sunxi_lradc_softc *sc, int chan)
281 {
282 int i;
283
284 aprint_verbose_dev(sc->sc_dev, ": channel %d levels", chan);
285 for (i = 0; i < 32; i++) {
286 if (sc->sc_name[chan][i] == NULL)
287 break;
288 aprint_verbose(" %d(%s)",
289 sc->sc_level[chan][i], sc->sc_name[chan][i]);
290 }
291 aprint_verbose("\n");
292 }
293
294 static bool
sunxi_lradc_register_switches(struct sunxi_lradc_softc * sc,int chan)295 sunxi_lradc_register_switches(struct sunxi_lradc_softc *sc, int chan)
296 {
297
298 KASSERT(sc->sc_nlevels[chan] > 0);
299 sc->sc_switches[chan] = kmem_zalloc(
300 sizeof(struct sysmon_pswitch) * sc->sc_nlevels[chan] , KM_SLEEP);
301
302 if (sc->sc_switches[chan] == NULL)
303 return false;
304
305 for (int i = 0; i < sc->sc_nlevels[chan]; i++) {
306 struct sysmon_pswitch *sw = &sc->sc_switches[chan][i];
307 sw->smpsw_name = sc->sc_name[chan][i];
308 sw->smpsw_type = PSWITCH_TYPE_HOTKEY;
309 sysmon_pswitch_register(sw);
310 }
311 return true;
312 }
313
314 static void
sunxi_lradc_intr_ev(struct sunxi_lradc_softc * sc,int chan,int event)315 sunxi_lradc_intr_ev(struct sunxi_lradc_softc *sc, int chan, int event)
316 {
317 int32_t val;
318 int diff = 64;
319
320
321 if (event == PSWITCH_EVENT_RELEASED) {
322 sysmon_pswitch_event(
323 &sc->sc_switches[chan][sc->sc_lastlevel[chan]], event);
324 return;
325 }
326
327 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
328 chan == 0 ? AWIN_LRADC_DATA0_REG : AWIN_LRADC_DATA1_REG);
329
330 KASSERT(sc->sc_nlevels[chan] > 0);
331 for (int i = 0; i < sc->sc_nlevels[chan]; i++) {
332 int curdiff;
333 curdiff = val - sc->sc_level[chan][i];
334 if (curdiff < 0)
335 curdiff = -curdiff;
336 if (diff > curdiff) {
337 diff = curdiff;
338 sc->sc_lastlevel[chan] = i;
339 }
340 }
341 sysmon_pswitch_event(
342 &sc->sc_switches[chan][sc->sc_lastlevel[chan]], event);
343 }
344
345 static void
sunxi_lradc_intr_task(void * arg)346 sunxi_lradc_intr_task(void *arg)
347 {
348 struct sunxi_lradc_softc *sc = arg;
349 mutex_enter(&sc->sc_lock);
350 if (sc->sc_chans == 0 || sc->sc_chans == 2) {
351 if (sc->sc_ints & AWIN_LRADC_INT_KEY0) {
352 sunxi_lradc_intr_ev(sc, 0, PSWITCH_EVENT_PRESSED);
353 }
354 if (sc->sc_ints & AWIN_LRADC_INT_KEYUP0) {
355 sunxi_lradc_intr_ev(sc, 0, PSWITCH_EVENT_RELEASED);
356 }
357 }
358 if (sc->sc_chans == 1 || sc->sc_chans == 2) {
359 if (sc->sc_ints & AWIN_LRADC_INT_KEY1) {
360 sunxi_lradc_intr_ev(sc, 1, PSWITCH_EVENT_PRESSED);
361 }
362 if (sc->sc_ints & AWIN_LRADC_INT_KEYUP1) {
363 sunxi_lradc_intr_ev(sc, 1, PSWITCH_EVENT_RELEASED);
364 }
365 }
366 sc->sc_ints = 0;
367 mutex_exit(&sc->sc_lock);
368 }
369
370 static int
sunxi_lradc_intr(void * arg)371 sunxi_lradc_intr(void *arg)
372 {
373 struct sunxi_lradc_softc *sc = arg;
374 int error;
375
376 mutex_enter(&sc->sc_lock);
377 sc->sc_ints = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
378 AWIN_LRADC_INTS_REG);
379 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_LRADC_INTS_REG,
380 sc->sc_ints);
381 mutex_exit(&sc->sc_lock);
382 error = sysmon_task_queue_sched(0, sunxi_lradc_intr_task, sc);
383 if (error != 0) {
384 printf("%s: sysmon_task_queue_sched failed (%d)\n",
385 device_xname(sc->sc_dev), error);
386 }
387 return 1;
388 }
389