1 /* $NetBSD: sunxi_gmacclk.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: sunxi_gmacclk.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/kmem.h>
36 #include <sys/bus.h>
37
38 #include <dev/clk/clk_backend.h>
39
40 #include <dev/fdt/fdtvar.h>
41
42 #define GMAC_CLK_PIT __BIT(2)
43 #define GMAC_CLK_PIT_MII 0
44 #define GMAC_CLK_PIT_RGMII 1
45 #define GMAC_CLK_SRC __BITS(1,0)
46 #define GMAC_CLK_SRC_MII 0
47 #define GMAC_CLK_SRC_EXT_RGMII 1
48 #define GMAC_CLK_SRC_RGMII 2
49
50 static int sunxi_gmacclk_match(device_t, cfdata_t, void *);
51 static void sunxi_gmacclk_attach(device_t, device_t, void *);
52
53 static struct clk *sunxi_gmacclk_decode(device_t, int, const void *, size_t);
54
55 static const struct fdtbus_clock_controller_func sunxi_gmacclk_fdt_funcs = {
56 .decode = sunxi_gmacclk_decode
57 };
58
59 static struct clk *sunxi_gmacclk_get(void *, const char *);
60 static void sunxi_gmacclk_put(void *, struct clk *);
61 static int sunxi_gmacclk_set_rate(void *, struct clk *, u_int);
62 static u_int sunxi_gmacclk_get_rate(void *, struct clk *);
63 static struct clk *sunxi_gmacclk_get_parent(void *, struct clk *);
64
65 static const struct clk_funcs sunxi_gmacclk_clk_funcs = {
66 .get = sunxi_gmacclk_get,
67 .put = sunxi_gmacclk_put,
68 .set_rate = sunxi_gmacclk_set_rate,
69 .get_rate = sunxi_gmacclk_get_rate,
70 .get_parent = sunxi_gmacclk_get_parent,
71 };
72
73 struct sunxi_gmacclk_softc {
74 device_t sc_dev;
75 int sc_phandle;
76 bus_space_tag_t sc_bst;
77 bus_space_handle_t sc_bsh;
78
79 struct clk_domain sc_clkdom;
80 struct clk sc_clk;
81 struct clk *sc_parent[2];
82 };
83
84 #define RD4(sc, reg) \
85 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
86 #define WR4(sc, reg, val) \
87 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
88
89 CFATTACH_DECL_NEW(sunxi_gmacclk, sizeof(struct sunxi_gmacclk_softc),
90 sunxi_gmacclk_match, sunxi_gmacclk_attach, NULL, NULL);
91
92 static const struct device_compatible_entry compat_data[] = {
93 { .compat = "allwinner,sun7i-a20-gmac-clk" },
94 DEVICE_COMPAT_EOL
95 };
96
97 static int
sunxi_gmacclk_match(device_t parent,cfdata_t cf,void * aux)98 sunxi_gmacclk_match(device_t parent, cfdata_t cf, void *aux)
99 {
100 const struct fdt_attach_args *faa = aux;
101
102 return of_compatible_match(faa->faa_phandle, compat_data);
103 }
104
105 static void
sunxi_gmacclk_attach(device_t parent,device_t self,void * aux)106 sunxi_gmacclk_attach(device_t parent, device_t self, void *aux)
107 {
108 struct sunxi_gmacclk_softc * const sc = device_private(self);
109 const struct fdt_attach_args *faa = aux;
110 const int phandle = faa->faa_phandle;
111 bus_addr_t addr;
112 bus_size_t size;
113
114 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
115 aprint_error(": couldn't get registers\n");
116 return;
117 }
118
119 sc->sc_dev = self;
120 sc->sc_phandle = phandle;
121 sc->sc_bst = faa->faa_bst;
122 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
123 aprint_error(": couldn't map registers\n");
124 return;
125 }
126 sc->sc_parent[0] = fdtbus_clock_get_index(phandle, 0);
127 sc->sc_parent[1] = fdtbus_clock_get_index(phandle, 1);
128 if (sc->sc_parent[0] == NULL || sc->sc_parent[1] == NULL) {
129 aprint_error(": couldn't get parent clocks\n");
130 return;
131 }
132
133 sc->sc_clkdom.funcs = &sunxi_gmacclk_clk_funcs;
134 sc->sc_clkdom.priv = sc;
135
136 sc->sc_clk.domain = &sc->sc_clkdom;
137 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
138
139 aprint_naive("\n");
140 aprint_normal(": GMAC MII/RGMII clock mux\n");
141
142 fdtbus_register_clock_controller(self, phandle, &sunxi_gmacclk_fdt_funcs);
143 }
144
145 static struct clk *
sunxi_gmacclk_decode(device_t dev,int cc_phandle,const void * data,size_t len)146 sunxi_gmacclk_decode(device_t dev, int cc_phandle, const void *data,
147 size_t len)
148 {
149 struct sunxi_gmacclk_softc * const sc = device_private(dev);
150
151 if (len != 0)
152 return NULL;
153
154 return &sc->sc_clk;
155 }
156
157 static struct clk *
sunxi_gmacclk_get(void * priv,const char * name)158 sunxi_gmacclk_get(void *priv, const char *name)
159 {
160 struct sunxi_gmacclk_softc * const sc = priv;
161
162 if (strcmp(name, sc->sc_clk.name) != 0)
163 return NULL;
164
165 return &sc->sc_clk;
166 }
167
168 static void
sunxi_gmacclk_put(void * priv,struct clk * clk)169 sunxi_gmacclk_put(void *priv, struct clk *clk)
170 {
171 }
172
173 static int
sunxi_gmacclk_set_rate(void * priv,struct clk * clk,u_int rate)174 sunxi_gmacclk_set_rate(void *priv, struct clk *clk, u_int rate)
175 {
176 struct sunxi_gmacclk_softc * const sc = priv;
177 uint32_t val;
178
179 val = RD4(sc, 0);
180 val &= ~(GMAC_CLK_PIT|GMAC_CLK_SRC);
181 if (rate == clk_get_rate(sc->sc_parent[GMAC_CLK_PIT_MII])) {
182 /* MII clock */
183 val |= __SHIFTIN(GMAC_CLK_PIT_MII, GMAC_CLK_PIT);
184 val |= __SHIFTIN(GMAC_CLK_SRC_MII, GMAC_CLK_SRC);
185 } else if (rate == clk_get_rate(sc->sc_parent[GMAC_CLK_PIT_RGMII])) {
186 /* RGMII clock */
187 val |= __SHIFTIN(GMAC_CLK_PIT_RGMII, GMAC_CLK_PIT);
188 val |= __SHIFTIN(GMAC_CLK_SRC_RGMII, GMAC_CLK_SRC);
189 } else {
190 return ENXIO;
191 }
192 WR4(sc, 0, val);
193
194 return 0;
195 }
196
197 static u_int
sunxi_gmacclk_get_rate(void * priv,struct clk * clk)198 sunxi_gmacclk_get_rate(void *priv, struct clk *clk)
199 {
200 struct clk *clk_parent = clk_get_parent(clk);
201
202 return clk_get_rate(clk_parent);
203 }
204
205 static struct clk *
sunxi_gmacclk_get_parent(void * priv,struct clk * clk)206 sunxi_gmacclk_get_parent(void *priv, struct clk *clk)
207 {
208 struct sunxi_gmacclk_softc * const sc = priv;
209 uint32_t val;
210 u_int sel;
211
212 val = RD4(sc, 0);
213 sel = __SHIFTOUT(val, GMAC_CLK_PIT);
214
215 return sc->sc_parent[sel];
216 }
217